compatible = "mediatek,mt7986-auxadc",
"mediatek,mt7622-auxadc";
reg = <0 0x1100d000 0 0x1000>;
- clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
- <&infracfg CLK_INFRA_ADC_FRC_CK>;
- clock-names = "main", "32k";
+ clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
+ clock-names = "main";
#io-channel-cells = <1>;
};
reg = <0 0x1100c800 0 0x800>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_THERM_CK>,
- <&infracfg CLK_INFRA_ADC_26M_CK>,
- <&infracfg CLK_INFRA_ADC_FRC_CK>;
- clock-names = "therm", "auxadc", "adc_32k";
+ <&infracfg CLK_INFRA_ADC_26M_CK>;
+ clock-names = "therm", "auxadc";
mediatek,auxadc = <&auxadc>;
mediatek,apmixedsys = <&apmixedsys>;
nvmem-cells = <&thermal_calibration>;
18),
GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "infra_sysaxi_d2",
19),
- GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "csw_f26m_sel", 20),
+ GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20),
GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m_sel", 21),
GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x_sel", 23),
/* INFRA2 */
+++ /dev/null
-From patchwork Wed Oct 19 14:37:35 2022
-Content-Type: text/plain; charset="utf-8"
-MIME-Version: 1.0
-Content-Transfer-Encoding: 7bit
-X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
-X-Patchwork-Id: 13011901
-Date: Wed, 19 Oct 2022 15:37:35 +0100
-From: Daniel Golle <daniel@makrotopia.org>
-To: Jonathan Cameron <jic23@kernel.org>,
- Lars-Peter Clausen <lars@metafoo.de>,
- Matthias Brugger <matthias.bgg@gmail.com>,
- linux-iio@vger.kernel.org
-Cc: David Bauer <mail@david-bauer.net>,
- Gwendal Grignou <gwendal@chromium.org>,
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
- linux-arm-kernel@lists.infradead.org,
- linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org
-Subject: [PATCH 1/2] iio: adc: mt6577_auxadc: add optional 32k clock
-Message-ID:
- <f98ed7f3fc15a0614443a57427d46ce17ec2e0cc.1666190235.git.daniel@makrotopia.org>
-MIME-Version: 1.0
-Content-Disposition: inline
-X-BeenThere: linux-mediatek@lists.infradead.org
-X-Mailman-Version: 2.1.34
-Precedence: list
-List-Id: <linux-mediatek.lists.infradead.org>
-
-MediaTek MT7986 and MT7981 require an additional clock to be brought up
-for AUXADC. Add support for that in the driver, similar to how it's
-done in MediaTek's SDK[1].
-
-[1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/refs/heads/master/target/linux/mediatek/patches-5.4/500-auxadc-add-auxadc-32k-clk.patch
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/iio/adc/mt6577_auxadc.c | 22 ++++++++++++++++++++++
- 1 file changed, 22 insertions(+)
-
---- a/drivers/iio/adc/mt6577_auxadc.c
-+++ b/drivers/iio/adc/mt6577_auxadc.c
-@@ -42,6 +42,7 @@ struct mtk_auxadc_compatible {
- struct mt6577_auxadc_device {
- void __iomem *reg_base;
- struct clk *adc_clk;
-+ struct clk *adc_32k_clk;
- struct mutex lock;
- const struct mtk_auxadc_compatible *dev_comp;
- };
-@@ -222,6 +223,12 @@ static int __maybe_unused mt6577_auxadc_
- return ret;
- }
-
-+ ret = clk_prepare_enable(adc_dev->adc_32k_clk);
-+ if (ret) {
-+ pr_err("failed to enable auxadc clock\n");
-+ return ret;
-+ }
-+
- mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
- MT6577_AUXADC_PDN_EN, 0);
- mdelay(MT6577_AUXADC_POWER_READY_MS);
-@@ -236,6 +243,8 @@ static int __maybe_unused mt6577_auxadc_
-
- mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
- 0, MT6577_AUXADC_PDN_EN);
-+
-+ clk_disable_unprepare(adc_dev->adc_32k_clk);
- clk_disable_unprepare(adc_dev->adc_clk);
-
- return 0;
-@@ -277,6 +286,17 @@ static int mt6577_auxadc_probe(struct pl
- return ret;
- }
-
-+ adc_dev->adc_32k_clk = devm_clk_get_optional(&pdev->dev, "32k");
-+ if (IS_ERR(adc_dev->adc_32k_clk)) {
-+ dev_err(&pdev->dev, "failed to get auxadc 32k clock\n");
-+ return PTR_ERR(adc_dev->adc_32k_clk);
-+ }
-+ ret = clk_prepare_enable(adc_dev->adc_32k_clk);
-+ if (ret) {
-+ dev_err(&pdev->dev, "failed to enable auxadc 32k clock\n");
-+ return ret;
-+ }
-+
- adc_clk_rate = clk_get_rate(adc_dev->adc_clk);
- if (!adc_clk_rate) {
- ret = -EINVAL;
-@@ -306,6 +326,7 @@ err_power_off:
- mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
- 0, MT6577_AUXADC_PDN_EN);
- err_disable_clk:
-+ clk_disable_unprepare(adc_dev->adc_32k_clk);
- clk_disable_unprepare(adc_dev->adc_clk);
- return ret;
- }
-@@ -320,6 +341,7 @@ static int mt6577_auxadc_remove(struct p
- mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
- 0, MT6577_AUXADC_PDN_EN);
-
-+ clk_disable_unprepare(adc_dev->adc_32k_clk);
- clk_disable_unprepare(adc_dev->adc_clk);
-
- return 0;
struct mtk_thermal;
struct thermal_bank_cfg {
-@@ -279,6 +316,7 @@ struct mtk_thermal {
-
- struct clk *clk_peri_therm;
- struct clk *clk_auxadc;
-+ struct clk *clk_adc_32k;
- /* lock: for getting and putting banks */
- struct mutex lock;
-
-@@ -386,6 +424,14 @@ static const int mt7622_mux_values[MT762
+@@ -386,6 +423,14 @@ static const int mt7622_mux_values[MT762
static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
/*
* The MT8173 thermal controller has four banks. Each bank can read up to
* four temperature sensors simultaneously. The MT8173 has a total of 5
-@@ -549,6 +595,30 @@ static const struct mtk_thermal_data mt8
+@@ -549,6 +594,30 @@ static const struct mtk_thermal_data mt8
.version = MTK_THERMAL_V1,
};
/**
* raw_to_mcelsius - convert a raw ADC value to mcelsius
* @mt: The thermal controller
-@@ -603,6 +673,22 @@ static int raw_to_mcelsius_v2(struct mtk
+@@ -603,6 +672,22 @@ static int raw_to_mcelsius_v2(struct mtk
return (format_2 - tmp) * 100;
}
/**
* mtk_thermal_get_bank - get bank
* @bank: The bank
-@@ -659,9 +745,12 @@ static int mtk_thermal_bank_temperature(
+@@ -659,9 +744,12 @@ static int mtk_thermal_bank_temperature(
if (mt->conf->version == MTK_THERMAL_V1) {
temp = raw_to_mcelsius_v1(
mt, conf->bank_data[bank->id].sensors[i], raw);
}
/*
-@@ -887,6 +976,26 @@ static int mtk_thermal_extract_efuse_v2(
+@@ -887,6 +975,26 @@ static int mtk_thermal_extract_efuse_v2(
return 0;
}
static int mtk_thermal_get_calibration_data(struct device *dev,
struct mtk_thermal *mt)
{
-@@ -897,6 +1006,7 @@ static int mtk_thermal_get_calibration_d
+@@ -897,6 +1005,7 @@ static int mtk_thermal_get_calibration_d
/* Start with default values */
mt->adc_ge = 512;
for (i = 0; i < mt->conf->num_sensors; i++)
mt->vts[i] = 260;
mt->degc_cali = 40;
-@@ -924,8 +1034,10 @@ static int mtk_thermal_get_calibration_d
+@@ -924,8 +1033,10 @@ static int mtk_thermal_get_calibration_d
if (mt->conf->version == MTK_THERMAL_V1)
ret = mtk_thermal_extract_efuse_v1(mt, buf);
if (ret) {
dev_info(dev, "Device not calibrated, using default calibration values\n");
-@@ -956,6 +1068,10 @@ static const struct of_device_id mtk_the
+@@ -956,6 +1067,10 @@ static const struct of_device_id mtk_the
.data = (void *)&mt7622_thermal_data,
},
{
.compatible = "mediatek,mt8183-thermal",
.data = (void *)&mt8183_thermal_data,
}, {
-@@ -1009,6 +1125,12 @@ static int mtk_thermal_probe(struct plat
- if (IS_ERR(mt->clk_auxadc))
- return PTR_ERR(mt->clk_auxadc);
-
-+ if (mt->conf->version == MTK_THERMAL_V3) {
-+ mt->clk_adc_32k = devm_clk_get(&pdev->dev, "adc_32k");
-+ if (IS_ERR(mt->clk_adc_32k))
-+ return PTR_ERR(mt->clk_adc_32k);
-+ }
-+
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- mt->thermal_base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(mt->thermal_base))
-@@ -1058,10 +1180,18 @@ static int mtk_thermal_probe(struct plat
- if (ret)
- return ret;
-
-+ if (mt->conf->version == MTK_THERMAL_V3) {
-+ ret = clk_prepare_enable(mt->clk_adc_32k);
-+ if (ret) {
-+ dev_err(&pdev->dev, "Can't enable auxadc 32k clk: %d\n", ret);
-+ return ret;
-+ }
-+ }
-+
- ret = clk_prepare_enable(mt->clk_auxadc);
- if (ret) {
- dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
-- return ret;
-+ goto err_disable_clk_adc_32k;
- }
-
- ret = clk_prepare_enable(mt->clk_peri_therm);
-@@ -1070,7 +1200,8 @@ static int mtk_thermal_probe(struct plat
+@@ -1070,7 +1185,8 @@ static int mtk_thermal_probe(struct plat
goto err_disable_clk_auxadc;
}
mtk_thermal_turn_on_buffer(apmixed_base);
mtk_thermal_release_periodic_ts(mt, auxadc_base);
}
-@@ -1099,6 +1230,9 @@ err_disable_clk_peri_therm:
- clk_disable_unprepare(mt->clk_peri_therm);
- err_disable_clk_auxadc:
- clk_disable_unprepare(mt->clk_auxadc);
-+err_disable_clk_adc_32k:
-+ if (mt->conf->version == MTK_THERMAL_V3)
-+ clk_disable_unprepare(mt->clk_adc_32k);
-
- return ret;
- }
-@@ -1110,6 +1244,9 @@ static int mtk_thermal_remove(struct pla
- clk_disable_unprepare(mt->clk_peri_therm);
- clk_disable_unprepare(mt->clk_auxadc);
-
-+ if (mt->conf->version == MTK_THERMAL_V3)
-+ clk_disable_unprepare(mt->clk_adc_32k);
-+
- return 0;
- }
-
projects / openwrt / staging / dangole.git / commitdiff