drm/amd/display: only include FEC overhead if both asic and display support FEC

[why]
Some asics don't support FEC but FEC overhead is added into link
bandwidth calculation by mistake. This causes certain timing cannot be
validated.

[how]
Only include FEC overhead if both asic and display support FEC.

Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Ashley Thomas <Ashley.Thomas2@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 549bea1d725c559e17af1e3fdbae2e26d9bbcc7a..951b43dde4e550a5674e0e3ab8c19a06ce67b039 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3406,7 +3406,7 @@ uint32_t dc_link_bandwidth_kbps(
        link_bw_kbps *= 8;   /* 8 bits per byte*/
        link_bw_kbps *= link_setting->lane_count;
 
-       if (link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
+       if (dc_link_is_fec_supported(link)) {
                /* Account for FEC overhead.
                 * We have to do it based on caps,
                 * and not based on FEC being set ready,
@@ -3450,3 +3450,12 @@ void dc_link_overwrite_extended_receiver_cap(
        dp_overwrite_extended_receiver_cap(link);
 }
 
+bool dc_link_is_fec_supported(const struct dc_link *link)
+{
+       return (dc_is_dp_signal(link->connector_signal) &&
+                       link->link_enc->features.fec_supported &&
+                       link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
+                       !link->dc->debug.disable_fec &&
+                       !IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
+}
+

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 5aa3de9644ea4b3d35897747ca2cd41ff3affd47..c805bec18044e12957317590421e7b1e99a559af 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -4126,8 +4126,7 @@ void dp_set_fec_ready(struct dc_link *link, bool ready)
        struct link_encoder *link_enc = link->link_enc;
        uint8_t fec_config = 0;
 
-       if (link->dc->debug.disable_fec ||
-                       IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment))
+       if (!dc_link_is_fec_supported(link))
                return;
 
        if (link_enc->funcs->fec_set_ready &&
@@ -4162,8 +4161,7 @@ void dp_set_fec_enable(struct dc_link *link, bool enable)
 {
        struct link_encoder *link_enc = link->link_enc;
 
-       if (link->dc->debug.disable_fec ||
-                       IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment))
+       if (!dc_link_is_fec_supported(link))
                return;
 
        if (link_enc->funcs->fec_set_enable &&

diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index c45c7680fa58186a6abbc04effd8195702b67572..00ff5e98278c2f731957a08fcf0c4bb32ca5ed2e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -333,4 +333,7 @@ bool dc_submit_i2c_oem(
 
 uint32_t dc_bandwidth_in_kbps_from_timing(
        const struct dc_crtc_timing *timing);
+
+bool dc_link_is_fec_supported(const struct dc_link *link);
+
 #endif /* DC_LINK_H_ */

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 78971b6b195c3022ed804974455d16d684257ae2..34483853e8891a2a538a18a5d902c2b885103824 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1143,6 +1143,7 @@ static const struct encoder_feature_support link_enc_feature = {
                .max_hdmi_pixel_clock = 600000,
                .hdmi_ycbcr420_supported = true,
                .dp_ycbcr420_supported = true,
+               .fec_supported = true,
                .flags.bits.IS_HBR2_CAPABLE = true,
                .flags.bits.IS_HBR3_CAPABLE = true,
                .flags.bits.IS_TPS3_CAPABLE = true,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 88b51cae617862e643bc479bd38cc0cb8f1d92b9..de9047dd811d020eacec0f050c92f04806cb91f5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -1589,6 +1589,7 @@ static const struct encoder_feature_support link_enc_feature = {
                .max_hdmi_pixel_clock = 600000,
                .hdmi_ycbcr420_supported = true,
                .dp_ycbcr420_supported = true,
+               .fec_supported = true,
                .flags.bits.IS_HBR2_CAPABLE = true,
                .flags.bits.IS_HBR3_CAPABLE = true,
                .flags.bits.IS_TPS3_CAPABLE = true,

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
index fb748f082c5601431f57005ae33f0fd060c20c07..c2b392a533b1ce079cde9d7de086373cacedd3f4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
@@ -68,6 +68,7 @@ struct encoder_feature_support {
        unsigned int max_hdmi_pixel_clock;
        bool hdmi_ycbcr420_supported;
        bool dp_ycbcr420_supported;
+       bool fec_supported;
 };
 
 union dpcd_psr_configuration {