Move generic architectural setup out of blx_plat_arch_setup().

blx_plat_arch_setup() should only perform platform-specific
architectural setup, e.g. enabling the MMU.  This patch moves
generic architectural setup code out of blx_plat_arch_setup().

Change-Id: I4ccf56b8c4a2fa84909817779a2d97a14aaafab6

diff --git a/arch/aarch64/cpu/cpu_helpers.S b/arch/aarch64/cpu/cpu_helpers.S
index 600b72fb01fb19dccc935b3b36b0ecc803e0cc34..76edaa3b3fa5af078780e11b79de210e60c6ab9f 100644 (file)
--- a/arch/aarch64/cpu/cpu_helpers.S
+++ b/arch/aarch64/cpu/cpu_helpers.S
@@ -39,14 +39,9 @@ cpu_reset_handler:; .type cpu_reset_handler, %function
        mov     x19, x30 // lr
 
        /* ---------------------------------------------
-        * As a bare minimal enable the SMP bit and the
-        * I$ for all aarch64 processors. Also set the
-        * exception vector to something sane.
+        * As a bare minimal enable the SMP bit.
         * ---------------------------------------------
         */
-       adr     x0, early_exceptions
-       bl      write_vbar
-
        bl      read_midr
        lsr     x0, x0, #MIDR_PN_SHIFT
        and     x0, x0, #MIDR_PN_MASK
@@ -59,8 +54,4 @@ smp_setup_begin:
        orr     x0, x0, #CPUECTLR_SMP_BIT
        bl      write_cpuectlr
 smp_setup_end:
-       bl      read_sctlr
-       orr     x0, x0, #SCTLR_I_BIT
-       bl      write_sctlr
-
        ret     x19

diff --git a/bl1/aarch64/bl1_entrypoint.S b/bl1/aarch64/bl1_entrypoint.S
index f5ccc65511167f3b2f129120dea50aadfbc5472b..9db2bdf092ecaec726348a590680b4bc879b7140 100644 (file)
--- a/bl1/aarch64/bl1_entrypoint.S
+++ b/bl1/aarch64/bl1_entrypoint.S
@@ -28,6 +28,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include <arch.h>
 
        .globl  reset_handler
 
@@ -49,6 +50,23 @@ reset_handler:; .type reset_handler, %function
         */
        bl      cpu_reset_handler
 
+       /* ---------------------------------------------
+        * Set the exception vector to something sane.
+        * ---------------------------------------------
+        */
+       adr     x0, early_exceptions
+       msr     vbar_el3, x0
+
+       /* ---------------------------------------------
+        * Enable the instruction cache.
+        * ---------------------------------------------
+        */
+       mrs     x0, sctlr_el3
+       orr     x0, x0, #SCTLR_I_BIT
+       msr     sctlr_el3, x0
+
+       isb
+
 _wait_for_entrypoint:
        /* ---------------------------------------------
         * Find the type of reset and jump to handler

diff --git a/bl2/aarch64/bl2_entrypoint.S b/bl2/aarch64/bl2_entrypoint.S
index bade09918f8b5a01f97bb4dd73cfe910cac56d46..4b989a6994d9fa3d141f93516e86ac06fe02f9f3 100644 (file)
--- a/bl2/aarch64/bl2_entrypoint.S
+++ b/bl2/aarch64/bl2_entrypoint.S
@@ -29,6 +29,7 @@
  */
 
 #include <bl_common.h>
+#include <arch.h>
 
 
        .globl  bl2_entrypoint
@@ -59,6 +60,23 @@ bl2_entrypoint:; .type bl2_entrypoint, %function
        bl      platform_is_primary_cpu
        cbz     x0, _panic
 
+       /* ---------------------------------------------
+        * Set the exception vector to something sane.
+        * ---------------------------------------------
+        */
+       adr     x0, early_exceptions
+       msr     vbar_el1, x0
+
+       /* ---------------------------------------------
+        * Enable the instruction cache.
+        * ---------------------------------------------
+        */
+       mrs     x0, sctlr_el1
+       orr     x0, x0, #SCTLR_I_BIT
+       msr     sctlr_el1, x0
+
+       isb
+
        /* --------------------------------------------
         * Give ourselves a small coherent stack to
         * ease the pain of initializing the MMU

diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S
index 3a850e6a4f7a74415fffb6a9f1925a64ea5403f5..3922840d83509a4deb2c3ab0ed488c84608b3c52 100644 (file)
--- a/bl31/aarch64/bl31_entrypoint.S
+++ b/bl31/aarch64/bl31_entrypoint.S
@@ -31,6 +31,7 @@
 #include <bl1.h>
 #include <bl_common.h>
 #include <platform.h>
+#include <arch.h>
 
 
        .globl  bl31_entrypoint
@@ -50,8 +51,29 @@ bl31_entrypoint:; .type bl31_entrypoint, %function
         * indicating BL31 should be run, memory layout
         * of the trusted SRAM available to BL31 and
         * information about running the non-trusted
-        * software already loaded by BL2. Check the
-        * opcode out of paranoia.
+        * software already loaded by BL2.
+        * ---------------------------------------------
+        */
+
+       /* ---------------------------------------------
+        * Set the exception vector to something sane.
+        * ---------------------------------------------
+        */
+       adr     x1, runtime_exceptions
+       msr     vbar_el3, x1
+
+       /* ---------------------------------------------
+        * Enable the instruction cache.
+        * ---------------------------------------------
+        */
+       mrs     x1, sctlr_el3
+       orr     x1, x1, #SCTLR_I_BIT
+       msr     sctlr_el3, x1
+
+       isb
+
+       /* ---------------------------------------------
+        * Check the opcodes out of paranoia.
         * ---------------------------------------------
         */
        mov     x19, #RUN_IMAGE

diff --git a/plat/fvp/bl2_plat_setup.c b/plat/fvp/bl2_plat_setup.c
index e38f00bdf667c1d84fc58cb14c51ba7f52c4644e..4bb10157cecde2c0f53fe3951e7da45feba29584 100644 (file)
--- a/plat/fvp/bl2_plat_setup.c
+++ b/plat/fvp/bl2_plat_setup.c
@@ -124,24 +124,9 @@ void bl2_platform_setup()
  ******************************************************************************/
 void bl2_plat_arch_setup()
 {
-       unsigned long sctlr;
-
-       /* Enable instruction cache. */
-       sctlr = read_sctlr();
-       sctlr |= SCTLR_I_BIT;
-       write_sctlr(sctlr);
-
-       /*
-        * Very simple exception vectors which assert if any exception other
-        * than a single SMC call from BL2 to pass control to BL31 in EL3 is
-        * received.
-        */
-       write_vbar((unsigned long) early_exceptions);
-
        configure_mmu(&bl2_tzram_layout,
                      (unsigned long) &BL2_RO_BASE,
                      (unsigned long) &BL2_STACKS_BASE,
                      (unsigned long) &BL2_COHERENT_RAM_BASE,
                      (unsigned long) &BL2_RW_BASE);
-       return;
 }

diff --git a/plat/fvp/bl31_plat_setup.c b/plat/fvp/bl31_plat_setup.c
index 6c8635fa47f848d4bc4111f33ac897a341a7cc79..7aa1182ddecc2cc718ec13b8d49ab2d91d19af46 100644 (file)
--- a/plat/fvp/bl31_plat_setup.c
+++ b/plat/fvp/bl31_plat_setup.c
@@ -166,14 +166,6 @@ void bl31_platform_setup()
  ******************************************************************************/
 void bl31_plat_arch_setup()
 {
-       unsigned long sctlr;
-
-       /* Enable instruction cache. */
-       sctlr = read_sctlr();
-       sctlr |= SCTLR_I_BIT;
-       write_sctlr(sctlr);
-
-       write_vbar((unsigned long) runtime_exceptions);
        configure_mmu(&bl31_tzram_layout,
                      (unsigned long) &BL31_RO_BASE,
                      (unsigned long) &BL31_STACKS_BASE,