No hold time required! */
iowrite32(0x00000001, ioaddr + PCIBusCfg);
- dev->base_addr = (unsigned long)ioaddr;
- dev->irq = irq;
-
np = netdev_priv(dev);
np->pci_dev = pdev;
np->chip_id = chip_idx;
{
struct netdev_private *np = netdev_priv(dev);
void __iomem *ioaddr = np->base_addr;
+ const int irq = np->pci_dev->irq;
int i;
iowrite32(0x00000001, ioaddr + PCIBusCfg); /* Reset */
netif_device_detach(dev);
- i = request_irq(dev->irq, intr_handler, IRQF_SHARED, dev->name, dev);
+ i = request_irq(irq, intr_handler, IRQF_SHARED, dev->name, dev);
if (i)
goto out_err;
if (debug > 1)
- netdev_dbg(dev, "w89c840_open() irq %d\n", dev->irq);
+ netdev_dbg(dev, "w89c840_open() irq %d\n", irq);
if((i=alloc_ringdesc(dev)))
goto out_err;
{
struct netdev_private *np = netdev_priv(dev);
void __iomem *ioaddr = np->base_addr;
+ const int irq = np->pci_dev->irq;
dev_warn(&dev->dev, "Transmit timed out, status %08x, resetting...\n",
ioread32(ioaddr + IntrStatus));
np->cur_tx, np->dirty_tx, np->tx_full, np->tx_q_bytes);
printk(KERN_DEBUG "Tx Descriptor addr %xh\n", ioread32(ioaddr+0x4C));
- disable_irq(dev->irq);
+ disable_irq(irq);
spin_lock_irq(&np->lock);
/*
* Under high load dirty_tx and the internal tx descriptor pointer
init_rxtx_rings(dev);
init_registers(dev);
spin_unlock_irq(&np->lock);
- enable_irq(dev->irq);
+ enable_irq(irq);
netif_wake_queue(dev);
dev->trans_start = jiffies; /* prevent tx timeout */
iowrite32(0x0000, ioaddr + IntrEnable);
spin_unlock_irq(&np->lock);
- free_irq(dev->irq, dev);
+ free_irq(np->pci_dev->irq, dev);
wmb();
netif_device_attach(dev);
iowrite32(0, ioaddr + IntrEnable);
spin_unlock_irq(&np->lock);
- synchronize_irq(dev->irq);
+ synchronize_irq(np->pci_dev->irq);
netif_tx_disable(dev);
np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;