drm/amdgpu/sdma: switch to amdgpu_sdma_ras_late_init helper function

amdgpu_sdma_ras_late_init is used to init sdma specfic
ras debugfs/sysfs node and sdma specific interrupt handler.
It can be shared among sdma generations

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
index 5c13c503e61f7ca72ad385dba21aa8e3a5625fd9..de27491d620d32da78d04a5bf24e98f018795662 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
@@ -23,6 +23,7 @@
 
 #include "amdgpu.h"
 #include "amdgpu_sdma.h"
+#include "amdgpu_ras.h"
 
 #define AMDGPU_CSA_SDMA_SIZE 64
 /* SDMA CSA reside in the 3rd page of CSA */
@@ -83,3 +84,54 @@ uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring,
 
        return csa_mc_addr;
 }
+
+int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
+                             void *ras_ih_info)
+{
+       int r, i;
+       struct ras_ih_if *ih_info = (struct ras_ih_if *)ras_ih_info;
+       struct ras_fs_if fs_info = {
+               .sysfs_name = "sdma_err_count",
+               .debugfs_name = "sdma_err_inject",
+       };
+
+       if (!ih_info)
+               return -EINVAL;
+
+       if (!adev->sdma.ras_if) {
+               adev->sdma.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
+               if (!adev->sdma.ras_if)
+                       return -ENOMEM;
+               adev->sdma.ras_if->block = AMDGPU_RAS_BLOCK__SDMA;
+               adev->sdma.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
+               adev->sdma.ras_if->sub_block_index = 0;
+               strcpy(adev->sdma.ras_if->name, "sdma");
+       }
+       fs_info.head = ih_info->head = *adev->sdma.ras_if;
+
+       r = amdgpu_ras_late_init(adev, adev->sdma.ras_if,
+                                &fs_info, ih_info);
+       if (r)
+               goto free;
+
+       if (amdgpu_ras_is_supported(adev, adev->sdma.ras_if->block)) {
+               for (i = 0; i < adev->sdma.num_instances; i++) {
+                       r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq,
+                               AMDGPU_SDMA_IRQ_INSTANCE0 + i);
+                       if (r)
+                               goto late_fini;
+               }
+       } else {
+               r = 0;
+               goto free;
+       }
+
+        return 0;
+
+late_fini:
+       amdgpu_ras_late_fini(adev, adev->sdma.ras_if, ih_info);
+free:
+       kfree(adev->sdma.ras_if);
+       adev->sdma.ras_if = NULL;
+       return r;
+}

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
index a9ae0d8a05894c54327b417728bc446af09937ee..79dcb907d00dfd38dda5accf02be0ca05db1f3c4 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
@@ -104,4 +104,6 @@ struct amdgpu_sdma_instance *
 amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring);
 int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);
 uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid);
+int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
+                             void *ras_ih_info);
 #endif

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 5e759a877fdf4509141f638fc66a6acb0a0f8c90..c3635c477bd104c1f8d17c305358eda36e6bc2b1 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1699,48 +1699,8 @@ static int sdma_v4_0_late_init(void *handle)
        struct ras_ih_if ih_info = {
                .cb = sdma_v4_0_process_ras_data_cb,
        };
-       struct ras_fs_if fs_info = {
-               .sysfs_name = "sdma_err_count",
-               .debugfs_name = "sdma_err_inject",
-       };
-       int r, i;
-
-       if (!adev->sdma.ras_if) {
-               adev->sdma.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
-               if (!adev->sdma.ras_if)
-                       return -ENOMEM;
-               adev->sdma.ras_if->block = AMDGPU_RAS_BLOCK__SDMA;
-               adev->sdma.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
-               adev->sdma.ras_if->sub_block_index = 0;
-               strcpy(adev->sdma.ras_if->name, "sdma");
-       }
-       fs_info.head = ih_info.head = *adev->sdma.ras_if;
-
-       r = amdgpu_ras_late_init(adev, adev->sdma.ras_if,
-                                &fs_info, &ih_info);
-       if (r)
-               goto free;
-
-       if (amdgpu_ras_is_supported(adev, adev->sdma.ras_if->block)) {
-               for (i = 0; i < adev->sdma.num_instances; i++) {
-                       r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq,
-                               AMDGPU_SDMA_IRQ_INSTANCE0 + i);
-                       if (r)
-                               goto late_fini;
-               }
-       } else {
-               /* free sdma ras_if if sdma ras is not supported */
-               r = 0;
-               goto free;
-       }
 
-        return 0;
-late_fini:
-       amdgpu_ras_late_fini(adev, adev->sdma.ras_if, &ih_info);
-free:
-       kfree(adev->sdma.ras_if);
-       adev->sdma.ras_if = NULL;
-       return r;
+       return amdgpu_sdma_ras_late_init(adev, &ih_info);
 }
 
 static int sdma_v4_0_sw_init(void *handle)