staging: fbtft: fix space prohibited before that ','

This patch fixes the following checkpatch.pl error:
space prohibited before that ','

Signed-off-by: Aya Mahfouz <mahfouz.saif.elyazal@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/staging/fbtft/fb_ra8875.c b/drivers/staging/fbtft/fb_ra8875.c
index c323c06344fdeff47f73374e27769b7588959e41..8df97373e183d533920e7c07af2005fdac984696 100644 (file)
--- a/drivers/staging/fbtft/fb_ra8875.c
+++ b/drivers/staging/fbtft/fb_ra8875.c
@@ -79,112 +79,112 @@ static int init_display(struct fbtft_par *par)
 
        if ((par->info->var.xres == 320) && (par->info->var.yres == 240)) {
                /* PLL clock frequency */
-               write_reg(par, 0x88 , 0x0A);
-               write_reg(par, 0x89 , 0x02);
+               write_reg(par, 0x88, 0x0A);
+               write_reg(par, 0x89, 0x02);
                mdelay(10);
                /* color deep / MCU Interface */
-               write_reg(par, 0x10 , 0x0C);
+               write_reg(par, 0x10, 0x0C);
                /* pixel clock period  */
-               write_reg(par, 0x04 , 0x03);
+               write_reg(par, 0x04, 0x03);
                mdelay(1);
                /* horizontal settings */
-               write_reg(par, 0x14 , 0x27);
-               write_reg(par, 0x15 , 0x00);
-               write_reg(par, 0x16 , 0x05);
-               write_reg(par, 0x17 , 0x04);
-               write_reg(par, 0x18 , 0x03);
+               write_reg(par, 0x14, 0x27);
+               write_reg(par, 0x15, 0x00);
+               write_reg(par, 0x16, 0x05);
+               write_reg(par, 0x17, 0x04);
+               write_reg(par, 0x18, 0x03);
                /* vertical settings */
-               write_reg(par, 0x19 , 0xEF);
-               write_reg(par, 0x1A , 0x00);
-               write_reg(par, 0x1B , 0x05);
-               write_reg(par, 0x1C , 0x00);
-               write_reg(par, 0x1D , 0x0E);
-               write_reg(par, 0x1E , 0x00);
-               write_reg(par, 0x1F , 0x02);
+               write_reg(par, 0x19, 0xEF);
+               write_reg(par, 0x1A, 0x00);
+               write_reg(par, 0x1B, 0x05);
+               write_reg(par, 0x1C, 0x00);
+               write_reg(par, 0x1D, 0x0E);
+               write_reg(par, 0x1E, 0x00);
+               write_reg(par, 0x1F, 0x02);
        } else if ((par->info->var.xres == 480) && (par->info->var.yres == 272)) {
                /* PLL clock frequency  */
-               write_reg(par, 0x88 , 0x0A);
-               write_reg(par, 0x89 , 0x02);
+               write_reg(par, 0x88, 0x0A);
+               write_reg(par, 0x89, 0x02);
                mdelay(10);
                /* color deep / MCU Interface */
-               write_reg(par, 0x10 , 0x0C);
+               write_reg(par, 0x10, 0x0C);
                /* pixel clock period  */
-               write_reg(par, 0x04 , 0x82);
+               write_reg(par, 0x04, 0x82);
                mdelay(1);
                /* horizontal settings */
-               write_reg(par, 0x14 , 0x3B);
-               write_reg(par, 0x15 , 0x00);
-               write_reg(par, 0x16 , 0x01);
-               write_reg(par, 0x17 , 0x00);
-               write_reg(par, 0x18 , 0x05);
+               write_reg(par, 0x14, 0x3B);
+               write_reg(par, 0x15, 0x00);
+               write_reg(par, 0x16, 0x01);
+               write_reg(par, 0x17, 0x00);
+               write_reg(par, 0x18, 0x05);
                /* vertical settings */
-               write_reg(par, 0x19 , 0x0F);
-               write_reg(par, 0x1A , 0x01);
-               write_reg(par, 0x1B , 0x02);
-               write_reg(par, 0x1C , 0x00);
-               write_reg(par, 0x1D , 0x07);
-               write_reg(par, 0x1E , 0x00);
-               write_reg(par, 0x1F , 0x09);
+               write_reg(par, 0x19, 0x0F);
+               write_reg(par, 0x1A, 0x01);
+               write_reg(par, 0x1B, 0x02);
+               write_reg(par, 0x1C, 0x00);
+               write_reg(par, 0x1D, 0x07);
+               write_reg(par, 0x1E, 0x00);
+               write_reg(par, 0x1F, 0x09);
        } else if ((par->info->var.xres == 640) && (par->info->var.yres == 480)) {
                /* PLL clock frequency */
-               write_reg(par, 0x88 , 0x0B);
-               write_reg(par, 0x89 , 0x02);
+               write_reg(par, 0x88, 0x0B);
+               write_reg(par, 0x89, 0x02);
                mdelay(10);
                /* color deep / MCU Interface */
-               write_reg(par, 0x10 , 0x0C);
+               write_reg(par, 0x10, 0x0C);
                /* pixel clock period */
-               write_reg(par, 0x04 , 0x01);
+               write_reg(par, 0x04, 0x01);
                mdelay(1);
                /* horizontal settings */
-               write_reg(par, 0x14 , 0x4F);
-               write_reg(par, 0x15 , 0x05);
-               write_reg(par, 0x16 , 0x0F);
-               write_reg(par, 0x17 , 0x01);
-               write_reg(par, 0x18 , 0x00);
+               write_reg(par, 0x14, 0x4F);
+               write_reg(par, 0x15, 0x05);
+               write_reg(par, 0x16, 0x0F);
+               write_reg(par, 0x17, 0x01);
+               write_reg(par, 0x18, 0x00);
                /* vertical settings */
-               write_reg(par, 0x19 , 0xDF);
-               write_reg(par, 0x1A , 0x01);
-               write_reg(par, 0x1B , 0x0A);
-               write_reg(par, 0x1C , 0x00);
-               write_reg(par, 0x1D , 0x0E);
-               write_reg(par, 0x1E , 0x00);
-               write_reg(par, 0x1F , 0x01);
+               write_reg(par, 0x19, 0xDF);
+               write_reg(par, 0x1A, 0x01);
+               write_reg(par, 0x1B, 0x0A);
+               write_reg(par, 0x1C, 0x00);
+               write_reg(par, 0x1D, 0x0E);
+               write_reg(par, 0x1E, 0x00);
+               write_reg(par, 0x1F, 0x01);
        } else if ((par->info->var.xres == 800) && (par->info->var.yres == 480)) {
                /* PLL clock frequency */
-               write_reg(par, 0x88 , 0x0B);
-               write_reg(par, 0x89 , 0x02);
+               write_reg(par, 0x88, 0x0B);
+               write_reg(par, 0x89, 0x02);
                mdelay(10);
                /* color deep / MCU Interface */
-               write_reg(par, 0x10 , 0x0C);
+               write_reg(par, 0x10, 0x0C);
                /* pixel clock period */
-               write_reg(par, 0x04 , 0x81);
+               write_reg(par, 0x04, 0x81);
                mdelay(1);
                /* horizontal settings */
-               write_reg(par, 0x14 , 0x63);
-               write_reg(par, 0x15 , 0x03);
-               write_reg(par, 0x16 , 0x03);
-               write_reg(par, 0x17 , 0x02);
-               write_reg(par, 0x18 , 0x00);
+               write_reg(par, 0x14, 0x63);
+               write_reg(par, 0x15, 0x03);
+               write_reg(par, 0x16, 0x03);
+               write_reg(par, 0x17, 0x02);
+               write_reg(par, 0x18, 0x00);
                /* vertical settings */
-               write_reg(par, 0x19 , 0xDF);
-               write_reg(par, 0x1A , 0x01);
-               write_reg(par, 0x1B , 0x14);
-               write_reg(par, 0x1C , 0x00);
-               write_reg(par, 0x1D , 0x06);
-               write_reg(par, 0x1E , 0x00);
-               write_reg(par, 0x1F , 0x01);
+               write_reg(par, 0x19, 0xDF);
+               write_reg(par, 0x1A, 0x01);
+               write_reg(par, 0x1B, 0x14);
+               write_reg(par, 0x1C, 0x00);
+               write_reg(par, 0x1D, 0x06);
+               write_reg(par, 0x1E, 0x00);
+               write_reg(par, 0x1F, 0x01);
        } else {
                dev_err(par->info->device, "display size is not supported!!");
                return -1;
        }
 
        /* PWM clock */
-       write_reg(par, 0x8a , 0x81);
-       write_reg(par, 0x8b , 0xFF);
+       write_reg(par, 0x8a, 0x81);
+       write_reg(par, 0x8b, 0xFF);
        mdelay(10);
 
        /* Display ON */
-       write_reg(par, 0x01 , 0x80);
+       write_reg(par, 0x01, 0x80);
        mdelay(10);
 
        return 0;
@@ -196,14 +196,14 @@ static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
                "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
 
        /* Set_Active_Window */
-       write_reg(par, 0x30 , xs & 0x00FF);
-       write_reg(par, 0x31 , (xs & 0xFF00) >> 8);
-       write_reg(par, 0x32 , ys & 0x00FF);
-       write_reg(par, 0x33 , (ys & 0xFF00) >> 8);
-       write_reg(par, 0x34 , (xs+xe) & 0x00FF);
-       write_reg(par, 0x35 , ((xs+xe) & 0xFF00) >> 8);
-       write_reg(par, 0x36 , (ys+ye) & 0x00FF);
-       write_reg(par, 0x37 , ((ys+ye) & 0xFF00) >> 8);
+       write_reg(par, 0x30, xs & 0x00FF);
+       write_reg(par, 0x31, (xs & 0xFF00) >> 8);
+       write_reg(par, 0x32, ys & 0x00FF);
+       write_reg(par, 0x33, (ys & 0xFF00) >> 8);
+       write_reg(par, 0x34, (xs+xe) & 0x00FF);
+       write_reg(par, 0x35, ((xs+xe) & 0xFF00) >> 8);
+       write_reg(par, 0x36, (ys+ye) & 0x00FF);
+       write_reg(par, 0x37, ((ys+ye) & 0xFF00) >> 8);
 
        /* Set_Memory_Write_Cursor */
        write_reg(par, 0x46,  xs & 0xff);