allwinner: Add Allwinner H6 SoC support

The H6 is Allwinner's most recent SoC. It shares most peripherals with the
other ARMv8 Allwinner SoCs (A64/H5), but has a completely different memory
map.

Introduce a separate platform target, which includes a different header
file to cater for the address differences. Also add the new build target
to the documentation.

The new ATF platform name is "sun50i_h6".

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

diff --git a/docs/plat/allwinner.rst b/docs/plat/allwinner.rst
index 825fded48eb68c61c79ec570ec6bca48f9ef58b2..140edf511a03f4659e40e46f5f610ed354a0b60d 100644 (file)
--- a/docs/plat/allwinner.rst
+++ b/docs/plat/allwinner.rst
@@ -22,12 +22,18 @@ bl31.bin can be either copied (or sym-linked) into U-Boot's root directory,
 or the environment variable BL31 must contain the binary's path.
 See the respective `U-Boot documentation`_ for more details.
 
-To build:
+To build for machines with an A64 or H5 SoC:
 
 ::
 
     make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_a64 DEBUG=1 bl31
 
+To build for machines with an H6 SoC:
+
+::
+
+    make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_h6 DEBUG=1 bl31
+
 .. _U-Boot documentation: http://git.denx.de/?p=u-boot.git;f=board/sunxi/README.sunxi64;hb=HEAD
 
 Trusted OS dispatcher

diff --git a/plat/allwinner/common/sunxi_bl31_setup.c b/plat/allwinner/common/sunxi_bl31_setup.c
index e910ee5491816e4bae4565aadf024aafbf1e8f8e..8ecf49083b6ab1b879b8d952d4f20ab658db5c63 100644 (file)
--- a/plat/allwinner/common/sunxi_bl31_setup.c
+++ b/plat/allwinner/common/sunxi_bl31_setup.c
@@ -74,6 +74,9 @@ void bl31_platform_setup(void)
        case 0x1718:
                soc_name = "H5";
                break;
+       case 0x1728:
+               soc_name = "H6";
+               break;
        default:
                soc_name = "unknown";
                break;

diff --git a/plat/allwinner/sun50i_h6/include/sunxi_cpucfg.h b/plat/allwinner/sun50i_h6/include/sunxi_cpucfg.h
new file mode 100644 (file)
index 0000000..e061b89
--- /dev/null
+++ b/plat/allwinner/sun50i_h6/include/sunxi_cpucfg.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SUNXI_CPUCFG_H__
+#define __SUNXI_CPUCFG_H__
+
+#include <sunxi_mmap.h>
+
+/* c = cluster, n = core */
+#define SUNXI_CPUCFG_CLS_CTRL_REG0(c)  (SUNXI_CPUCFG_BASE + 0x0010 + (c) * 0x10)
+#define SUNXI_CPUCFG_CLS_CTRL_REG1(c)  (SUNXI_CPUCFG_BASE + 0x0014 + (c) * 0x10)
+#define SUNXI_CPUCFG_CACHE_CFG_REG     (SUNXI_CPUCFG_BASE + 0x0024)
+#define SUNXI_CPUCFG_DBG_REG0          (SUNXI_CPUCFG_BASE + 0x00c0)
+
+#define SUNXI_CPUCFG_RST_CTRL_REG(c)   (SUNXI_CPUCFG_BASE + 0x0000 + (c) * 4)
+#define SUNXI_CPUCFG_RVBAR_LO_REG(n)   (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8)
+#define SUNXI_CPUCFG_RVBAR_HI_REG(n)   (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8)
+
+#define SUNXI_POWERON_RST_REG(c)       (SUNXI_R_CPUCFG_BASE + 0x0040 + (c) * 4)
+#define SUNXI_POWEROFF_GATING_REG(c)   (SUNXI_R_CPUCFG_BASE + 0x0044 + (c) * 4)
+#define SUNXI_CPU_POWER_CLAMP_REG(c, n)        (SUNXI_R_CPUCFG_BASE + 0x0050 + \
+                                       (c) * 0x10 + (n) * 4)
+
+#endif /* __SUNXI_CPUCFG_H__ */

diff --git a/plat/allwinner/sun50i_h6/include/sunxi_mmap.h b/plat/allwinner/sun50i_h6/include/sunxi_mmap.h
new file mode 100644 (file)
index 0000000..f2d5aed
--- /dev/null
+++ b/plat/allwinner/sun50i_h6/include/sunxi_mmap.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SUNXI_MMAP_H__
+#define __SUNXI_MMAP_H__
+
+/* Memory regions */
+#define SUNXI_ROM_BASE                 0x00000000
+#define SUNXI_ROM_SIZE                 0x00010000
+#define SUNXI_SRAM_BASE                        0x00020000
+#define SUNXI_SRAM_SIZE                        0x00098000
+#define SUNXI_SRAM_A1_BASE             0x00020000
+#define SUNXI_SRAM_A1_SIZE             0x00008000
+#define SUNXI_SRAM_A2_BASE             0x00104000
+#define SUNXI_SRAM_A2_SIZE             0x00014000
+#define SUNXI_SRAM_C_BASE              0x00028000
+#define SUNXI_SRAM_C_SIZE              0x0001e000
+#define SUNXI_DEV_BASE                 0x01000000
+#define SUNXI_DEV_SIZE                 0x09000000
+#define SUNXI_DRAM_BASE                        0x40000000
+#define SUNXI_DRAM_SIZE                        0xc0000000
+
+/* Memory-mapped devices */
+#define SUNXI_SYSCON_BASE              0x03000000
+#define SUNXI_CPUCFG_BASE              0x09010000
+#define SUNXI_SID_BASE                 0x03006000
+#define SUNXI_DMA_BASE                 0x03002000
+#define SUNXI_MSGBOX_BASE              0x03003000
+#define SUNXI_CCU_BASE                 0x03010000
+#define SUNXI_CCU_SEC_SWITCH_REG       (SUNXI_CCU_BASE + 0xf00)
+#define SUNXI_PIO_BASE                 0x030b0000
+#define SUNXI_TIMER_BASE               0x03009000
+#define SUNXI_WDOG_BASE                        0x030090a0
+#define SUNXI_THS_BASE                 0x05070400
+#define SUNXI_UART0_BASE               0x05000000
+#define SUNXI_UART1_BASE               0x05000400
+#define SUNXI_UART2_BASE               0x05000800
+#define SUNXI_UART3_BASE               0x05000c00
+#define SUNXI_I2C0_BASE                        0x05002000
+#define SUNXI_I2C1_BASE                        0x05002400
+#define SUNXI_I2C2_BASE                        0x05002800
+#define SUNXI_I2C3_BASE                        0x05002c00
+#define SUNXI_SPI0_BASE                        0x05010000
+#define SUNXI_SPI1_BASE                        0x05011000
+#define SUNXI_SCU_BASE                 0x03020000
+#define SUNXI_GICD_BASE                        0x03021000
+#define SUNXI_GICC_BASE                        0x03022000
+#define SUNXI_R_TIMER_BASE             0x07020000
+#define SUNXI_R_INTC_BASE              0x07021000
+#define SUNXI_R_WDOG_BASE              0x07020400
+#define SUNXI_R_PRCM_BASE              0x07010000
+#define SUNXI_R_TWD_BASE               0x07020800
+#define SUNXI_R_CPUCFG_BASE            0x07000400
+#define SUNXI_R_I2C_BASE               0x07081400
+#define SUNXI_R_UART_BASE              0x07080000
+#define SUNXI_R_PIO_BASE               0x07022000
+
+#endif /* __SUNXI_MMAP_H__ */

diff --git a/plat/allwinner/sun50i_h6/platform.mk b/plat/allwinner/sun50i_h6/platform.mk
new file mode 100644 (file)
index 0000000..c1b26fa
--- /dev/null
+++ b/plat/allwinner/sun50i_h6/platform.mk
@@ -0,0 +1,59 @@
+#
+# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+include lib/xlat_tables_v2/xlat_tables.mk
+
+AW_PLAT                        :=      plat/allwinner
+
+PLAT_INCLUDES          :=      -Iinclude/plat/arm/common               \
+                               -Iinclude/plat/arm/common/aarch64       \
+                               -I${AW_PLAT}/common/include             \
+                               -I${AW_PLAT}/${PLAT}/include
+
+PLAT_BL_COMMON_SOURCES :=      drivers/console/${ARCH}/console.S       \
+                               drivers/ti/uart/${ARCH}/16550_console.S \
+                               ${XLAT_TABLES_LIB_SRCS}                 \
+                               ${AW_PLAT}/common/plat_helpers.S        \
+                               ${AW_PLAT}/common/sunxi_common.c
+
+BL31_SOURCES           +=      drivers/arm/gic/common/gic_common.c     \
+                               drivers/arm/gic/v2/gicv2_helpers.c      \
+                               drivers/arm/gic/v2/gicv2_main.c         \
+                               drivers/delay_timer/delay_timer.c       \
+                               drivers/delay_timer/generic_delay_timer.c \
+                               lib/cpus/${ARCH}/cortex_a53.S           \
+                               plat/common/plat_gicv2.c                \
+                               plat/common/plat_psci_common.c          \
+                               ${AW_PLAT}/common/sunxi_bl31_setup.c    \
+                               ${AW_PLAT}/common/sunxi_cpu_ops.c       \
+                               ${AW_PLAT}/common/sunxi_pm.c            \
+                               ${AW_PLAT}/common/sunxi_security.c      \
+                               ${AW_PLAT}/common/sunxi_topology.c
+
+# The bootloader is guaranteed to only run on CPU 0 by the boot ROM.
+COLD_BOOT_SINGLE_CPU           :=      1
+
+# Enable workarounds for Cortex-A53 errata. Allwinner uses at least r0p4.
+ERRATA_A53_835769              :=      1
+ERRATA_A53_843419              :=      1
+ERRATA_A53_855873              :=      1
+
+# Disable the PSCI platform compatibility layer.
+ENABLE_PLAT_COMPAT             :=      0
+
+MULTI_CONSOLE_API              :=      1
+
+# Prohibit using deprecated interfaces. We rely on this for this platform.
+ERROR_DEPRECATED               :=      1
+
+# The reset vector can be changed for each CPU.
+PROGRAMMABLE_RESET_ADDRESS     :=      1
+
+# Allow mapping read-only data as execute-never.
+SEPARATE_CODE_AND_RODATA       :=      1
+
+# BL31 gets loaded alongside BL33 (U-Boot) by U-Boot's SPL
+RESET_TO_BL31                  :=      1