--- /dev/null
+From 28edd829133766eb3cefaf2e49d3ee701968061b Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 9 May 2023 01:57:17 +0200
+Subject: [PATCH] mmc: sdhci-msm: comment unused sdhci_msm_set_clock
+
+comment unused sdhci_msm_set_clock and __sdhci_msm_set_clock as due to some
+current problem, we are forced to use sdhci_set_clock.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ drivers/mmc/host/sdhci-msm.c | 86 ++++++++++++++++++------------------
+ 1 file changed, 43 insertions(+), 43 deletions(-)
+
+--- a/drivers/mmc/host/sdhci-msm.c
++++ b/drivers/mmc/host/sdhci-msm.c
+@@ -1751,49 +1751,49 @@ static unsigned int sdhci_msm_get_min_cl
+ return SDHCI_MSM_MIN_CLOCK;
+ }
+
+-/*
+- * __sdhci_msm_set_clock - sdhci_msm clock control.
+- *
+- * Description:
+- * MSM controller does not use internal divider and
+- * instead directly control the GCC clock as per
+- * HW recommendation.
+- **/
+-static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
+-{
+- u16 clk;
+-
+- sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
+-
+- if (clock == 0)
+- return;
+-
+- /*
+- * MSM controller do not use clock divider.
+- * Thus read SDHCI_CLOCK_CONTROL and only enable
+- * clock with no divider value programmed.
+- */
+- clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+- sdhci_enable_clk(host, clk);
+-}
+-
+-/* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
+-static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
+-{
+- struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+- struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
+-
+- if (!clock) {
+- host->mmc->actual_clock = msm_host->clk_rate = 0;
+- goto out;
+- }
+-
+- sdhci_msm_hc_select_mode(host);
+-
+- msm_set_clock_rate_for_bus_mode(host, clock);
+-out:
+- __sdhci_msm_set_clock(host, clock);
+-}
++// /*
++// * __sdhci_msm_set_clock - sdhci_msm clock control.
++// *
++// * Description:
++// * MSM controller does not use internal divider and
++// * instead directly control the GCC clock as per
++// * HW recommendation.
++// **/
++// static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
++// {
++// u16 clk;
++
++// sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
++
++// if (clock == 0)
++// return;
++
++// /*
++// * MSM controller do not use clock divider.
++// * Thus read SDHCI_CLOCK_CONTROL and only enable
++// * clock with no divider value programmed.
++// */
++// clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
++// sdhci_enable_clk(host, clk);
++// }
++
++// /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
++// static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
++// {
++// struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
++// struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
++
++// if (!clock) {
++// host->mmc->actual_clock = msm_host->clk_rate = 0;
++// goto out;
++// }
++
++// sdhci_msm_hc_select_mode(host);
++
++// msm_set_clock_rate_for_bus_mode(host, clock);
++// out:
++// __sdhci_msm_set_clock(host, clock);
++// }
+
+ /*****************************************************************************\
+ * *