drm/amd/display: Move opp reg access from hwss to opp module.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index b3cd7ca7b4ef801ee0f2b7bf3755b947480d1788..aea64946c409c0e7ece859c1754a1dcad217d207 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -140,10 +140,6 @@
        BL_REG_LIST()
 
 #define HWSEQ_DCN_REG_LIST()\
-       SRII(OPP_PIPE_CONTROL, OPP_PIPE, 0), \
-       SRII(OPP_PIPE_CONTROL, OPP_PIPE, 1), \
-       SRII(OPP_PIPE_CONTROL, OPP_PIPE, 2), \
-       SRII(OPP_PIPE_CONTROL, OPP_PIPE, 3), \
        SR(REFCLK_CNTL), \
        SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
        SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\
@@ -248,7 +244,6 @@ struct dce_hwseq_registers {
        uint32_t DCHUB_AGP_BOT;
        uint32_t DCHUB_AGP_TOP;
 
-       uint32_t OPP_PIPE_CONTROL[4];
        uint32_t REFCLK_CNTL;
        uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;
        uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A;
@@ -418,7 +413,6 @@ struct dce_hwseq_registers {
 #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\
        HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\
        HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \
-       HWS_SF(OPP_PIPE0_, OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, mask_sh),\
        HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
        HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \
        HWS_SF(, DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 5431de7419b3f9685bd05626a899a0bc99dac271..b03ffff9135ba706027238955fb18fd698f3efe8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -633,7 +633,6 @@ static void plane_atomic_power_down(struct dc *dc, struct pipe_ctx *pipe_ctx)
  */
 static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
 {
-       struct dce_hwseq *hws = dc->hwseq;
        struct hubp *hubp = pipe_ctx->plane_res.hubp;
        struct dpp *dpp = pipe_ctx->plane_res.dpp;
        int opp_id = hubp->opp_id;
@@ -645,8 +644,9 @@ static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
        dpp->funcs->dpp_dppclk_control(dpp, false, false);
 
        if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL)
-               REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
-                               OPP_PIPE_CLOCK_EN, 0);
+               pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
+                               pipe_ctx->stream_res.opp,
+                               false);
 
        hubp->power_gated = true;
        dc->optimized_required = false; /* We're powering off, no need to optimize */
@@ -1311,8 +1311,9 @@ static void dcn10_enable_plane(
        pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
 
        /* make sure OPP_PIPE_CLOCK_EN = 1 */
-       REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->stream_res.tg->inst],
-                       OPP_PIPE_CLOCK_EN, 1);
+       pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
+                       pipe_ctx->stream_res.opp,
+                       true);
 
 /* TODO: enable/disable in dm as per update type.
        if (plane_state) {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
index f6ba0eef4489b6f72fb97069eb90ec8b76631c9a..77a1a9d541a410119f92e77cc144477137337983 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
@@ -367,6 +367,14 @@ void opp1_program_oppbuf(
 
 }
 
+void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable)
+{
+       struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
+       uint32_t regval = enable ? 1 : 0;
+
+       REG_UPDATE(OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, regval);
+}
+
 /*****************************************/
 /* Constructor, Destructor               */
 /*****************************************/
@@ -382,6 +390,7 @@ static struct opp_funcs dcn10_opp_funcs = {
                .opp_program_fmt = opp1_program_fmt,
                .opp_program_bit_depth_reduction = opp1_program_bit_depth_reduction,
                .opp_program_stereo = opp1_program_stereo,
+               .opp_pipe_clock_control = opp1_pipe_clock_control,
                .opp_destroy = opp1_destroy
 };
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
index bc5058af626627d62d9f6bf8266764ff75910a84..0f10adea000cc29f844abe4767c1b7f59099086a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
@@ -44,7 +44,8 @@
        SRI(FMT_MAP420_MEMORY_CONTROL, FMT, id), \
        SRI(OPPBUF_CONTROL, OPPBUF, id),\
        SRI(OPPBUF_3D_PARAMETERS_0, OPPBUF, id), \
-       SRI(OPPBUF_3D_PARAMETERS_1, OPPBUF, id)
+       SRI(OPPBUF_3D_PARAMETERS_1, OPPBUF, id), \
+       SRI(OPP_PIPE_CONTROL, OPP_PIPE, id)
 
 #define OPP_REG_LIST_DCN10(id) \
        OPP_REG_LIST_DCN(id)
@@ -61,7 +62,8 @@
        uint32_t OPPBUF_CONTROL; \
        uint32_t OPPBUF_CONTROL1; \
        uint32_t OPPBUF_3D_PARAMETERS_0; \
-       uint32_t OPPBUF_3D_PARAMETERS_1
+       uint32_t OPPBUF_3D_PARAMETERS_1; \
+       uint32_t OPP_PIPE_CONTROL
 
 #define OPP_MASK_SH_LIST_DCN(mask_sh) \
        OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \
@@ -89,7 +91,8 @@
        OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, mask_sh),\
        OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_PIXEL_REPETITION, mask_sh),\
        OPP_SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, mask_sh), \
-       OPP_SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE2_SIZE, mask_sh)
+       OPP_SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE2_SIZE, mask_sh), \
+       OPP_SF(OPP_PIPE0_OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, mask_sh)
 
 #define OPP_MASK_SH_LIST_DCN10(mask_sh) \
        OPP_MASK_SH_LIST_DCN(mask_sh), \
@@ -125,7 +128,8 @@
        type OPPBUF_OVERLAP_PIXEL_NUM;\
        type OPPBUF_NUM_SEGMENT_PADDED_PIXELS; \
        type OPPBUF_3D_VACT_SPACE1_SIZE; \
-       type OPPBUF_3D_VACT_SPACE2_SIZE
+       type OPPBUF_3D_VACT_SPACE2_SIZE; \
+       type OPP_PIPE_CLOCK_EN
 
 struct dcn10_opp_registers {
        OPP_COMMON_REG_VARIABLE_LIST;
@@ -176,6 +180,8 @@ void opp1_program_stereo(
        bool enable,
        const struct dc_crtc_timing *timing);
 
+void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable);
+
 void opp1_destroy(struct output_pixel_processor **opp);
 
 #endif

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
index ab8fb77f1ae5d36d01c263694860d4d681579239..d974d9e18612e7b4af3675f054da8e76769b5522 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
@@ -297,6 +297,10 @@ struct opp_funcs {
                bool enable,
                const struct dc_crtc_timing *timing);
 
+       void (*opp_pipe_clock_control)(
+                       struct output_pixel_processor *opp,
+                       bool enable);
+
 };
 
 #endif