drm/amdgpu/fiji: set UVD CG state when enabling UVD DPM (v2)

Need to call the IP cg callbacks.

v2: fix gate logic

Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c
index e68edf06ed73eecb0afa21f4531ace01156c9b82..e1b649bd5344919b55786bea9fd5fd49c48e240b 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c
@@ -47,10 +47,17 @@ int fiji_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
 
        data->uvd_power_gated = bgate;
 
-       if (bgate)
+       if (bgate) {
+               cgs_set_clockgating_state(hwmgr->device,
+                                         AMD_IP_BLOCK_TYPE_UVD,
+                                         AMD_CG_STATE_GATE);
                fiji_update_uvd_dpm(hwmgr, true);
-       else
+       } else {
                fiji_update_uvd_dpm(hwmgr, false);
+               cgs_set_clockgating_state(hwmgr->device,
+                                         AMD_IP_BLOCK_TYPE_UVD,
+                                         AMD_PG_STATE_UNGATE);
+       }
 
        return 0;
 }