Fix locking and lock usage, making it compile for SMP.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 43578
CONFIG_B53_PHY_FIXUP=y
CONFIG_B53_SPI_DRIVER=y
# CONFIG_B53_SRAB_DRIVER is not set
+CONFIG_BCM6345_EXT_IRQ=y
+CONFIG_BCM6345_PERIPH_IRQ=y
CONFIG_BCM63XX=y
CONFIG_BCM63XX_CPU_3368=y
CONFIG_BCM63XX_CPU_6318=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_IO=y
CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_NET_UTILS=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GPIOLIB=y
CONFIG_B53_SPI_DRIVER=y
# CONFIG_B53_SRAB_DRIVER is not set
CONFIG_BCM6345_EXT_IRQ=y
-CONFIG_BCM6345_L2_IRQ=y
+CONFIG_BCM6345_PERIPH_IRQ=y
CONFIG_BCM63XX=y
CONFIG_BCM63XX_CPU_3368=y
CONFIG_BCM63XX_CPU_6318=y
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_CPU_MIPS32=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
CONFIG_CPU_R4K_CACHE_TLB=y
CONFIG_CPU_R4K_FPU=y
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
};
periph_intc: interrupt-controller@10000020 {
- compatible = "brcm,bcm6345-l2-intc";
+ compatible = "brcm,bcm6345-periph-intc";
reg = <0x10000020 0x20>;
interrupt-controller;
};
periph_intc: interrupt-controller@10000020 {
- compatible = "brcm,bcm6345-l2-intc";
+ compatible = "brcm,bcm6345-periph-intc";
reg = <0x10000020 0x20>,
<0x10000040 0x20>;
};
periph_intc: interrupt-controller@10000020 {
- compatible = "brcm,bcm6345-l2-intc";
+ compatible = "brcm,bcm6345-periph-intc";
reg = <0x10000020 0x10>;
interrupt-controller;
compatible = "simple-bus";
periph_intc: interrupt-controller@fffe000c {
- compatible = "brcm,bcm6345-l2-intc";
+ compatible = "brcm,bcm6345-periph-intc";
reg = <0xfffe000c 0x8>;
interrupt-controller;
compatible = "simple-bus";
periph_intc: interrupt-controller@fffe000c {
- compatible = "brcm,bcm6345-l2-intc";
+ compatible = "brcm,bcm6345-periph-intc";
reg = <0xfffe000c 0x9>;
interrupt-controller;
compatible = "simple-bus";
periph_intc: interrupt-controller@fffe000c {
- compatible = "brcm,bcm6345-l2-intc";
+ compatible = "brcm,bcm6345-periph-intc";
reg = <0xfffe000c 0x8>;
interrupt-controller;
interrupt-parent = <&cpu_intc>;
interrupts = <3>, <4>, <5>, <6>;
+
+ brcm,field-width = <5>;
};
};
};
compatible = "simple-bus";
periph_intc: interrupt-controller@fffe000c {
- compatible = "brcm,bcm6345-l2-intc";
+ compatible = "brcm,bcm6345-periph-intc";
reg = <0xfffe000c 0x8>,
<0xfffe0038 0x8>;
};
periph_intc: interrupt-controller@10000020 {
- compatible = "brcm,bcm6345-l2-intc";
+ compatible = "brcm,bcm6345-periph-intc";
reg = <0x10000020 0x10>,
<0x10000030 0x10>;
};
periph_intc: interrupt-controller@10000020 {
- compatible = "brcm,bcm6345-l2-intc";
+ compatible = "brcm,bcm6345-periph-intc";
reg = <0x10000020 0x10>,
<0x10000030 0x10>;
+++ /dev/null
-From 4d3886359d6f6ac475e143d5f3e3b389542a0510 Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jogo@openwrt.org>
-Date: Sun, 30 Nov 2014 14:53:12 +0100
-Subject: [PATCH 17/20] irqchip: add support for bcm6345-style l2 irq
- controller
-
-Signed-off-by: Jonas Gorski <jogo@openwrt.org>
----
- .../interrupt-controller/brcm,bcm6345-l2-intc.txt | 25 ++
- drivers/irqchip/Kconfig | 4 +
- drivers/irqchip/Makefile | 1 +
- drivers/irqchip/irq-bcm6345-l2.c | 320 ++++++++++++++++++++
- include/linux/irqchip/irq-bcm6345-l2-intc.h | 16 +
- 5 files changed, 366 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l2-intc.txt
- create mode 100644 drivers/irqchip/irq-bcm6345-l2.c
- create mode 100644 include/linux/irqchip/irq-bcm6345-l2-intc.h
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l2-intc.txt
-@@ -0,0 +1,25 @@
-+Broadcom BCM6345 Level 2 interrupt controller
-+
-+Required properties:
-+
-+- compatible: should be "brcm,bcm6345-l2-intc"
-+- reg: specifies the base physical address and size of the registers;
-+ multiple regs may be specified, and must match the amount of parent interrupts
-+- interrupt-controller: identifies the node as an interrupt controller
-+- #interrupt-cells: specifies the number of cells needed to encode an interrupt
-+ source, should be 1
-+- interrupt-parent: specifies the phandle to the parent interrupt controller
-+ this one is cascaded from
-+- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
-+ node, valid values depend on the type of parent interrupt controller
-+
-+Example:
-+
-+periph_intc: interrupt-controller@f0406800 {
-+ compatible = "brcm,bcm6345-l2-intc";
-+ interrupt-parent = <&mips_intc>;
-+ #interrupt-cells = <1>;
-+ reg = <0x10000020 0x10> <0x10000030 0x10>;
-+ interrupt-controller;
-+ interrupts = <2>, <3>;
-+};
---- a/drivers/irqchip/Kconfig
-+++ b/drivers/irqchip/Kconfig
-@@ -30,6 +30,10 @@ config ARM_VIC_NR
- The maximum number of VICs available in the system, for
- power management.
-
-+config BCM6345_L2_IRQ
-+ bool
-+ select IRQ_DOMAIN
-+
- config DW_APB_ICTL
- bool
- select IRQ_DOMAIN
---- a/drivers/irqchip/Makefile
-+++ b/drivers/irqchip/Makefile
-@@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
- obj-$(CONFIG_ARCH_MVEBU) += irq-armada-370-xp.o
- obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
- obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
-+obj-$(CONFIG_BCM6345_L2_IRQ) += irq-bcm6345-l2.o
- obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
- obj-$(CONFIG_METAG) += irq-metag-ext.o
- obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
---- /dev/null
-+++ b/drivers/irqchip/irq-bcm6345-l2.c
-@@ -0,0 +1,320 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>
-+ */
-+
-+#include <linux/ioport.h>
-+#include <linux/irq.h>
-+#include <linux/irqchip/chained_irq.h>
-+#include <linux/irqchip/irq-bcm6345-l2-intc.h>
-+#include <linux/kernel.h>
-+#include <linux/of.h>
-+#include <linux/of_irq.h>
-+#include <linux/of_address.h>
-+#include <linux/slab.h>
-+#include <linux/spinlock.h>
-+
-+#ifdef CONFIG_BCM63XX
-+#include <asm/mach-bcm63xx/bcm63xx_irq.h>
-+
-+#define VIRQ_BASE IRQ_INTERNAL_BASE
-+#else
-+#define VIRQ_BASE 0
-+#endif
-+
-+#include "irqchip.h"
-+
-+#define MAX_WORDS 4
-+#define MAX_PARENT_IRQS 2
-+#define IRQS_PER_WORD 32
-+
-+struct intc_block {
-+ int parent_irq;
-+ void __iomem *base;
-+ void __iomem *en_reg[MAX_WORDS];
-+ void __iomem *status_reg[MAX_WORDS];
-+ u32 mask_cache[MAX_WORDS];
-+};
-+
-+struct intc_data {
-+ struct irq_chip chip;
-+ struct intc_block block[MAX_PARENT_IRQS];
-+
-+ int num_words;
-+
-+ struct irq_domain *domain;
-+ spinlock_t lock;
-+};
-+
-+static void bcm6345_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
-+{
-+ struct intc_data *data = irq_desc_get_handler_data(desc);
-+ struct irq_chip *chip = irq_desc_get_chip(desc);
-+ struct intc_block *block;
-+ unsigned int idx;
-+
-+ chained_irq_enter(chip, desc);
-+
-+ for (idx = 0; idx < MAX_PARENT_IRQS; idx++)
-+ if (irq == data->block[idx].parent_irq)
-+ block = &data->block[idx];
-+
-+ for (idx = 0; idx < data->num_words; idx++) {
-+ int base = idx * IRQS_PER_WORD;
-+ unsigned long pending;
-+ int hw_irq;
-+
-+ raw_spin_lock(data->lock);
-+ pending = __raw_readl(block->en_reg[idx]) &
-+ __raw_readl(block->status_reg[idx]);
-+ raw_spin_unlock(data->lock);
-+
-+ for_each_set_bit(hw_irq, &pending, IRQS_PER_WORD) {
-+ generic_handle_irq(irq_find_mapping(data->domain, base + hw_irq));
-+ }
-+ }
-+
-+ chained_irq_exit(chip, desc);
-+}
-+
-+static void bcm6345_l2_intc_irq_mask(struct irq_data *data)
-+{
-+ unsigned int i, reg, bit;
-+ struct intc_data *priv = data->domain->host_data;
-+ irq_hw_number_t hwirq = irqd_to_hwirq(data);
-+
-+ reg = hwirq / IRQS_PER_WORD;
-+ bit = hwirq % IRQS_PER_WORD;
-+
-+ raw_spin_lock(priv->lock);
-+ for (i = 0; i < MAX_PARENT_IRQS; i++) {
-+ struct intc_block *block = &priv->block[i];
-+ u32 val;
-+
-+ if (!block->parent_irq)
-+ break;
-+
-+ val = __raw_readl(block->en_reg[reg]);
-+ __raw_writel(val & ~BIT(bit), block->en_reg[reg]);
-+ }
-+ raw_spin_unlock(priv->lock);
-+}
-+
-+static void bcm6345_l2_intc_irq_unmask(struct irq_data *data)
-+{
-+ unsigned int i, reg, bit;
-+ struct intc_data *priv = data->domain->host_data;
-+ irq_hw_number_t hwirq = irqd_to_hwirq(data);
-+
-+ reg = hwirq / IRQS_PER_WORD;
-+ bit = hwirq % IRQS_PER_WORD;
-+
-+ raw_spin_lock(priv->lock);
-+ for (i = 0; i < MAX_PARENT_IRQS; i++) {
-+ struct intc_block *block = &priv->block[i];
-+ u32 val;
-+
-+ if (!block->parent_irq)
-+ break;
-+
-+ val = __raw_readl(block->en_reg[reg]);
-+
-+ if (block->mask_cache[reg] & BIT(bit))
-+ val |= BIT(bit);
-+ else
-+ val &= ~BIT(bit);
-+
-+ __raw_writel(val, block->en_reg[reg]);
-+
-+ }
-+ raw_spin_unlock(priv->lock);
-+}
-+
-+#ifdef CONFIG_SMP
-+static int bcm6345_l2_intc_set_affinity(struct irq_data *data,
-+ const struct cpumask *mask,
-+ bool force)
-+{
-+ irq_hw_number_t hwirq = irqd_to_hwirq(data);
-+ struct intc_data *priv = data->domain->host_data;
-+ unsigned int i, reg, bit;
-+ int cpu;
-+
-+ reg = hwirq / IRQS_PER_WORD;
-+ bit = hwirq % IRQS_PER_WORD;
-+
-+ /* we could route to more than one cpu, but performance
-+ suffers, so fix it to one.
-+ */
-+ cpu = cpumask_any_and(mask, cpu_online_mask);
-+ if (cpu >= nr_cpu_ids)
-+ return -EINVAL;
-+
-+ if (cpu >= MAX_PARENT_IRQS)
-+ return -EINVAL;
-+
-+ if (!priv->block[cpu].parent_irq)
-+ return -EINVAL;
-+
-+ raw_spin_lock(priv->lock);
-+ for (i = 0; i < MAX_PARENT_IRQS; i++) {
-+ if (i == cpu)
-+ priv->block[i].mask_cache[reg] |= BIT(bit);
-+ else
-+ priv->block[i].mask_cache[reg] &= ~BIT(bit);
-+ }
-+ raw_spin_unlock(priv->lock);
-+
-+ return 0;
-+}
-+#endif
-+
-+static int bcm6345_l2_map(struct irq_domain *d, unsigned int irq,
-+ irq_hw_number_t hw)
-+{
-+ struct intc_data *priv = d->host_data;
-+
-+ irq_set_chip_and_handler(irq, &priv->chip, handle_level_irq);
-+
-+ return 0;
-+}
-+
-+static const struct irq_domain_ops bcm6345_l2_domain_ops = {
-+ .xlate = irq_domain_xlate_onecell,
-+ .map = bcm6345_l2_map,
-+};
-+
-+static int __init __bcm6345_l2_intc_init(struct device_node *node,
-+ int num_blocks, int *irq,
-+ void __iomem **base, int num_words)
-+{
-+ struct intc_data *data;
-+ unsigned int i, w, status_offset;
-+
-+ data = kzalloc(sizeof(*data), GFP_KERNEL);
-+ if (!data)
-+ return -ENOMEM;
-+
-+ status_offset = num_words * sizeof(u32);
-+
-+ for (i = 0; i < num_blocks; i++) {
-+ struct intc_block *block = &data->block[i];
-+
-+ block->parent_irq = irq[i];
-+ block->base = base[i];
-+
-+ for (w = 0; w < num_words; w++) {
-+ int word_offset = sizeof(u32) * ((num_words - w) - 1);
-+
-+ block->en_reg[w] = base[i] + word_offset;
-+ block->status_reg[w] = base[i] + status_offset;
-+ block->status_reg[w] += word_offset;
-+
-+ /* route all interrups to line 0 by default */
-+ if (i == 0)
-+ block->mask_cache[w] = 0xffffffff;
-+ }
-+
-+ irq_set_handler_data(block->parent_irq, data);
-+ irq_set_chained_handler(block->parent_irq,
-+ bcm6345_l2_intc_irq_handle);
-+ }
-+
-+ data->num_words = num_words;
-+
-+ data->chip.name = "bcm6345-l2-intc";
-+ data->chip.irq_mask = bcm6345_l2_intc_irq_mask;
-+ data->chip.irq_unmask = bcm6345_l2_intc_irq_unmask;
-+
-+#ifdef CONFIG_SMP
-+ if (num_blocks > 1)
-+ data->chip.set_affinity = bcm6345_l2_intc_set_affinity;
-+#endif
-+
-+ data->domain = irq_domain_add_simple(node, IRQS_PER_WORD * num_words,
-+ VIRQ_BASE, &bcm6345_l2_domain_ops,
-+ data);
-+ if (!data->domain) {
-+ kfree(data);
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+void __init bcm6345_l2_intc_init(int num_blocks, int *irq, void __iomem **base,
-+ int num_words)
-+{
-+ __bcm6345_l2_intc_init(NULL, num_blocks, irq, base, num_words);
-+}
-+
-+#ifdef CONFIG_OF
-+static int __init bcm6345_l2_intc_of_init(struct device_node *node,
-+ struct device_node *parent)
-+{
-+ struct resource res;
-+ int num_irqs, ret = -EINVAL;
-+ int irqs[MAX_PARENT_IRQS] = { 0 };
-+ void __iomem *bases[MAX_PARENT_IRQS] = { NULL };
-+ int words = 0;
-+ int i;
-+
-+ num_irqs = of_irq_count(node);
-+
-+ if (num_irqs < 1 || num_irqs > MAX_PARENT_IRQS)
-+ return -EINVAL;
-+
-+ for (i = 0; i < num_irqs; i++) {
-+ resource_size_t size;
-+
-+ irqs[i] = irq_of_parse_and_map(node, i);
-+ if (!irqs[i])
-+ goto out_unmap;
-+
-+ if (of_address_to_resource(node, i, &res)) {
-+ goto out_unmap;
-+ }
-+
-+ size = resource_size(&res);
-+ switch (size) {
-+ case 8:
-+ case 16:
-+ case 32:
-+ size = size / 8;
-+ break;
-+ default:
-+ goto out_unmap;
-+ }
-+
-+ if (words && words != size) {
-+ ret = -EINVAL;
-+ goto out_unmap;
-+ }
-+ words = size;
-+
-+ bases[i] = of_iomap(node, i);
-+ if (!bases[i]) {
-+ ret = -ENOMEM;
-+ goto out_unmap;
-+ }
-+ }
-+
-+ ret = __bcm6345_l2_intc_init(node, num_irqs, irqs, bases, words);
-+ if (!ret)
-+ return 0;
-+
-+out_unmap:
-+ for (i = 0; i < num_irqs; i++) {
-+ iounmap(bases[i]);
-+ irq_dispose_mapping(irqs[i]);
-+ }
-+
-+ return ret;
-+}
-+
-+IRQCHIP_DECLARE(bcm6345_l2_intc, "brcm,bcm6345-l2-intc",
-+ bcm6345_l2_intc_of_init);
-+#endif
---- /dev/null
-+++ b/include/linux/irqchip/irq-bcm6345-l2-intc.h
-@@ -0,0 +1,16 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
-+ * Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr>
-+ */
-+
-+#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_L2_INTC_H
-+#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_L2_INTC_H
-+
-+void bcm6345_l2_intc_init(int num_blocks, int *irq, void __iomem **base,
-+ int num_words);
-+
-+#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_L2_INTC_H */
--- /dev/null
+From 7aaa70416d87434792b73077beb328202975e541 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Sun, 30 Nov 2014 14:53:12 +0100
+Subject: [PATCH 1/5] irqchip: add support for bcm6345-style periphery irq
+ controller
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ .../brcm,bcm6345-periph-intc.txt | 50 +++
+ drivers/irqchip/Kconfig | 4 +
+ drivers/irqchip/Makefile | 1 +
+ drivers/irqchip/irq-bcm6345-periph.c | 325 ++++++++++++++++++++
+ include/linux/irqchip/irq-bcm6345-periph.h | 16 +
+ 5 files changed, 396 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-periph-intc.txt
+ create mode 100644 drivers/irqchip/irq-bcm6345-periph.c
+ create mode 100644 include/linux/irqchip/irq-bcm6345-periph.h
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-periph-intc.txt
+@@ -0,0 +1,50 @@
++Broadcom BCM6345 Level 1 periphery interrupt controller
++
++This block is a interrupt controller that is typically connected directly
++to one of the HW INT lines on each CPU. Every BCM63XX xDSL chip since
++BCM6345 has contained this hardware.
++
++Key elements of the hardware design include:
++
++- 32, 64, or 128 incoming level IRQ lines
++
++- All onchip peripherals are wired directly to an L2 input
++
++- A separate instance of the register set for each CPU, allowing individual
++ peripheral IRQs to be routed to any CPU
++
++- No atomic mask/unmask operations
++
++- No polarity/level/edge settings
++
++- No FIFO or priority encoder logic; software is expected to read all
++ 1-4 status words to determine which IRQs are pending
++
++Required properties:
++
++- compatible: Should be "brcm,bcm6345-periph-intc".
++- reg: Specifies the base physical address and size of the registers.
++ Multiple register addresses may be specified, and must match the amount of
++ parent interrupts.
++- interrupt-controller: Identifies the node as an interrupt controller.
++- #interrupt-cells: Specifies the number of cells needed to encode an interrupt
++ source, should be 1.
++- interrupt-parent: Specifies the phandle to the parent interrupt controller
++ this one is cascaded from.
++- interrupts: Specifies the interrupt line(s) in the interrupt-parent controller
++ node, valid values depend on the type of parent interrupt controller.
++ Multiple lines are used to route interrupts to different cpus, with the first
++ assumed to be for the boot CPU.
++
++Example:
++
++periph_intc: interrupt-controller@f0406800 {
++ compatible = "brcm,bcm6345-periph-intc";
++ reg = <0x10000020 0x10>, <0x10000030 0x10>;
++
++ interrupt-controller;
++ #interrupt-cells = <1>;
++
++ interrupt-parent = <&cpu_intc>;
++ interrupts = <2>, <3>;
++};
+--- a/drivers/irqchip/Kconfig
++++ b/drivers/irqchip/Kconfig
+@@ -30,6 +30,10 @@ config ARM_VIC_NR
+ The maximum number of VICs available in the system, for
+ power management.
+
++config BCM6345_PERIPH_IRQ
++ bool
++ select IRQ_DOMAIN
++
+ config DW_APB_ICTL
+ bool
+ select IRQ_DOMAIN
+--- a/drivers/irqchip/Makefile
++++ b/drivers/irqchip/Makefile
+@@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
+ obj-$(CONFIG_ARCH_MVEBU) += irq-armada-370-xp.o
+ obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
+ obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
++obj-$(CONFIG_BCM6345_PERIPH_IRQ) += irq-bcm6345-periph.o
+ obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
+ obj-$(CONFIG_METAG) += irq-metag-ext.o
+ obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
+--- /dev/null
++++ b/drivers/irqchip/irq-bcm6345-periph.c
+@@ -0,0 +1,340 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>
++ */
++
++#include <linux/ioport.h>
++#include <linux/irq.h>
++#include <linux/irqchip/chained_irq.h>
++#include <linux/irqchip/irq-bcm6345-periph.h>
++#include <linux/kernel.h>
++#include <linux/of.h>
++#include <linux/of_irq.h>
++#include <linux/of_address.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++
++#ifdef CONFIG_BCM63XX
++#include <asm/mach-bcm63xx/bcm63xx_irq.h>
++
++#define VIRQ_BASE IRQ_INTERNAL_BASE
++#else
++#define VIRQ_BASE 0
++#endif
++
++#include "irqchip.h"
++
++#define MAX_WORDS 4
++#define MAX_PARENT_IRQS 2
++#define IRQS_PER_WORD 32
++
++struct intc_block {
++ int parent_irq;
++ void __iomem *base;
++ void __iomem *en_reg[MAX_WORDS];
++ void __iomem *status_reg[MAX_WORDS];
++ u32 mask_cache[MAX_WORDS];
++};
++
++struct intc_data {
++ struct irq_chip chip;
++ struct intc_block block[MAX_PARENT_IRQS];
++
++ int num_words;
++
++ struct irq_domain *domain;
++ raw_spinlock_t lock;
++};
++
++static void bcm6345_periph_irq_handle(unsigned int irq, struct irq_desc *desc)
++{
++ struct intc_data *data = irq_desc_get_handler_data(desc);
++ struct irq_chip *chip = irq_desc_get_chip(desc);
++ struct intc_block *block;
++ unsigned int idx;
++
++ chained_irq_enter(chip, desc);
++
++ for (idx = 0; idx < MAX_PARENT_IRQS; idx++)
++ if (irq == data->block[idx].parent_irq)
++ block = &data->block[idx];
++
++ for (idx = 0; idx < data->num_words; idx++) {
++ int base = idx * IRQS_PER_WORD;
++ unsigned long pending;
++ int hw_irq;
++
++ raw_spin_lock(&data->lock);
++ pending = __raw_readl(block->en_reg[idx]) &
++ __raw_readl(block->status_reg[idx]);
++ raw_spin_unlock(&data->lock);
++
++ for_each_set_bit(hw_irq, &pending, IRQS_PER_WORD) {
++ int virq;
++
++ virq = irq_find_mapping(data->domain, base + hw_irq);
++ generic_handle_irq(virq);
++ }
++ }
++
++ chained_irq_exit(chip, desc);
++}
++
++static void __bcm6345_periph_enable(struct intc_block *block, int reg, int bit,
++ bool enable)
++{
++ u32 val;
++
++ val = __raw_readl(block->en_reg[reg]);
++ if (enable)
++ val |= BIT(bit);
++ else
++ val &= ~BIT(bit);
++ __raw_writel(val, block->en_reg[reg]);
++}
++
++static void bcm6345_periph_irq_mask(struct irq_data *data)
++{
++ unsigned int i, reg, bit;
++ struct intc_data *priv = data->domain->host_data;
++ irq_hw_number_t hwirq = irqd_to_hwirq(data);
++
++ reg = hwirq / IRQS_PER_WORD;
++ bit = hwirq % IRQS_PER_WORD;
++
++ raw_spin_lock(&priv->lock);
++ for (i = 0; i < MAX_PARENT_IRQS; i++) {
++ struct intc_block *block = &priv->block[i];
++
++ if (!block->parent_irq)
++ break;
++
++ __bcm6345_periph_enable(block, reg, bit, false);
++ }
++ raw_spin_unlock(&priv->lock);
++}
++
++static void bcm6345_periph_irq_unmask(struct irq_data *data)
++{
++ struct intc_data *priv = data->domain->host_data;
++ irq_hw_number_t hwirq = irqd_to_hwirq(data);
++ unsigned int i, reg, bit;
++
++ reg = hwirq / IRQS_PER_WORD;
++ bit = hwirq % IRQS_PER_WORD;
++
++ raw_spin_lock(&priv->lock);
++ for (i = 0; i < MAX_PARENT_IRQS; i++) {
++ struct intc_block *block = &priv->block[i];
++
++ if (!block->parent_irq)
++ break;
++
++ if (block->mask_cache[reg] & BIT(bit))
++ __bcm6345_periph_enable(block, reg, bit, true);
++ else
++ __bcm6345_periph_enable(block, reg, bit, false);
++
++ }
++ raw_spin_unlock(&priv->lock);
++}
++
++#ifdef CONFIG_SMP
++static int bcm6345_periph_set_affinity(struct irq_data *data,
++ const struct cpumask *mask, bool force)
++{
++ irq_hw_number_t hwirq = irqd_to_hwirq(data);
++ struct intc_data *priv = data->domain->host_data;
++ unsigned int i, reg, bit;
++ bool enabled;
++ int cpu;
++
++ reg = hwirq / IRQS_PER_WORD;
++ bit = hwirq % IRQS_PER_WORD;
++
++ /* we could route to more than one cpu, but performance
++ suffers, so fix it to one.
++ */
++ cpu = cpumask_any_and(mask, cpu_online_mask);
++ if (cpu >= nr_cpu_ids)
++ return -EINVAL;
++
++ if (cpu >= MAX_PARENT_IRQS)
++ return -EINVAL;
++
++ if (!priv->block[cpu].parent_irq)
++ return -EINVAL;
++
++ raw_spin_lock(&priv->lock);
++ enabled = !irqd_irq_masked(data);
++ for (i = 0; i < MAX_PARENT_IRQS; i++) {
++ struct intc_block *block = &priv->block[i];
++
++ if (!block->parent_irq)
++ break;
++
++ if (i == cpu) {
++ block->mask_cache[reg] |= BIT(bit);
++ __bcm6345_periph_enable(block, reg, bit, enabled);
++ } else {
++ block->mask_cache[reg] &= ~BIT(bit);
++ __bcm6345_periph_enable(block, reg, bit, false);
++ }
++ }
++ raw_spin_unlock(&priv->lock);
++
++ return 0;
++}
++#endif
++
++static int bcm6345_periph_map(struct irq_domain *d, unsigned int irq,
++ irq_hw_number_t hw)
++{
++ struct intc_data *priv = d->host_data;
++
++ irq_set_chip_and_handler(irq, &priv->chip, handle_level_irq);
++
++ return 0;
++}
++
++static const struct irq_domain_ops bcm6345_periph_domain_ops = {
++ .xlate = irq_domain_xlate_onecell,
++ .map = bcm6345_periph_map,
++};
++
++static int __init __bcm6345_periph_intc_init(struct device_node *node,
++ int num_blocks, int *irq,
++ void __iomem **base, int num_words)
++{
++ struct intc_data *data;
++ unsigned int i, w, status_offset;
++
++ data = kzalloc(sizeof(*data), GFP_KERNEL);
++ if (!data)
++ return -ENOMEM;
++
++ raw_spin_lock_init(&data->lock);
++
++ status_offset = num_words * sizeof(u32);
++
++ for (i = 0; i < num_blocks; i++) {
++ struct intc_block *block = &data->block[i];
++
++ block->parent_irq = irq[i];
++ block->base = base[i];
++
++ for (w = 0; w < num_words; w++) {
++ int word_offset = sizeof(u32) * ((num_words - w) - 1);
++
++ block->en_reg[w] = base[i] + word_offset;
++ block->status_reg[w] = base[i] + status_offset;
++ block->status_reg[w] += word_offset;
++
++ /* route all interrups to line 0 by default */
++ if (i == 0)
++ block->mask_cache[w] = 0xffffffff;
++ }
++
++ irq_set_handler_data(block->parent_irq, data);
++ irq_set_chained_handler(block->parent_irq,
++ bcm6345_periph_irq_handle);
++ }
++
++ data->num_words = num_words;
++
++ data->chip.name = "bcm6345-periph-intc";
++ data->chip.irq_mask = bcm6345_periph_irq_mask;
++ data->chip.irq_unmask = bcm6345_periph_irq_unmask;
++
++#ifdef CONFIG_SMP
++ if (num_blocks > 1)
++ data->chip.irq_set_affinity = bcm6345_periph_set_affinity;
++#endif
++
++ data->domain = irq_domain_add_simple(node, IRQS_PER_WORD * num_words,
++ VIRQ_BASE,
++ &bcm6345_periph_domain_ops, data);
++ if (!data->domain) {
++ kfree(data);
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++void __init bcm6345_periph_intc_init(int num_blocks, int *irq,
++ void __iomem **base, int num_words)
++{
++ __bcm6345_periph_intc_init(NULL, num_blocks, irq, base, num_words);
++}
++
++#ifdef CONFIG_OF
++static int __init bcm6345_periph_of_init(struct device_node *node,
++ struct device_node *parent)
++{
++ struct resource res;
++ int num_irqs, ret = -EINVAL;
++ int irqs[MAX_PARENT_IRQS] = { 0 };
++ void __iomem *bases[MAX_PARENT_IRQS] = { NULL };
++ int words = 0;
++ int i;
++
++ num_irqs = of_irq_count(node);
++
++ if (num_irqs < 1 || num_irqs > MAX_PARENT_IRQS)
++ return -EINVAL;
++
++ for (i = 0; i < num_irqs; i++) {
++ resource_size_t size;
++
++ irqs[i] = irq_of_parse_and_map(node, i);
++ if (!irqs[i])
++ goto out_unmap;
++
++ if (of_address_to_resource(node, i, &res)) {
++ goto out_unmap;
++ }
++
++ size = resource_size(&res);
++ switch (size) {
++ case 8:
++ case 16:
++ case 32:
++ size = size / 8;
++ break;
++ default:
++ goto out_unmap;
++ }
++
++ if (words && words != size) {
++ ret = -EINVAL;
++ goto out_unmap;
++ }
++ words = size;
++
++ bases[i] = of_iomap(node, i);
++ if (!bases[i]) {
++ ret = -ENOMEM;
++ goto out_unmap;
++ }
++ }
++
++ ret = __bcm6345_periph_intc_init(node, num_irqs, irqs, bases, words);
++ if (!ret)
++ return 0;
++
++out_unmap:
++ for (i = 0; i < num_irqs; i++) {
++ iounmap(bases[i]);
++ irq_dispose_mapping(irqs[i]);
++ }
++
++ return ret;
++}
++
++IRQCHIP_DECLARE(bcm6345_periph_intc, "brcm,bcm6345-periph-intc",
++ bcm6345_periph_of_init);
++#endif
+--- /dev/null
++++ b/include/linux/irqchip/irq-bcm6345-periph.h
+@@ -0,0 +1,16 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
++ * Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr>
++ */
++
++#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H
++#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H
++
++void bcm6345_periph_intc_init(int num_blocks, int *irq, void __iomem **base,
++ int num_words);
++
++#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H */
+diff --git a/drivers/irqchip/irq-bcm6345-periph.c b/drivers/irqchip/irq-bcm6345-periph.c
+index dfab88e..b280164 100644
+--- a/drivers/irqchip/irq-bcm6345-periph.c
++++ b/drivers/irqchip/irq-bcm6345-periph.c
+@@ -149,6 +149,7 @@ static int bcm6345_periph_set_affinity(struct irq_data *data,
+ irq_hw_number_t hwirq = irqd_to_hwirq(data);
+ struct intc_data *priv = data->domain->host_data;
+ unsigned int i, reg, bit;
++ unsigned long flags;
+ bool enabled;
+ int cpu;
+
+@@ -168,7 +169,7 @@ static int bcm6345_periph_set_affinity(struct irq_data *data,
+ if (!priv->block[cpu].parent_irq)
+ return -EINVAL;
+
+- raw_spin_lock(&priv->lock);
++ raw_spin_lock_irqsave(&priv->lock, flags);
+ enabled = !irqd_irq_masked(data);
+ for (i = 0; i < MAX_PARENT_IRQS; i++) {
+ struct intc_block *block = &priv->block[i];
+@@ -184,7 +185,7 @@ static int bcm6345_periph_set_affinity(struct irq_data *data,
+ __bcm6345_periph_enable(block, reg, bit, false);
+ }
+ }
+- raw_spin_unlock(&priv->lock);
++ raw_spin_unlock_irqrestore(&priv->lock, flags);
+
+ return 0;
+ }
-From 6896b5f0538a7a7cfb7fac2d9ed3c6841c72ed40 Mon Sep 17 00:00:00 2001
+From ac60253478d58fc73b4c0a390eb6229222460e8a Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Sun, 30 Nov 2014 14:54:27 +0100
-Subject: [PATCH 18/20] irqchip: add support for bcm6345-style external
+Subject: [PATCH 2/5] irqchip: add support for bcm6345-style external
interrupt controller
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
- .../interrupt-controller/brcm,bcm6345-ext-intc.txt | 24 ++
+ .../interrupt-controller/brcm,bcm6345-ext-intc.txt | 29 ++
drivers/irqchip/Kconfig | 4 +
drivers/irqchip/Makefile | 1 +
- drivers/irqchip/irq-bcm6345-ext.c | 296 ++++++++++++++++++++
- include/linux/irqchip/irq-bcm6345-ext-intc.h | 14 +
- 5 files changed, 339 insertions(+)
+ drivers/irqchip/irq-bcm6345-ext.c | 286 ++++++++++++++++++++
+ include/linux/irqchip/irq-bcm6345-ext.h | 14 +
+ 5 files changed, 334 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.txt
create mode 100644 drivers/irqchip/irq-bcm6345-ext.c
- create mode 100644 include/linux/irqchip/irq-bcm6345-ext-intc.h
+ create mode 100644 include/linux/irqchip/irq-bcm6345-ext.h
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.txt
-@@ -0,0 +1,24 @@
+@@ -0,0 +1,29 @@
+Broadcom BCM6345-style external interrupt controller
+
+Required properties:
+
-+- compatible: should be "brcm,bcm6345-l2-intc" or "brcm,bcm6345-l2-intc"
-+- reg: specifies the base physical addresses and size of the registers.
-+- interrupt-controller: identifies the node as an interrupt controller
-+- #interrupt-cells: specifies the number of cells needed to encode an interrupt
-+ source, should be 2
-+- interrupt-parent: specifies the phandle to the parent interrupt controller
-+ this one is cascaded from
-+- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
-+ node, valid values depend on the type of parent interrupt controller
++- compatible: Should be "brcm,bcm6345-l2-intc".
++- reg: Specifies the base physical addresses and size of the registers.
++- interrupt-controller: identifies the node as an interrupt controller.
++- #interrupt-cells: Specifies the number of cells needed to encode an interrupt
++ source, Should be 2.
++- interrupt-parent: Specifies the phandle to the parent interrupt controller
++ this one is cascaded from.
++- interrupts: Specifies the interrupt line(s) in the interrupt-parent controller
++ node, valid values depend on the type of parent interrupt controller.
++
++Optional properties:
++
++- brcm,field-width: Size of each field (mask, clear, sense, ...) in bits in the
++ register. Defaults to 4.
+
+Example:
+
+ bool
+ select IRQ_DOMAIN
+
- config BCM6345_L2_IRQ
+ config BCM6345_PERIPH_IRQ
bool
select IRQ_DOMAIN
--- a/drivers/irqchip/Makefile
obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
+obj-$(CONFIG_BCM6345_EXT_IRQ) += irq-bcm6345-ext.o
- obj-$(CONFIG_BCM6345_L2_IRQ) += irq-bcm6345-l2.o
+ obj-$(CONFIG_BCM6345_PERIPH_IRQ) += irq-bcm6345-periph.o
obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
obj-$(CONFIG_METAG) += irq-metag-ext.o
--- /dev/null
+++ b/drivers/irqchip/irq-bcm6345-ext.c
-@@ -0,0 +1,296 @@
+@@ -0,0 +1,288 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+#include <linux/ioport.h>
+#include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
-+#include <linux/irqchip/irq-bcm6345-ext-intc.h>
++#include <linux/irqchip/irq-bcm6345-ext.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+struct intc_data {
+ struct irq_chip chip;
+ struct irq_domain *domain;
-+ spinlock_t lock;
++ raw_spinlock_t lock;
+
+ int parent_irq[MAX_IRQS];
+ void __iomem *reg;
+ irq_hw_number_t hwirq = irqd_to_hwirq(data);
+ u32 reg;
+
-+ raw_spin_lock(priv->lock);
++ raw_spin_lock(&priv->lock);
+ reg = __raw_readl(priv->reg);
+ reg |= hwirq << (EXTIRQ_CFG_CLEAR * priv->shift);
+ __raw_writel(reg, priv->reg);
-+ raw_spin_unlock(priv->lock);
++ raw_spin_unlock(&priv->lock);
+}
+
+static void bcm6345_ext_intc_irq_mask(struct irq_data *data)
+ irq_hw_number_t hwirq = irqd_to_hwirq(data);
+ u32 reg;
+
-+ raw_spin_lock(priv->lock);
++ raw_spin_lock(&priv->lock);
+ reg = __raw_readl(priv->reg);
+ reg &= ~(hwirq << (EXTIRQ_CFG_MASK * priv->shift));
+ __raw_writel(reg, priv->reg);
-+ raw_spin_unlock(priv->lock);
++ raw_spin_unlock(&priv->lock);
+}
+
+static void bcm6345_ext_intc_irq_unmask(struct irq_data *data)
+ irq_hw_number_t hwirq = irqd_to_hwirq(data);
+ u32 reg;
+
-+ raw_spin_lock(priv->lock);
++ raw_spin_lock(&priv->lock);
+ reg = __raw_readl(priv->reg);
+ reg |= hwirq << (EXTIRQ_CFG_MASK * priv->shift);
+ __raw_writel(reg, priv->reg);
-+ raw_spin_unlock(priv->lock);
++ raw_spin_unlock(&priv->lock);
+}
+
+static int bcm6345_ext_intc_set_type(struct irq_data *data,
+ return -EINVAL;
+ }
+
-+ raw_spin_lock(priv->lock);
++ raw_spin_lock(&priv->lock);
+ reg = __raw_readl(priv->reg);
+
+ if (levelsense)
+ reg &= ~(hwirq << (EXTIRQ_CFG_BOTHEDGE * priv->shift));
+
+ __raw_writel(reg, priv->reg);
-+ raw_spin_unlock(priv->lock);
++ raw_spin_unlock(&priv->lock);
+
+ irqd_set_trigger_type(data, flow_type);
+ if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
+ if (!data)
+ return -ENOMEM;
+
++ raw_spin_lock_init(&data->lock);
++
+ for (i = 0; i < num_irqs; i++) {
+ data->parent_irq[i] = irqs[i];
+
+}
+
+#ifdef CONFIG_OF
-+static int __init bcm63xx_ext_intc_of_init(struct device_node *node,
-+ struct device_node *parent,
-+ int shift)
++static int __init bcm6345_ext_intc_of_init(struct device_node *node,
++ struct device_node *parent)
+{
+ int num_irqs, ret = -EINVAL;
+ unsigned i;
+ void __iomem *base;
+ int irqs[MAX_IRQS] = { 0 };
++ u32 shift;
+
+ num_irqs = of_irq_count(node);
+
+ if (!num_irqs || num_irqs > MAX_IRQS)
+ return -EINVAL;
+
++ if (of_property_read_u32(node, "brcm,field-width", &shift))
++ shift = 4;
++
+ for (i = 0; i < num_irqs; i++) {
+ irqs[i] = irq_of_parse_and_map(node, i);
+ if (!irqs[i]) {
+ return ret;
+}
+
-+static int __init bcm6345_ext_intc_of_init(struct device_node *node,
-+ struct device_node *parent)
-+{
-+ return bcm63xx_ext_intc_of_init(node, parent, 4);
-+}
-+static int __init bcm6348_ext_intc_of_init(struct device_node *node,
-+ struct device_node *parent)
-+{
-+ return bcm63xx_ext_intc_of_init(node, parent, 5);
-+}
-+
+IRQCHIP_DECLARE(bcm6345_ext_intc, "brcm,bcm6345-ext-intc",
+ bcm6345_ext_intc_of_init);
-+IRQCHIP_DECLARE(bcm6348_ext_intc, "brcm,bcm6348-ext-intc",
-+ bcm6348_ext_intc_of_init);
+#endif
--- /dev/null
-+++ b/include/linux/irqchip/irq-bcm6345-ext-intc.h
++++ b/include/linux/irqchip/irq-bcm6345-ext.h
@@ -0,0 +1,14 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>
+ */
+
-+#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_INTC_H
-+#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_INTC_H
++#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H
++#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H
+
+void bcm6345_ext_intc_init(int n_irqs, int *irqs, void __iomem *reg, int shift);
+
-+#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_INTC_H */
++#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H */
select DMA_NONCOHERENT
select IRQ_CPU
+ select BCM6345_EXT_IRQ
-+ select BCM6345_L2_IRQ
++ select BCM6345_PERIPH_IRQ
+ select IRQ_DOMAIN
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
#include <linux/irq.h>
-#include <linux/spinlock.h>
+#include <linux/irqchip.h>
-+#include <linux/irqchip/irq-bcm6345-ext-intc.h>
-+#include <linux/irqchip/irq-bcm6345-l2-intc.h>
++#include <linux/irqchip/irq-bcm6345-ext.h>
++#include <linux/irqchip/irq-bcm6345-periph.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <bcm63xx_cpu.h>
- irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF);
- irq_stat_addr[1] = bcm63xx_regset_address(RSET_PERF);
- irq_mask_addr[1] = bcm63xx_regset_address(RSET_PERF);
-+ void __iomem *l2_intc_bases[2];
++ void __iomem *periph_bases[2];
+ void __iomem *ext_intc_bases[2];
-+ int l2_irq_count, l2_width, ext_irq_count, ext_shift;
-+ int l2_irqs[2] = { 2, 3 };
++ int periph_irq_count, periph_width, ext_irq_count, ext_shift;
++ int periph_irqs[2] = { 2, 3 };
+ int ext_irqs[6];
+
-+ l2_intc_bases[0] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
-+ l2_intc_bases[1] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
++ periph_bases[0] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
++ periph_bases[1] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
+ ext_intc_bases[0] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
+ ext_intc_bases[1] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
- irq_bits = 32;
- ext_irq_count = 4;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
-+ l2_intc_bases[0] += PERF_IRQMASK_3368_REG;
-+ l2_irq_count = 1;
-+ l2_width = 1;
++ periph_bases[0] += PERF_IRQMASK_3368_REG;
++ periph_irq_count = 1;
++ periph_width = 1;
+
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_3368;
+ ext_irq_count = 4;
- ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
- ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
-+ l2_intc_bases[0] += PERF_IRQMASK_6328_REG(0);
-+ l2_intc_bases[1] += PERF_IRQMASK_6328_REG(1);
-+ l2_irq_count = 2;
-+ l2_width = 2;
++ periph_bases[0] += PERF_IRQMASK_6328_REG(0);
++ periph_bases[1] += PERF_IRQMASK_6328_REG(1);
++ periph_irq_count = 2;
++ periph_width = 2;
+
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6328;
+ ext_irq_count = 4;
- irq_bits = 32;
- ext_irq_count = 4;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
-+ l2_intc_bases[0] += PERF_IRQMASK_6338_REG;
-+ l2_irq_count = 1;
-+ l2_width = 1;
++ periph_bases[0] += PERF_IRQMASK_6338_REG;
++ periph_irq_count = 1;
++ periph_width = 1;
+
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6338;
+ ext_irq_count = 4;
- irq_bits = 32;
- ext_irq_count = 4;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
-+ l2_intc_bases[0] += PERF_IRQMASK_6345_REG;
-+ l2_irq_count = 1;
-+ l2_width = 1;
++ periph_bases[0] += PERF_IRQMASK_6345_REG;
++ periph_irq_count = 1;
++ periph_width = 1;
+
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6345;
+ ext_irq_count = 4;
- irq_bits = 32;
- ext_irq_count = 4;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
-+ l2_intc_bases[0] += PERF_IRQMASK_6348_REG;
-+ l2_irq_count = 1;
-+ l2_width = 1;
++ periph_bases[0] += PERF_IRQMASK_6348_REG;
++ periph_irq_count = 1;
++ periph_width = 1;
+
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6348;
+ ext_irq_count = 4;
- ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
- ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
-+ l2_intc_bases[0] += PERF_IRQMASK_6358_REG(0);
-+ l2_intc_bases[1] += PERF_IRQMASK_6358_REG(1);
-+ l2_irq_count = 2;
-+ l2_width = 1;
++ periph_bases[0] += PERF_IRQMASK_6358_REG(0);
++ periph_bases[1] += PERF_IRQMASK_6358_REG(1);
++ periph_irq_count = 2;
++ periph_width = 1;
+
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6358;
+ ext_irq_count = 4;
- ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;
- ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
-+ l2_intc_bases[0] += PERF_IRQMASK_6362_REG(0);
-+ l2_intc_bases[1] += PERF_IRQMASK_6362_REG(1);
-+ l2_irq_count = 2;
-+ l2_width = 2;
++ periph_bases[0] += PERF_IRQMASK_6362_REG(0);
++ periph_bases[1] += PERF_IRQMASK_6362_REG(1);
++ periph_irq_count = 2;
++ periph_width = 2;
+
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6362;
+ ext_irq_count = 4;
- irq_stat_addr[1] += PERF_IRQSTAT_6368_REG(1);
- irq_mask_addr[1] += PERF_IRQMASK_6368_REG(1);
- irq_bits = 64;
-+ l2_intc_bases[0] += PERF_IRQMASK_6368_REG(0);
-+ l2_intc_bases[1] += PERF_IRQMASK_6368_REG(1);
-+ l2_irq_count = 2;
-+ l2_width = 2;
++ periph_bases[0] += PERF_IRQMASK_6368_REG(0);
++ periph_bases[1] += PERF_IRQMASK_6368_REG(1);
++ periph_irq_count = 2;
++ periph_width = 2;
+
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6368;
+ ext_intc_bases[1] += PERF_EXTIRQ_CFG_REG2_6368;
- internal_irq_unmask = __internal_irq_unmask_64;
- }
+ mips_cpu_irq_init();
-+ bcm6345_l2_intc_init(l2_irq_count, l2_irqs, l2_intc_bases, l2_width);
++ bcm6345_periph_intc_init(periph_irq_count, periph_irqs, periph_bases, periph_width);
+ bcm6345_ext_intc_init(4, ext_irqs, ext_intc_bases[0], ext_shift);
+ if (ext_irq_count > 4)
+ bcm6345_ext_intc_init(2, &ext_irqs[4], ext_intc_bases[1],
-From e3c68bbba30b212326fb69bf64b2220750dead3e Mon Sep 17 00:00:00 2001
+From fc8b863c38be9b2ccf805dd5ae17dbffb6bfbe87 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Sun, 30 Nov 2014 20:20:30 +0100
-Subject: [PATCH 20/20] MIPS: BCM63XX: wire up BCM6358's external interrupts 4
+Subject: [PATCH 4/5] MIPS: BCM63XX: wire up BCM6358's external interrupts 4
and 5
Due to the external interrupts being non consecutive, the previous
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -109,11 +109,14 @@ static void bcm63xx_init_irq(void)
- l2_width = 1;
+ periph_width = 1;
ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6358;
- ext_irq_count = 4;
ext_shift = 4;
break;
+ case BCM63268_CPU_ID:
-+ l2_intc_bases[0] += PERF_IRQSTAT_63268_REG(0);
-+ l2_intc_bases[1] += PERF_IRQSTAT_63268_REG(1);
-+ l2_irq_count = 2;
-+ l2_width = 4;
++ periph_bases[0] += PERF_IRQSTAT_63268_REG(0);
++ periph_bases[1] += PERF_IRQSTAT_63268_REG(1);
++ periph_irq_count = 2;
++ periph_width = 4;
+
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_63268;
+ ext_irq_count = 4;
ext_shift = 4;
break;
+ case BCM6318_CPU_ID:
-+ l2_intc_bases[0] += PERF_IRQMASK_6318_REG;
-+ l2_irq_count = 1;
-+ l2_width = 4;
++ periph_bases[0] += PERF_IRQMASK_6318_REG;
++ periph_irq_count = 1;
++ periph_width = 4;
+
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6318;
+ ext_irq_count = 4;
+ ext_shift = 4;
+ break;
case BCM6328_CPU_ID:
- l2_intc_bases[0] += PERF_IRQMASK_6328_REG(0);
- l2_intc_bases[1] += PERF_IRQMASK_6328_REG(1);
+ periph_bases[0] += PERF_IRQMASK_6328_REG(0);
+ periph_bases[1] += PERF_IRQMASK_6328_REG(1);
--- a/arch/mips/bcm63xx/prom.c
+++ b/arch/mips/bcm63xx/prom.c
@@ -72,7 +72,7 @@ void __init prom_init(void)
-From 7c22b08baba941a8c83072047b0d2b55a6b952aa Mon Sep 17 00:00:00 2001
+From 40c0e6e4f68ce0c759eb216b44cdfbe18de328b0 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Mon, 1 Dec 2014 00:20:07 +0100
-Subject: [PATCH] MIPS: BCM63XX: register interrupt controllers through DT
+Subject: [PATCH 5/5] MIPS: BCM63XX: register interrupt controllers through DT
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
- arch/mips/bcm63xx/irq.c | 10 +++++++++-
- 1 file changed, 9 insertions(+), 1 deletion(-)
+ arch/mips/bcm63xx/irq.c | 12 +++++++++++-
+ 1 file changed, 11 insertions(+), 1 deletion(-)
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -15,6 +15,8 @@
#include <linux/irqchip.h>
- #include <linux/irqchip/irq-bcm6345-ext-intc.h>
- #include <linux/irqchip/irq-bcm6345-l2-intc.h>
+ #include <linux/irqchip/irq-bcm6345-ext.h>
+ #include <linux/irqchip/irq-bcm6345-periph.h>
+#include <linux/of.h>
+#include <linux/of_fdt.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <bcm63xx_cpu.h>
-@@ -189,7 +191,15 @@ static void bcm63xx_init_irq(void)
+@@ -189,7 +191,17 @@ static void bcm63xx_init_irq(void)
ext_shift);
}
void __init arch_init_irq(void)
{
- bcm63xx_init_irq();
++#ifdef CONFIG_OF
+ if (initial_boot_params)
+ irqchip_init();
+ else
++#endif
+ bcm63xx_init_irq();
}
+++ /dev/null
-From 4d3886359d6f6ac475e143d5f3e3b389542a0510 Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jogo@openwrt.org>
-Date: Sun, 30 Nov 2014 14:53:12 +0100
-Subject: [PATCH 17/20] irqchip: add support for bcm6345-style l2 irq
- controller
-
-Signed-off-by: Jonas Gorski <jogo@openwrt.org>
----
- .../interrupt-controller/brcm,bcm6345-l2-intc.txt | 25 ++
- drivers/irqchip/Kconfig | 4 +
- drivers/irqchip/Makefile | 1 +
- drivers/irqchip/irq-bcm6345-l2.c | 320 ++++++++++++++++++++
- include/linux/irqchip/irq-bcm6345-l2-intc.h | 16 +
- 5 files changed, 366 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l2-intc.txt
- create mode 100644 drivers/irqchip/irq-bcm6345-l2.c
- create mode 100644 include/linux/irqchip/irq-bcm6345-l2-intc.h
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l2-intc.txt
-@@ -0,0 +1,25 @@
-+Broadcom BCM6345 Level 2 interrupt controller
-+
-+Required properties:
-+
-+- compatible: should be "brcm,bcm6345-l2-intc"
-+- reg: specifies the base physical address and size of the registers;
-+ multiple regs may be specified, and must match the amount of parent interrupts
-+- interrupt-controller: identifies the node as an interrupt controller
-+- #interrupt-cells: specifies the number of cells needed to encode an interrupt
-+ source, should be 1
-+- interrupt-parent: specifies the phandle to the parent interrupt controller
-+ this one is cascaded from
-+- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
-+ node, valid values depend on the type of parent interrupt controller
-+
-+Example:
-+
-+periph_intc: interrupt-controller@f0406800 {
-+ compatible = "brcm,bcm6345-l2-intc";
-+ interrupt-parent = <&mips_intc>;
-+ #interrupt-cells = <1>;
-+ reg = <0x10000020 0x10> <0x10000030 0x10>;
-+ interrupt-controller;
-+ interrupts = <2>, <3>;
-+};
---- a/drivers/irqchip/Kconfig
-+++ b/drivers/irqchip/Kconfig
-@@ -54,6 +54,10 @@ config BRCMSTB_L2_IRQ
- select GENERIC_IRQ_CHIP
- select IRQ_DOMAIN
-
-+config BCM6345_L2_IRQ
-+ bool
-+ select IRQ_DOMAIN
-+
- config DW_APB_ICTL
- bool
- select IRQ_DOMAIN
---- a/drivers/irqchip/Makefile
-+++ b/drivers/irqchip/Makefile
-@@ -7,6 +7,7 @@ obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
- obj-$(CONFIG_ARCH_MVEBU) += irq-armada-370-xp.o
- obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
- obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
-+obj-$(CONFIG_BCM6345_L2_IRQ) += irq-bcm6345-l2.o
- obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
- obj-$(CONFIG_METAG) += irq-metag-ext.o
- obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
---- /dev/null
-+++ b/drivers/irqchip/irq-bcm6345-l2.c
-@@ -0,0 +1,320 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>
-+ */
-+
-+#include <linux/ioport.h>
-+#include <linux/irq.h>
-+#include <linux/irqchip/chained_irq.h>
-+#include <linux/irqchip/irq-bcm6345-l2-intc.h>
-+#include <linux/kernel.h>
-+#include <linux/of.h>
-+#include <linux/of_irq.h>
-+#include <linux/of_address.h>
-+#include <linux/slab.h>
-+#include <linux/spinlock.h>
-+
-+#ifdef CONFIG_BCM63XX
-+#include <asm/mach-bcm63xx/bcm63xx_irq.h>
-+
-+#define VIRQ_BASE IRQ_INTERNAL_BASE
-+#else
-+#define VIRQ_BASE 0
-+#endif
-+
-+#include "irqchip.h"
-+
-+#define MAX_WORDS 4
-+#define MAX_PARENT_IRQS 2
-+#define IRQS_PER_WORD 32
-+
-+struct intc_block {
-+ int parent_irq;
-+ void __iomem *base;
-+ void __iomem *en_reg[MAX_WORDS];
-+ void __iomem *status_reg[MAX_WORDS];
-+ u32 mask_cache[MAX_WORDS];
-+};
-+
-+struct intc_data {
-+ struct irq_chip chip;
-+ struct intc_block block[MAX_PARENT_IRQS];
-+
-+ int num_words;
-+
-+ struct irq_domain *domain;
-+ spinlock_t lock;
-+};
-+
-+static void bcm6345_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
-+{
-+ struct intc_data *data = irq_desc_get_handler_data(desc);
-+ struct irq_chip *chip = irq_desc_get_chip(desc);
-+ struct intc_block *block;
-+ unsigned int idx;
-+
-+ chained_irq_enter(chip, desc);
-+
-+ for (idx = 0; idx < MAX_PARENT_IRQS; idx++)
-+ if (irq == data->block[idx].parent_irq)
-+ block = &data->block[idx];
-+
-+ for (idx = 0; idx < data->num_words; idx++) {
-+ int base = idx * IRQS_PER_WORD;
-+ unsigned long pending;
-+ int hw_irq;
-+
-+ raw_spin_lock(data->lock);
-+ pending = __raw_readl(block->en_reg[idx]) &
-+ __raw_readl(block->status_reg[idx]);
-+ raw_spin_unlock(data->lock);
-+
-+ for_each_set_bit(hw_irq, &pending, IRQS_PER_WORD) {
-+ generic_handle_irq(irq_find_mapping(data->domain, base + hw_irq));
-+ }
-+ }
-+
-+ chained_irq_exit(chip, desc);
-+}
-+
-+static void bcm6345_l2_intc_irq_mask(struct irq_data *data)
-+{
-+ unsigned int i, reg, bit;
-+ struct intc_data *priv = data->domain->host_data;
-+ irq_hw_number_t hwirq = irqd_to_hwirq(data);
-+
-+ reg = hwirq / IRQS_PER_WORD;
-+ bit = hwirq % IRQS_PER_WORD;
-+
-+ raw_spin_lock(priv->lock);
-+ for (i = 0; i < MAX_PARENT_IRQS; i++) {
-+ struct intc_block *block = &priv->block[i];
-+ u32 val;
-+
-+ if (!block->parent_irq)
-+ break;
-+
-+ val = __raw_readl(block->en_reg[reg]);
-+ __raw_writel(val & ~BIT(bit), block->en_reg[reg]);
-+ }
-+ raw_spin_unlock(priv->lock);
-+}
-+
-+static void bcm6345_l2_intc_irq_unmask(struct irq_data *data)
-+{
-+ unsigned int i, reg, bit;
-+ struct intc_data *priv = data->domain->host_data;
-+ irq_hw_number_t hwirq = irqd_to_hwirq(data);
-+
-+ reg = hwirq / IRQS_PER_WORD;
-+ bit = hwirq % IRQS_PER_WORD;
-+
-+ raw_spin_lock(priv->lock);
-+ for (i = 0; i < MAX_PARENT_IRQS; i++) {
-+ struct intc_block *block = &priv->block[i];
-+ u32 val;
-+
-+ if (!block->parent_irq)
-+ break;
-+
-+ val = __raw_readl(block->en_reg[reg]);
-+
-+ if (block->mask_cache[reg] & BIT(bit))
-+ val |= BIT(bit);
-+ else
-+ val &= ~BIT(bit);
-+
-+ __raw_writel(val, block->en_reg[reg]);
-+
-+ }
-+ raw_spin_unlock(priv->lock);
-+}
-+
-+#ifdef CONFIG_SMP
-+static int bcm6345_l2_intc_set_affinity(struct irq_data *data,
-+ const struct cpumask *mask,
-+ bool force)
-+{
-+ irq_hw_number_t hwirq = irqd_to_hwirq(data);
-+ struct intc_data *priv = data->domain->host_data;
-+ unsigned int i, reg, bit;
-+ int cpu;
-+
-+ reg = hwirq / IRQS_PER_WORD;
-+ bit = hwirq % IRQS_PER_WORD;
-+
-+ /* we could route to more than one cpu, but performance
-+ suffers, so fix it to one.
-+ */
-+ cpu = cpumask_any_and(mask, cpu_online_mask);
-+ if (cpu >= nr_cpu_ids)
-+ return -EINVAL;
-+
-+ if (cpu >= MAX_PARENT_IRQS)
-+ return -EINVAL;
-+
-+ if (!priv->block[cpu].parent_irq)
-+ return -EINVAL;
-+
-+ raw_spin_lock(priv->lock);
-+ for (i = 0; i < MAX_PARENT_IRQS; i++) {
-+ if (i == cpu)
-+ priv->block[i].mask_cache[reg] |= BIT(bit);
-+ else
-+ priv->block[i].mask_cache[reg] &= ~BIT(bit);
-+ }
-+ raw_spin_unlock(priv->lock);
-+
-+ return 0;
-+}
-+#endif
-+
-+static int bcm6345_l2_map(struct irq_domain *d, unsigned int irq,
-+ irq_hw_number_t hw)
-+{
-+ struct intc_data *priv = d->host_data;
-+
-+ irq_set_chip_and_handler(irq, &priv->chip, handle_level_irq);
-+
-+ return 0;
-+}
-+
-+static const struct irq_domain_ops bcm6345_l2_domain_ops = {
-+ .xlate = irq_domain_xlate_onecell,
-+ .map = bcm6345_l2_map,
-+};
-+
-+static int __init __bcm6345_l2_intc_init(struct device_node *node,
-+ int num_blocks, int *irq,
-+ void __iomem **base, int num_words)
-+{
-+ struct intc_data *data;
-+ unsigned int i, w, status_offset;
-+
-+ data = kzalloc(sizeof(*data), GFP_KERNEL);
-+ if (!data)
-+ return -ENOMEM;
-+
-+ status_offset = num_words * sizeof(u32);
-+
-+ for (i = 0; i < num_blocks; i++) {
-+ struct intc_block *block = &data->block[i];
-+
-+ block->parent_irq = irq[i];
-+ block->base = base[i];
-+
-+ for (w = 0; w < num_words; w++) {
-+ int word_offset = sizeof(u32) * ((num_words - w) - 1);
-+
-+ block->en_reg[w] = base[i] + word_offset;
-+ block->status_reg[w] = base[i] + status_offset;
-+ block->status_reg[w] += word_offset;
-+
-+ /* route all interrups to line 0 by default */
-+ if (i == 0)
-+ block->mask_cache[w] = 0xffffffff;
-+ }
-+
-+ irq_set_handler_data(block->parent_irq, data);
-+ irq_set_chained_handler(block->parent_irq,
-+ bcm6345_l2_intc_irq_handle);
-+ }
-+
-+ data->num_words = num_words;
-+
-+ data->chip.name = "bcm6345-l2-intc";
-+ data->chip.irq_mask = bcm6345_l2_intc_irq_mask;
-+ data->chip.irq_unmask = bcm6345_l2_intc_irq_unmask;
-+
-+#ifdef CONFIG_SMP
-+ if (num_blocks > 1)
-+ data->chip.set_affinity = bcm6345_l2_intc_set_affinity;
-+#endif
-+
-+ data->domain = irq_domain_add_simple(node, IRQS_PER_WORD * num_words,
-+ VIRQ_BASE, &bcm6345_l2_domain_ops,
-+ data);
-+ if (!data->domain) {
-+ kfree(data);
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+void __init bcm6345_l2_intc_init(int num_blocks, int *irq, void __iomem **base,
-+ int num_words)
-+{
-+ __bcm6345_l2_intc_init(NULL, num_blocks, irq, base, num_words);
-+}
-+
-+#ifdef CONFIG_OF
-+static int __init bcm6345_l2_intc_of_init(struct device_node *node,
-+ struct device_node *parent)
-+{
-+ struct resource res;
-+ int num_irqs, ret = -EINVAL;
-+ int irqs[MAX_PARENT_IRQS] = { 0 };
-+ void __iomem *bases[MAX_PARENT_IRQS] = { NULL };
-+ int words = 0;
-+ int i;
-+
-+ num_irqs = of_irq_count(node);
-+
-+ if (num_irqs < 1 || num_irqs > MAX_PARENT_IRQS)
-+ return -EINVAL;
-+
-+ for (i = 0; i < num_irqs; i++) {
-+ resource_size_t size;
-+
-+ irqs[i] = irq_of_parse_and_map(node, i);
-+ if (!irqs[i])
-+ goto out_unmap;
-+
-+ if (of_address_to_resource(node, i, &res)) {
-+ goto out_unmap;
-+ }
-+
-+ size = resource_size(&res);
-+ switch (size) {
-+ case 8:
-+ case 16:
-+ case 32:
-+ size = size / 8;
-+ break;
-+ default:
-+ goto out_unmap;
-+ }
-+
-+ if (words && words != size) {
-+ ret = -EINVAL;
-+ goto out_unmap;
-+ }
-+ words = size;
-+
-+ bases[i] = of_iomap(node, i);
-+ if (!bases[i]) {
-+ ret = -ENOMEM;
-+ goto out_unmap;
-+ }
-+ }
-+
-+ ret = __bcm6345_l2_intc_init(node, num_irqs, irqs, bases, words);
-+ if (!ret)
-+ return 0;
-+
-+out_unmap:
-+ for (i = 0; i < num_irqs; i++) {
-+ iounmap(bases[i]);
-+ irq_dispose_mapping(irqs[i]);
-+ }
-+
-+ return ret;
-+}
-+
-+IRQCHIP_DECLARE(bcm6345_l2_intc, "brcm,bcm6345-l2-intc",
-+ bcm6345_l2_intc_of_init);
-+#endif
---- /dev/null
-+++ b/include/linux/irqchip/irq-bcm6345-l2-intc.h
-@@ -0,0 +1,16 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
-+ * Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr>
-+ */
-+
-+#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_L2_INTC_H
-+#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_L2_INTC_H
-+
-+void bcm6345_l2_intc_init(int num_blocks, int *irq, void __iomem **base,
-+ int num_words);
-+
-+#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_L2_INTC_H */
--- /dev/null
+From 301744ecbeece89ab3a9d6beef7802fa22598f00 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Sun, 30 Nov 2014 14:53:12 +0100
+Subject: [PATCH 1/5] irqchip: add support for bcm6345-style periphery irq
+ controller
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ .../brcm,bcm6345-periph-intc.txt | 50 +++
+ drivers/irqchip/Kconfig | 4 +
+ drivers/irqchip/Makefile | 1 +
+ drivers/irqchip/irq-bcm6345-periph.c | 339 ++++++++++++++++++++
+ include/linux/irqchip/irq-bcm6345-periph.h | 16 +
+ 5 files changed, 410 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-periph-intc.txt
+ create mode 100644 drivers/irqchip/irq-bcm6345-periph.c
+ create mode 100644 include/linux/irqchip/irq-bcm6345-periph.h
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-periph-intc.txt
+@@ -0,0 +1,50 @@
++Broadcom BCM6345 Level 1 periphery interrupt controller
++
++This block is a interrupt controller that is typically connected directly
++to one of the HW INT lines on each CPU. Every BCM63XX xDSL chip since
++BCM6345 has contained this hardware.
++
++Key elements of the hardware design include:
++
++- 32, 64, or 128 incoming level IRQ lines
++
++- All onchip peripherals are wired directly to an L2 input
++
++- A separate instance of the register set for each CPU, allowing individual
++ peripheral IRQs to be routed to any CPU
++
++- No atomic mask/unmask operations
++
++- No polarity/level/edge settings
++
++- No FIFO or priority encoder logic; software is expected to read all
++ 1-4 status words to determine which IRQs are pending
++
++Required properties:
++
++- compatible: Should be "brcm,bcm6345-periph-intc".
++- reg: Specifies the base physical address and size of the registers.
++ Multiple register addresses may be specified, and must match the amount of
++ parent interrupts.
++- interrupt-controller: Identifies the node as an interrupt controller.
++- #interrupt-cells: Specifies the number of cells needed to encode an interrupt
++ source, should be 1.
++- interrupt-parent: Specifies the phandle to the parent interrupt controller
++ this one is cascaded from.
++- interrupts: Specifies the interrupt line(s) in the interrupt-parent controller
++ node, valid values depend on the type of parent interrupt controller.
++ Multiple lines are used to route interrupts to different cpus, with the first
++ assumed to be for the boot CPU.
++
++Example:
++
++periph_intc: interrupt-controller@f0406800 {
++ compatible = "brcm,bcm6345-periph-intc";
++ reg = <0x10000020 0x10>, <0x10000030 0x10>;
++
++ interrupt-controller;
++ #interrupt-cells = <1>;
++
++ interrupt-parent = <&cpu_intc>;
++ interrupts = <2>, <3>;
++};
+--- a/drivers/irqchip/Kconfig
++++ b/drivers/irqchip/Kconfig
+@@ -54,6 +54,10 @@ config BRCMSTB_L2_IRQ
+ select GENERIC_IRQ_CHIP
+ select IRQ_DOMAIN
+
++config BCM6345_PERIPH_IRQ
++ bool
++ select IRQ_DOMAIN
++
+ config DW_APB_ICTL
+ bool
+ select IRQ_DOMAIN
+--- a/drivers/irqchip/Makefile
++++ b/drivers/irqchip/Makefile
+@@ -7,6 +7,7 @@ obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
+ obj-$(CONFIG_ARCH_MVEBU) += irq-armada-370-xp.o
+ obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
+ obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
++obj-$(CONFIG_BCM6345_PERIPH_IRQ) += irq-bcm6345-periph.o
+ obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
+ obj-$(CONFIG_METAG) += irq-metag-ext.o
+ obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
+--- /dev/null
++++ b/drivers/irqchip/irq-bcm6345-periph.c
+@@ -0,0 +1,339 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>
++ */
++
++#include <linux/ioport.h>
++#include <linux/irq.h>
++#include <linux/irqchip/chained_irq.h>
++#include <linux/irqchip/irq-bcm6345-periph.h>
++#include <linux/kernel.h>
++#include <linux/of.h>
++#include <linux/of_irq.h>
++#include <linux/of_address.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++
++#ifdef CONFIG_BCM63XX
++#include <asm/mach-bcm63xx/bcm63xx_irq.h>
++
++#define VIRQ_BASE IRQ_INTERNAL_BASE
++#else
++#define VIRQ_BASE 0
++#endif
++
++#include "irqchip.h"
++
++#define MAX_WORDS 4
++#define MAX_PARENT_IRQS 2
++#define IRQS_PER_WORD 32
++
++struct intc_block {
++ int parent_irq;
++ void __iomem *base;
++ void __iomem *en_reg[MAX_WORDS];
++ void __iomem *status_reg[MAX_WORDS];
++ u32 mask_cache[MAX_WORDS];
++};
++
++struct intc_data {
++ struct irq_chip chip;
++ struct intc_block block[MAX_PARENT_IRQS];
++
++ int num_words;
++
++ struct irq_domain *domain;
++ raw_spinlock_t lock;
++};
++
++static void bcm6345_periph_irq_handle(unsigned int irq, struct irq_desc *desc)
++{
++ struct intc_data *data = irq_desc_get_handler_data(desc);
++ struct irq_chip *chip = irq_desc_get_chip(desc);
++ struct intc_block *block;
++ unsigned int idx;
++
++ chained_irq_enter(chip, desc);
++
++ for (idx = 0; idx < MAX_PARENT_IRQS; idx++)
++ if (irq == data->block[idx].parent_irq)
++ block = &data->block[idx];
++
++ for (idx = 0; idx < data->num_words; idx++) {
++ int base = idx * IRQS_PER_WORD;
++ unsigned long pending;
++ int hw_irq;
++
++ raw_spin_lock(&data->lock);
++ pending = __raw_readl(block->en_reg[idx]) &
++ __raw_readl(block->status_reg[idx]);
++ raw_spin_unlock(&data->lock);
++
++ for_each_set_bit(hw_irq, &pending, IRQS_PER_WORD) {
++ int virq;
++
++ virq = irq_find_mapping(data->domain, base + hw_irq);
++ generic_handle_irq(virq);
++ }
++ }
++
++ chained_irq_exit(chip, desc);
++}
++
++static void __bcm6345_periph_enable(struct intc_block *block, int reg, int bit,
++ bool enable)
++{
++ u32 val;
++
++ val = __raw_readl(block->en_reg[reg]);
++ if (enable)
++ val |= BIT(bit);
++ else
++ val &= ~BIT(bit);
++ __raw_writel(val, block->en_reg[reg]);
++}
++
++static void bcm6345_periph_irq_mask(struct irq_data *data)
++{
++ unsigned int i, reg, bit;
++ struct intc_data *priv = data->domain->host_data;
++ irq_hw_number_t hwirq = irqd_to_hwirq(data);
++
++ reg = hwirq / IRQS_PER_WORD;
++ bit = hwirq % IRQS_PER_WORD;
++
++ raw_spin_lock(&priv->lock);
++ for (i = 0; i < MAX_PARENT_IRQS; i++) {
++ struct intc_block *block = &priv->block[i];
++
++ if (!block->parent_irq)
++ break;
++
++ __bcm6345_periph_enable(block, reg, bit, false);
++ }
++ raw_spin_unlock(&priv->lock);
++}
++
++static void bcm6345_periph_irq_unmask(struct irq_data *data)
++{
++ struct intc_data *priv = data->domain->host_data;
++ irq_hw_number_t hwirq = irqd_to_hwirq(data);
++ unsigned int i, reg, bit;
++
++ reg = hwirq / IRQS_PER_WORD;
++ bit = hwirq % IRQS_PER_WORD;
++
++ raw_spin_lock(&priv->lock);
++ for (i = 0; i < MAX_PARENT_IRQS; i++) {
++ struct intc_block *block = &priv->block[i];
++
++ if (!block->parent_irq)
++ break;
++
++ if (block->mask_cache[reg] & BIT(bit))
++ __bcm6345_periph_enable(block, reg, bit, true);
++ else
++ __bcm6345_periph_enable(block, reg, bit, false);
++ }
++ raw_spin_unlock(&priv->lock);
++}
++
++#ifdef CONFIG_SMP
++static int bcm6345_periph_set_affinity(struct irq_data *data,
++ const struct cpumask *mask, bool force)
++{
++ irq_hw_number_t hwirq = irqd_to_hwirq(data);
++ struct intc_data *priv = data->domain->host_data;
++ unsigned int i, reg, bit;
++ unsigned long flags;
++ bool enabled;
++ int cpu;
++
++ reg = hwirq / IRQS_PER_WORD;
++ bit = hwirq % IRQS_PER_WORD;
++
++ /* we could route to more than one cpu, but performance
++ suffers, so fix it to one.
++ */
++ cpu = cpumask_any_and(mask, cpu_online_mask);
++ if (cpu >= nr_cpu_ids)
++ return -EINVAL;
++
++ if (cpu >= MAX_PARENT_IRQS)
++ return -EINVAL;
++
++ if (!priv->block[cpu].parent_irq)
++ return -EINVAL;
++
++ raw_spin_lock_irqsave(&priv->lock, flags);
++ enabled = !irqd_irq_masked(data);
++ for (i = 0; i < MAX_PARENT_IRQS; i++) {
++ struct intc_block *block = &priv->block[i];
++
++ if (!block->parent_irq)
++ break;
++
++ if (i == cpu) {
++ block->mask_cache[reg] |= BIT(bit);
++ __bcm6345_periph_enable(block, reg, bit, enabled);
++ } else {
++ block->mask_cache[reg] &= ~BIT(bit);
++ __bcm6345_periph_enable(block, reg, bit, false);
++ }
++ }
++ raw_spin_unlock_irqrestore(&priv->lock, flags);
++
++ return 0;
++}
++#endif
++
++static int bcm6345_periph_map(struct irq_domain *d, unsigned int irq,
++ irq_hw_number_t hw)
++{
++ struct intc_data *priv = d->host_data;
++
++ irq_set_chip_and_handler(irq, &priv->chip, handle_level_irq);
++
++ return 0;
++}
++
++static const struct irq_domain_ops bcm6345_periph_domain_ops = {
++ .xlate = irq_domain_xlate_onecell,
++ .map = bcm6345_periph_map,
++};
++
++static int __init __bcm6345_periph_intc_init(struct device_node *node,
++ int num_blocks, int *irq,
++ void __iomem **base, int num_words)
++{
++ struct intc_data *data;
++ unsigned int i, w, status_offset;
++
++ data = kzalloc(sizeof(*data), GFP_KERNEL);
++ if (!data)
++ return -ENOMEM;
++
++ raw_spin_lock_init(&data->lock);
++
++ status_offset = num_words * sizeof(u32);
++
++ for (i = 0; i < num_blocks; i++) {
++ struct intc_block *block = &data->block[i];
++
++ block->parent_irq = irq[i];
++ block->base = base[i];
++
++ for (w = 0; w < num_words; w++) {
++ int word_offset = sizeof(u32) * ((num_words - w) - 1);
++
++ block->en_reg[w] = base[i] + word_offset;
++ block->status_reg[w] = base[i] + status_offset;
++ block->status_reg[w] += word_offset;
++
++ /* route all interrupts to line 0 by default */
++ if (i == 0)
++ block->mask_cache[w] = 0xffffffff;
++ }
++
++ irq_set_handler_data(block->parent_irq, data);
++ irq_set_chained_handler(block->parent_irq,
++ bcm6345_periph_irq_handle);
++ }
++
++ data->num_words = num_words;
++
++ data->chip.name = "bcm6345-periph-intc";
++ data->chip.irq_mask = bcm6345_periph_irq_mask;
++ data->chip.irq_unmask = bcm6345_periph_irq_unmask;
++
++#ifdef CONFIG_SMP
++ if (num_blocks > 1)
++ data->chip.irq_set_affinity = bcm6345_periph_set_affinity;
++#endif
++
++ data->domain = irq_domain_add_simple(node, IRQS_PER_WORD * num_words,
++ VIRQ_BASE,
++ &bcm6345_periph_domain_ops, data);
++ if (!data->domain) {
++ kfree(data);
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++void __init bcm6345_periph_intc_init(int num_blocks, int *irq,
++ void __iomem **base, int num_words)
++{
++ __bcm6345_periph_intc_init(NULL, num_blocks, irq, base, num_words);
++}
++
++#ifdef CONFIG_OF
++static int __init bcm6345_periph_of_init(struct device_node *node,
++ struct device_node *parent)
++{
++ struct resource res;
++ int num_irqs, ret = -EINVAL;
++ int irqs[MAX_PARENT_IRQS] = { 0 };
++ void __iomem *bases[MAX_PARENT_IRQS] = { NULL };
++ int words = 0;
++ int i;
++
++ num_irqs = of_irq_count(node);
++
++ if (num_irqs < 1 || num_irqs > MAX_PARENT_IRQS)
++ return -EINVAL;
++
++ for (i = 0; i < num_irqs; i++) {
++ resource_size_t size;
++
++ irqs[i] = irq_of_parse_and_map(node, i);
++ if (!irqs[i])
++ goto out_unmap;
++
++ if (of_address_to_resource(node, i, &res))
++ goto out_unmap;
++
++ size = resource_size(&res);
++ switch (size) {
++ case 8:
++ case 16:
++ case 32:
++ size = size / 8;
++ break;
++ default:
++ goto out_unmap;
++ }
++
++ if (words && words != size) {
++ ret = -EINVAL;
++ goto out_unmap;
++ }
++ words = size;
++
++ bases[i] = of_iomap(node, i);
++ if (!bases[i]) {
++ ret = -ENOMEM;
++ goto out_unmap;
++ }
++ }
++
++ ret = __bcm6345_periph_intc_init(node, num_irqs, irqs, bases, words);
++ if (!ret)
++ return 0;
++
++out_unmap:
++ for (i = 0; i < num_irqs; i++) {
++ iounmap(bases[i]);
++ irq_dispose_mapping(irqs[i]);
++ }
++
++ return ret;
++}
++
++IRQCHIP_DECLARE(bcm6345_periph_intc, "brcm,bcm6345-periph-intc",
++ bcm6345_periph_of_init);
++#endif
+--- /dev/null
++++ b/include/linux/irqchip/irq-bcm6345-periph.h
+@@ -0,0 +1,16 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
++ * Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr>
++ */
++
++#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H
++#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H
++
++void bcm6345_periph_intc_init(int num_blocks, int *irq, void __iomem **base,
++ int num_words);
++
++#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H */
-From 6896b5f0538a7a7cfb7fac2d9ed3c6841c72ed40 Mon Sep 17 00:00:00 2001
+From cf908990d4a8ccdb73ee4484aa8cadad379ca314 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Sun, 30 Nov 2014 14:54:27 +0100
-Subject: [PATCH 18/20] irqchip: add support for bcm6345-style external
+Subject: [PATCH 2/5] irqchip: add support for bcm6345-style external
interrupt controller
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
- .../interrupt-controller/brcm,bcm6345-ext-intc.txt | 24 ++
+ .../interrupt-controller/brcm,bcm6345-ext-intc.txt | 29 ++
drivers/irqchip/Kconfig | 4 +
drivers/irqchip/Makefile | 1 +
- drivers/irqchip/irq-bcm6345-ext.c | 296 ++++++++++++++++++++
- include/linux/irqchip/irq-bcm6345-ext-intc.h | 14 +
- 5 files changed, 339 insertions(+)
+ drivers/irqchip/irq-bcm6345-ext.c | 287 ++++++++++++++++++++
+ include/linux/irqchip/irq-bcm6345-ext.h | 14 +
+ 5 files changed, 335 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.txt
create mode 100644 drivers/irqchip/irq-bcm6345-ext.c
- create mode 100644 include/linux/irqchip/irq-bcm6345-ext-intc.h
+ create mode 100644 include/linux/irqchip/irq-bcm6345-ext.h
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.txt
-@@ -0,0 +1,24 @@
+@@ -0,0 +1,29 @@
+Broadcom BCM6345-style external interrupt controller
+
+Required properties:
+
-+- compatible: should be "brcm,bcm6345-l2-intc" or "brcm,bcm6345-l2-intc"
-+- reg: specifies the base physical addresses and size of the registers.
-+- interrupt-controller: identifies the node as an interrupt controller
-+- #interrupt-cells: specifies the number of cells needed to encode an interrupt
-+ source, should be 2
-+- interrupt-parent: specifies the phandle to the parent interrupt controller
-+ this one is cascaded from
-+- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
-+ node, valid values depend on the type of parent interrupt controller
++- compatible: Should be "brcm,bcm6345-l2-intc".
++- reg: Specifies the base physical addresses and size of the registers.
++- interrupt-controller: identifies the node as an interrupt controller.
++- #interrupt-cells: Specifies the number of cells needed to encode an interrupt
++ source, Should be 2.
++- interrupt-parent: Specifies the phandle to the parent interrupt controller
++ this one is cascaded from.
++- interrupts: Specifies the interrupt line(s) in the interrupt-parent controller
++ node, valid values depend on the type of parent interrupt controller.
++
++Optional properties:
++
++- brcm,field-width: Size of each field (mask, clear, sense, ...) in bits in the
++ register. Defaults to 4.
+
+Example:
+
+ bool
+ select IRQ_DOMAIN
+
- config BCM6345_L2_IRQ
+ config BCM6345_PERIPH_IRQ
bool
select IRQ_DOMAIN
--- a/drivers/irqchip/Makefile
obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
+obj-$(CONFIG_BCM6345_EXT_IRQ) += irq-bcm6345-ext.o
- obj-$(CONFIG_BCM6345_L2_IRQ) += irq-bcm6345-l2.o
+ obj-$(CONFIG_BCM6345_PERIPH_IRQ) += irq-bcm6345-periph.o
obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
obj-$(CONFIG_METAG) += irq-metag-ext.o
--- /dev/null
+++ b/drivers/irqchip/irq-bcm6345-ext.c
-@@ -0,0 +1,296 @@
+@@ -0,0 +1,287 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>
-+i */
++ */
+
+#include <linux/ioport.h>
+#include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
-+#include <linux/irqchip/irq-bcm6345-ext-intc.h>
++#include <linux/irqchip/irq-bcm6345-ext.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+struct intc_data {
+ struct irq_chip chip;
+ struct irq_domain *domain;
-+ spinlock_t lock;
++ raw_spinlock_t lock;
+
+ int parent_irq[MAX_IRQS];
+ void __iomem *reg;
+ irq_hw_number_t hwirq = irqd_to_hwirq(data);
+ u32 reg;
+
-+ raw_spin_lock(priv->lock);
++ raw_spin_lock(&priv->lock);
+ reg = __raw_readl(priv->reg);
+ reg |= hwirq << (EXTIRQ_CFG_CLEAR * priv->shift);
+ __raw_writel(reg, priv->reg);
-+ raw_spin_unlock(priv->lock);
++ raw_spin_unlock(&priv->lock);
+}
+
+static void bcm6345_ext_intc_irq_mask(struct irq_data *data)
+ irq_hw_number_t hwirq = irqd_to_hwirq(data);
+ u32 reg;
+
-+ raw_spin_lock(priv->lock);
++ raw_spin_lock(&priv->lock);
+ reg = __raw_readl(priv->reg);
+ reg &= ~(hwirq << (EXTIRQ_CFG_MASK * priv->shift));
+ __raw_writel(reg, priv->reg);
-+ raw_spin_unlock(priv->lock);
++ raw_spin_unlock(&priv->lock);
+}
+
+static void bcm6345_ext_intc_irq_unmask(struct irq_data *data)
+ irq_hw_number_t hwirq = irqd_to_hwirq(data);
+ u32 reg;
+
-+ raw_spin_lock(priv->lock);
++ raw_spin_lock(&priv->lock);
+ reg = __raw_readl(priv->reg);
+ reg |= hwirq << (EXTIRQ_CFG_MASK * priv->shift);
+ __raw_writel(reg, priv->reg);
-+ raw_spin_unlock(priv->lock);
++ raw_spin_unlock(&priv->lock);
+}
+
+static int bcm6345_ext_intc_set_type(struct irq_data *data,
+ return -EINVAL;
+ }
+
-+ raw_spin_lock(priv->lock);
++ raw_spin_lock(&priv->lock);
+ reg = __raw_readl(priv->reg);
+
+ if (levelsense)
+ reg &= ~(hwirq << (EXTIRQ_CFG_BOTHEDGE * priv->shift));
+
+ __raw_writel(reg, priv->reg);
-+ raw_spin_unlock(priv->lock);
++ raw_spin_unlock(&priv->lock);
+
+ irqd_set_trigger_type(data, flow_type);
+ if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
+}
+
+static int bcm6345_ext_intc_map(struct irq_domain *d, unsigned int irq,
-+ irq_hw_number_t hw)
++ irq_hw_number_t hw)
+{
+ struct intc_data *priv = d->host_data;
+
+ return 0;
+}
+
-+
+static const struct irq_domain_ops bcm6345_ext_domain_ops = {
+ .xlate = irq_domain_xlate_twocell,
+ .map = bcm6345_ext_intc_map,
+ if (!data)
+ return -ENOMEM;
+
++ raw_spin_lock_init(&data->lock);
++
+ for (i = 0; i < num_irqs; i++) {
+ data->parent_irq[i] = irqs[i];
+
+}
+
+#ifdef CONFIG_OF
-+static int __init bcm63xx_ext_intc_of_init(struct device_node *node,
-+ struct device_node *parent,
-+ int shift)
++static int __init bcm6345_ext_intc_of_init(struct device_node *node,
++ struct device_node *parent)
+{
+ int num_irqs, ret = -EINVAL;
+ unsigned i;
+ void __iomem *base;
+ int irqs[MAX_IRQS] = { 0 };
++ u32 shift;
+
+ num_irqs = of_irq_count(node);
+
+ if (!num_irqs || num_irqs > MAX_IRQS)
+ return -EINVAL;
+
++ if (of_property_read_u32(node, "brcm,field-width", &shift))
++ shift = 4;
++
+ for (i = 0; i < num_irqs; i++) {
+ irqs[i] = irq_of_parse_and_map(node, i);
+ if (!irqs[i]) {
+ return ret;
+}
+
-+static int __init bcm6345_ext_intc_of_init(struct device_node *node,
-+ struct device_node *parent)
-+{
-+ return bcm63xx_ext_intc_of_init(node, parent, 4);
-+}
-+static int __init bcm6348_ext_intc_of_init(struct device_node *node,
-+ struct device_node *parent)
-+{
-+ return bcm63xx_ext_intc_of_init(node, parent, 5);
-+}
-+
+IRQCHIP_DECLARE(bcm6345_ext_intc, "brcm,bcm6345-ext-intc",
+ bcm6345_ext_intc_of_init);
-+IRQCHIP_DECLARE(bcm6348_ext_intc, "brcm,bcm6348-ext-intc",
-+ bcm6348_ext_intc_of_init);
+#endif
--- /dev/null
-+++ b/include/linux/irqchip/irq-bcm6345-ext-intc.h
++++ b/include/linux/irqchip/irq-bcm6345-ext.h
@@ -0,0 +1,14 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>
+ */
+
-+#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_INTC_H
-+#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_INTC_H
++#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H
++#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H
+
+void bcm6345_ext_intc_init(int n_irqs, int *irqs, void __iomem *reg, int shift);
+
-+#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_INTC_H */
++#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H */
-From d93661c9e164ccc41820eeb4f1881e59a34a9e5c Mon Sep 17 00:00:00 2001
+From cfe7647c2a4decf874dff8abb60704e9917f76fe Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Sun, 30 Nov 2014 14:55:02 +0100
-Subject: [PATCH 19/20] MIPS: BCM63XX: switch to IRQ_DOMAIN
+Subject: [PATCH 3/5] MIPS: BCM63XX: switch to IRQ_DOMAIN
Now that we have working IRQ_DOMAIN drivers for both interrupt controllers,
switch to using them.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
arch/mips/Kconfig | 3 +
- arch/mips/bcm63xx/irq.c | 608 ++++++++---------------------------------------
- 2 files changed, 108 insertions(+), 503 deletions(-)
+ arch/mips/bcm63xx/irq.c | 609 +++++++++--------------------------------------
+ 2 files changed, 109 insertions(+), 503 deletions(-)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
select DMA_NONCOHERENT
select IRQ_CPU
+ select BCM6345_EXT_IRQ
-+ select BCM6345_L2_IRQ
++ select BCM6345_PERIPH_IRQ
+ select IRQ_DOMAIN
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
#include <linux/irq.h>
-#include <linux/spinlock.h>
+#include <linux/irqchip.h>
-+#include <linux/irqchip/irq-bcm6345-ext-intc.h>
-+#include <linux/irqchip/irq-bcm6345-l2-intc.h>
++#include <linux/irqchip/irq-bcm6345-ext.h>
++#include <linux/irqchip/irq-bcm6345-periph.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <bcm63xx_cpu.h>
-@@ -20,544 +22,144 @@
+@@ -20,544 +22,145 @@
#include <bcm63xx_io.h>
#include <bcm63xx_irq.h>
- irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF);
- irq_stat_addr[1] = bcm63xx_regset_address(RSET_PERF);
- irq_mask_addr[1] = bcm63xx_regset_address(RSET_PERF);
-+ void __iomem *l2_intc_bases[2];
++ void __iomem *periph_bases[2];
+ void __iomem *ext_intc_bases[2];
-+ int l2_irq_count, l2_width, ext_irq_count, ext_shift;
-+ int l2_irqs[2] = { 2, 3 };
++ int periph_irq_count, periph_width, ext_irq_count, ext_shift;
++ int periph_irqs[2] = { 2, 3 };
+ int ext_irqs[6];
+
-+ l2_intc_bases[0] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
-+ l2_intc_bases[1] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
++ periph_bases[0] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
++ periph_bases[1] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
+ ext_intc_bases[0] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
+ ext_intc_bases[1] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
- irq_bits = 32;
- ext_irq_count = 4;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
-+ l2_intc_bases[0] += PERF_IRQMASK_3368_REG;
-+ l2_irq_count = 1;
-+ l2_width = 1;
++ periph_bases[0] += PERF_IRQMASK_3368_REG;
++ periph_irq_count = 1;
++ periph_width = 1;
+
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_3368;
+ ext_irq_count = 4;
- ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
- ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
-+ l2_intc_bases[0] += PERF_IRQMASK_6328_REG(0);
-+ l2_intc_bases[1] += PERF_IRQMASK_6328_REG(1);
-+ l2_irq_count = 2;
-+ l2_width = 2;
++ periph_bases[0] += PERF_IRQMASK_6328_REG(0);
++ periph_bases[1] += PERF_IRQMASK_6328_REG(1);
++ periph_irq_count = 2;
++ periph_width = 2;
+
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6328;
+ ext_irq_count = 4;
- irq_bits = 32;
- ext_irq_count = 4;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
-+ l2_intc_bases[0] += PERF_IRQMASK_6338_REG;
-+ l2_irq_count = 1;
-+ l2_width = 1;
++ periph_bases[0] += PERF_IRQMASK_6338_REG;
++ periph_irq_count = 1;
++ periph_width = 1;
+
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6338;
+ ext_irq_count = 4;
- irq_bits = 32;
- ext_irq_count = 4;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
-+ l2_intc_bases[0] += PERF_IRQMASK_6345_REG;
-+ l2_irq_count = 1;
-+ l2_width = 1;
++ periph_bases[0] += PERF_IRQMASK_6345_REG;
++ periph_irq_count = 1;
++ periph_width = 1;
+
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6345;
+ ext_irq_count = 4;
- irq_bits = 32;
- ext_irq_count = 4;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
-+ l2_intc_bases[0] += PERF_IRQMASK_6348_REG;
-+ l2_irq_count = 1;
-+ l2_width = 1;
++ periph_bases[0] += PERF_IRQMASK_6348_REG;
++ periph_irq_count = 1;
++ periph_width = 1;
+
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6348;
+ ext_irq_count = 4;
- ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
- ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
-+ l2_intc_bases[0] += PERF_IRQMASK_6358_REG(0);
-+ l2_intc_bases[1] += PERF_IRQMASK_6358_REG(1);
-+ l2_irq_count = 2;
-+ l2_width = 1;
++ periph_bases[0] += PERF_IRQMASK_6358_REG(0);
++ periph_bases[1] += PERF_IRQMASK_6358_REG(1);
++ periph_irq_count = 2;
++ periph_width = 1;
+
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6358;
+ ext_irq_count = 4;
- ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;
- ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
-+ l2_intc_bases[0] += PERF_IRQMASK_6362_REG(0);
-+ l2_intc_bases[1] += PERF_IRQMASK_6362_REG(1);
-+ l2_irq_count = 2;
-+ l2_width = 2;
++ periph_bases[0] += PERF_IRQMASK_6362_REG(0);
++ periph_bases[1] += PERF_IRQMASK_6362_REG(1);
++ periph_irq_count = 2;
++ periph_width = 2;
+
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6362;
+ ext_irq_count = 4;
- irq_stat_addr[1] += PERF_IRQSTAT_6368_REG(1);
- irq_mask_addr[1] += PERF_IRQMASK_6368_REG(1);
- irq_bits = 64;
-+ l2_intc_bases[0] += PERF_IRQMASK_6368_REG(0);
-+ l2_intc_bases[1] += PERF_IRQMASK_6368_REG(1);
-+ l2_irq_count = 2;
-+ l2_width = 2;
++ periph_bases[0] += PERF_IRQMASK_6368_REG(0);
++ periph_bases[1] += PERF_IRQMASK_6368_REG(1);
++ periph_irq_count = 2;
++ periph_width = 2;
+
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6368;
+ ext_intc_bases[1] += PERF_EXTIRQ_CFG_REG2_6368;
- internal_irq_unmask = __internal_irq_unmask_64;
- }
+ mips_cpu_irq_init();
-+ bcm6345_l2_intc_init(l2_irq_count, l2_irqs, l2_intc_bases, l2_width);
++ bcm6345_periph_intc_init(periph_irq_count, periph_irqs, periph_bases,
++ periph_width);
+ bcm6345_ext_intc_init(4, ext_irqs, ext_intc_bases[0], ext_shift);
+ if (ext_irq_count > 4)
+ bcm6345_ext_intc_init(2, &ext_irqs[4], ext_intc_bases[1],
-From e3c68bbba30b212326fb69bf64b2220750dead3e Mon Sep 17 00:00:00 2001
+From 4fd286c3e5a5bebab0391cf1937695b3ed6721a3 Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Sun, 30 Nov 2014 20:20:30 +0100
-Subject: [PATCH 20/20] MIPS: BCM63XX: wire up BCM6358's external interrupts 4
+Subject: [PATCH 4/5] MIPS: BCM63XX: wire up BCM6358's external interrupts 4
and 5
Due to the external interrupts being non consecutive, the previous
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -109,11 +109,14 @@ static void bcm63xx_init_irq(void)
- l2_width = 1;
+ periph_width = 1;
ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6358;
- ext_irq_count = 4;
ext_shift = 4;
break;
+ case BCM63268_CPU_ID:
-+ l2_intc_bases[0] += PERF_IRQSTAT_63268_REG(0);
-+ l2_intc_bases[1] += PERF_IRQSTAT_63268_REG(1);
-+ l2_irq_count = 2;
-+ l2_width = 4;
++ periph_bases[0] += PERF_IRQSTAT_63268_REG(0);
++ periph_bases[1] += PERF_IRQSTAT_63268_REG(1);
++ periph_irq_count = 2;
++ periph_width = 4;
+
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_63268;
+ ext_irq_count = 4;
ext_shift = 4;
break;
+ case BCM6318_CPU_ID:
-+ l2_intc_bases[0] += PERF_IRQMASK_6318_REG;
-+ l2_irq_count = 1;
-+ l2_width = 4;
++ periph_bases[0] += PERF_IRQMASK_6318_REG;
++ periph_irq_count = 1;
++ periph_width = 4;
+
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6318;
+ ext_irq_count = 4;
+ ext_shift = 4;
+ break;
case BCM6328_CPU_ID:
- l2_intc_bases[0] += PERF_IRQMASK_6328_REG(0);
- l2_intc_bases[1] += PERF_IRQMASK_6328_REG(1);
+ periph_bases[0] += PERF_IRQMASK_6328_REG(0);
+ periph_bases[1] += PERF_IRQMASK_6328_REG(1);
--- a/arch/mips/bcm63xx/prom.c
+++ b/arch/mips/bcm63xx/prom.c
@@ -72,7 +72,7 @@ void __init prom_init(void)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
-@@ -2645,6 +2645,24 @@ config RAPIDIO
+@@ -2655,6 +2655,24 @@ config RAPIDIO
source "drivers/rapidio/Kconfig"
-From 7c22b08baba941a8c83072047b0d2b55a6b952aa Mon Sep 17 00:00:00 2001
+From 8a0803979163c647736cb234ee1620c049c4915c Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jogo@openwrt.org>
Date: Mon, 1 Dec 2014 00:20:07 +0100
-Subject: [PATCH] MIPS: BCM63XX: register interrupt controllers through DT
+Subject: [PATCH 5/5] MIPS: BCM63XX: register interrupt controllers through DT
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
---
- arch/mips/bcm63xx/irq.c | 10 +++++++++-
- 1 file changed, 9 insertions(+), 1 deletion(-)
+ arch/mips/bcm63xx/irq.c | 12 +++++++++++-
+ 1 file changed, 11 insertions(+), 1 deletion(-)
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -15,6 +15,8 @@
#include <linux/irqchip.h>
- #include <linux/irqchip/irq-bcm6345-ext-intc.h>
- #include <linux/irqchip/irq-bcm6345-l2-intc.h>
+ #include <linux/irqchip/irq-bcm6345-ext.h>
+ #include <linux/irqchip/irq-bcm6345-periph.h>
+#include <linux/of.h>
+#include <linux/of_fdt.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <bcm63xx_cpu.h>
-@@ -189,7 +191,13 @@ static void bcm63xx_init_irq(void)
+@@ -190,7 +192,15 @@ static void bcm63xx_init_irq(void)
ext_shift);
}
void __init arch_init_irq(void)
{
- bcm63xx_init_irq();
++#ifdef CONFIG_OF
+ if (initial_boot_params)
+ irqchip_init();
+ else
++#endif
+ bcm63xx_init_irq();
}
void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr,
-@@ -167,8 +145,8 @@ void dma_free_noncoherent(struct device
+@@ -167,8 +145,8 @@ void dma_free_noncoherent(struct device
}
EXPORT_SYMBOL(dma_free_noncoherent);
void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
enum dma_data_direction direction)
-@@ -360,23 +238,10 @@ void dma_cache_sync(struct device *dev,
+@@ -360,23 +238,10 @@ void dma_cache_sync(struct device *dev,
EXPORT_SYMBOL(dma_cache_sync);
--- a/scripts/kallsyms.c
+++ b/scripts/kallsyms.c
-@@ -58,6 +58,7 @@ static struct addr_range percpu_range =
+@@ -58,6 +58,7 @@ static struct addr_range percpu_range =
static struct sym_entry *table;
static unsigned int table_size, table_cnt;
static int all_symbols = 0;
#ifdef MODULE
#define __MODULE_INFO(tag, name, info) \
static const char __UNIQUE_ID(name)[] \
-@@ -23,8 +33,7 @@ static const char __UNIQUE_ID(name)[]
+@@ -23,8 +33,7 @@ static const char __UNIQUE_ID(name)[]
= __stringify(tag) "=" info
#else /* !MODULE */
/* This struct is here for syntactic coherency, it is not used */
#endif
#define __MODULE_PARM_TYPE(name, _type) \
__MODULE_INFO(parmtype, name##type, #name ":" _type)
-@@ -32,7 +41,7 @@ static const char __UNIQUE_ID(name)[]
+@@ -32,7 +41,7 @@ static const char __UNIQUE_ID(name)[]
/* One for each parameter, describing how to use it. Some files do
multiple of these per line, so can't just use MODULE_INFO. */
#define MODULE_PARM_DESC(_parm, desc) \
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
-@@ -325,7 +325,7 @@ cmd_bzip2 = (cat $(filter-out FORCE,$^)
+@@ -325,7 +325,7 @@ cmd_bzip2 = (cat $(filter-out FORCE,$^)
quiet_cmd_lzma = LZMA $@
cmd_lzma = (cat $(filter-out FORCE,$^) | \
--- a/arch/mips/include/asm/string.h
+++ b/arch/mips/include/asm/string.h
-@@ -133,11 +133,44 @@ strncmp(__const__ char *__cs, __const__
+@@ -133,11 +133,44 @@ strncmp(__const__ char *__cs, __const__
#define __HAVE_ARCH_MEMSET
extern void *memset(void *__s, int __c, size_t __count);
default y
--- a/drivers/mtd/mtdpart.c
+++ b/drivers/mtd/mtdpart.c
-@@ -681,6 +681,47 @@ mtd_pad_erasesize(struct mtd_info *mtd,
+@@ -681,6 +681,47 @@ mtd_pad_erasesize(struct mtd_info *mtd,
return len;
}
u64 offset, uint32_t mask_flags)
{
part->name = name;
-@@ -58,6 +59,26 @@ static void bcm47xxpart_add_part(struct
+@@ -58,6 +59,26 @@ static void bcm47xxpart_add_part(struct
part->mask_flags = mask_flags;
}
static struct proc_dir_entry *my_proc_entry;
static char *yaffs_dump_dev_part0(char *buf, struct yaffs_dev *dev)
-@@ -3398,6 +3399,7 @@ static int yaffs_proc_write(struct file
+@@ -3398,6 +3399,7 @@ static int yaffs_proc_write(struct file
return yaffs_proc_debug_write(file, buf, count, data);
return yaffs_proc_write_trace_options(file, buf, count, data);
}
depends on NETFILTER_ADVANCED
--- a/net/netfilter/Makefile
+++ b/net/netfilter/Makefile
-@@ -162,6 +162,7 @@ obj-$(CONFIG_NETFILTER_XT_MATCH_RECENT)
+@@ -162,6 +162,7 @@ obj-$(CONFIG_NETFILTER_XT_MATCH_RECENT)
obj-$(CONFIG_NETFILTER_XT_MATCH_SCTP) += xt_sctp.o
obj-$(CONFIG_NETFILTER_XT_MATCH_SOCKET) += xt_socket.o
obj-$(CONFIG_NETFILTER_XT_MATCH_STATE) += xt_state.o
#include <net/net_namespace.h>
#ifdef CONFIG_SYSCTL
#include <linux/sysctl.h>
-@@ -268,10 +269,66 @@ static int ct_open(struct inode *inode,
+@@ -268,10 +269,66 @@ static int ct_open(struct inode *inode,
sizeof(struct ct_iter_state));
}
depends on NETFILTER_ADVANCED
--- a/net/netfilter/Makefile
+++ b/net/netfilter/Makefile
-@@ -140,6 +140,7 @@ obj-$(CONFIG_NETFILTER_XT_MATCH_ESP) +=
+@@ -140,6 +140,7 @@ obj-$(CONFIG_NETFILTER_XT_MATCH_ESP) +=
obj-$(CONFIG_NETFILTER_XT_MATCH_HASHLIMIT) += xt_hashlimit.o
obj-$(CONFIG_NETFILTER_XT_MATCH_HELPER) += xt_helper.o
obj-$(CONFIG_NETFILTER_XT_MATCH_HL) += xt_hl.o
Ethernet bridge, which means that the different Ethernet segments it
--- a/net/ipv6/Makefile
+++ b/net/ipv6/Makefile
-@@ -45,6 +45,7 @@ obj-y += addrconf_core.o exthdrs_core.o
+@@ -45,6 +45,7 @@ obj-y += addrconf_core.o exthdrs_core.o
obj-$(CONFIG_INET) += output_core.o protocol.o $(ipv6-offload)
obj-$(subst m,y,$(CONFIG_IPV6)) += inet6_hashtables.o
}
#endif
-@@ -1556,6 +1581,7 @@ static int br_multicast_ipv4_rcv(struct
+@@ -1556,6 +1581,7 @@ static int br_multicast_ipv4_rcv(struct
struct sk_buff *skb,
u16 vid)
{
struct sk_buff *skb2 = skb;
const struct iphdr *iph;
struct igmphdr *ih;
-@@ -1629,7 +1655,7 @@ static int br_multicast_ipv4_rcv(struct
+@@ -1629,7 +1655,7 @@ static int br_multicast_ipv4_rcv(struct
case IGMP_HOST_MEMBERSHIP_REPORT:
case IGMPV2_HOST_MEMBERSHIP_REPORT:
BR_INPUT_SKB_CB(skb)->mrouters_only = 1;
break;
case IGMPV3_HOST_MEMBERSHIP_REPORT:
err = br_ip4_multicast_igmp3_report(br, port, skb2, vid);
-@@ -1638,7 +1664,7 @@ static int br_multicast_ipv4_rcv(struct
+@@ -1638,7 +1664,7 @@ static int br_multicast_ipv4_rcv(struct
err = br_ip4_multicast_query(br, port, skb2, vid);
break;
case IGMP_HOST_LEAVE_MESSAGE:
break;
}
-@@ -1656,6 +1682,7 @@ static int br_multicast_ipv6_rcv(struct
+@@ -1656,6 +1682,7 @@ static int br_multicast_ipv6_rcv(struct
struct sk_buff *skb,
u16 vid)
{
struct sk_buff *skb2;
const struct ipv6hdr *ip6h;
u8 icmp6_type;
-@@ -1765,7 +1792,8 @@ static int br_multicast_ipv6_rcv(struct
+@@ -1765,7 +1792,8 @@ static int br_multicast_ipv6_rcv(struct
}
mld = (struct mld_msg *)skb_transport_header(skb2);
BR_INPUT_SKB_CB(skb)->mrouters_only = 1;
break;
}
case ICMPV6_MLD2_REPORT:
-@@ -1782,7 +1810,7 @@ static int br_multicast_ipv6_rcv(struct
+@@ -1782,7 +1810,7 @@ static int br_multicast_ipv6_rcv(struct
goto out;
}
mld = (struct mld_msg *)skb_transport_header(skb2);
--- a/net/netlink/af_netlink.c
+++ b/net/netlink/af_netlink.c
-@@ -1715,27 +1715,7 @@ void netlink_detachskb(struct sock *sk,
+@@ -1715,27 +1715,7 @@ void netlink_detachskb(struct sock *sk,
static struct sk_buff *netlink_trim(struct sk_buff *skb, gfp_t allocation)
{
}
--- a/net/sched/sch_fifo.c
+++ b/net/sched/sch_fifo.c
-@@ -29,17 +29,21 @@ static int bfifo_enqueue(struct sk_buff
+@@ -29,17 +29,21 @@ static int bfifo_enqueue(struct sk_buff
static int pfifo_enqueue(struct sk_buff *skb, struct Qdisc *sch)
{
err = ip6_tnl_xmit2(skb, dev, dsfield, &fl6, encap_limit, &mtu);
if (err != 0) {
/* XXX: send ICMP error even if DF is not set. */
-@@ -1263,6 +1413,14 @@ ip6_tnl_change(struct ip6_tnl *t, const
+@@ -1263,6 +1413,14 @@ ip6_tnl_change(struct ip6_tnl *t, const
t->parms.flowinfo = p->flowinfo;
t->parms.link = p->link;
t->parms.proto = p->proto;
--- a/net/ipv4/fib_semantics.c
+++ b/net/ipv4/fib_semantics.c
-@@ -138,6 +138,10 @@ const struct fib_prop fib_props[RTN_MAX
+@@ -138,6 +138,10 @@ const struct fib_prop fib_props[RTN_MAX
.error = -EINVAL,
.scope = RT_SCOPE_NOWHERE,
},
--- a/drivers/net/wireless/hostap/hostap_ap.c
+++ b/drivers/net/wireless/hostap/hostap_ap.c
-@@ -2403,13 +2403,13 @@ int prism2_ap_get_sta_qual(local_info_t
+@@ -2403,13 +2403,13 @@ int prism2_ap_get_sta_qual(local_info_t
addr[count].sa_family = ARPHRD_ETHER;
memcpy(addr[count].sa_data, sta->addr, ETH_ALEN);
if (sta->last_rx_silence == 0)
#include <bcm47xx_nvram.h>
static const struct bcma_device_id bgmac_bcma_tbl[] = {
-@@ -1405,6 +1406,17 @@ static void bgmac_mii_unregister(struct
+@@ -1405,6 +1406,17 @@ static void bgmac_mii_unregister(struct
mdiobus_free(mii_bus);
}
default y
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
-@@ -41,6 +41,7 @@ static void quirk_mmio_always_on(struct
+@@ -41,6 +41,7 @@ static void quirk_mmio_always_on(struct
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
&fib_triestat_fops))
goto out2;
-@@ -2594,17 +2596,21 @@ int __net_init fib_proc_init(struct net
+@@ -2594,17 +2596,21 @@ int __net_init fib_proc_init(struct net
return 0;
out3:
* All of these routines try to estimate how many bits of randomness a
* particular randomness source. They do this by keeping track of the
* first and second order deltas of the event timings.
-@@ -938,6 +948,63 @@ void add_disk_randomness(struct gendisk
+@@ -938,6 +948,63 @@ void add_disk_randomness(struct gendisk
EXPORT_SYMBOL_GPL(add_disk_randomness);
#endif
projects / openwrt / staging / ynezz.git / commitdiff