drm/amdgpu: Only retrieve GPU address of GART table after pinning it

Doing it earlier hits a WARN_ON_ONCE in amdgpu_bo_gpu_offset.

Fixes: "drm/amdgpu: remove gart.table_addr"
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 543287e5d67bf49b02f6ac0a5b52232123e15a04..9c45ea318bd65e68774fda7f766348e605218b5f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -494,7 +494,7 @@ static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
 
 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
 {
-       uint64_t table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
+       uint64_t table_addr;
        int r, i;
        u32 field;
 
@@ -505,6 +505,9 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
        r = amdgpu_gart_table_vram_pin(adev);
        if (r)
                return r;
+
+       table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
+
        /* Setup TLB control */
        WREG32(mmMC_VM_MX_L1_TLB_CNTL,
               (0xA << 7) |

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index c88708abe016946ef83a797be548144771006774..d3400064e9db2423a967b2ea0fa3db606796ed83 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -602,7 +602,7 @@ static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
  */
 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
 {
-       uint64_t table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
+       uint64_t table_addr;
        int r, i;
        u32 tmp, field;
 
@@ -613,6 +613,9 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
        r = amdgpu_gart_table_vram_pin(adev);
        if (r)
                return r;
+
+       table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
+
        /* Setup TLB control */
        tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
        tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 8213ea1a6cbc7d5a3156e5facfbe906bd70cc8ff..fb0d57655f78c09d2f1629699e362378b6c6fe99 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -807,7 +807,7 @@ static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
  */
 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
 {
-       uint64_t table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
+       uint64_t table_addr;
        int r, i;
        u32 tmp, field;
 
@@ -818,6 +818,9 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
        r = amdgpu_gart_table_vram_pin(adev);
        if (r)
                return r;
+
+       table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
+
        /* Setup TLB control */
        tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
        tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);