#define NV_DEVICE_V0_DISABLE_CE0 0x0000008000000000ULL
#define NV_DEVICE_V0_DISABLE_CE1 0x0000010000000000ULL
#define NV_DEVICE_V0_DISABLE_VIC 0x0000020000000000ULL
-#define NV_DEVICE_V0_DISABLE_VENC 0x0000040000000000ULL
+#define NV_DEVICE_V0_DISABLE_MSENC 0x0000040000000000ULL
#define NV_DEVICE_V0_DISABLE_CE2 0x0000080000000000ULL
#define NV_DEVICE_V0_DISABLE_MSVLD 0x0000100000000000ULL
#define NV_DEVICE_V0_DISABLE_SEC 0x0000200000000000ULL
[NVDEV_ENGINE_CE1] = NV_DEVICE_V0_DISABLE_CE1,
[NVDEV_ENGINE_CE2] = NV_DEVICE_V0_DISABLE_CE2,
[NVDEV_ENGINE_VIC] = NV_DEVICE_V0_DISABLE_VIC,
- [NVDEV_ENGINE_VENC] = NV_DEVICE_V0_DISABLE_VENC,
+ [NVDEV_ENGINE_MSENC] = NV_DEVICE_V0_DISABLE_MSENC,
[NVDEV_ENGINE_DISP] = NV_DEVICE_V0_DISABLE_DISP,
[NVDEV_ENGINE_MSVLD] = NV_DEVICE_V0_DISABLE_MSVLD,
[NVDEV_ENGINE_SEC] = NV_DEVICE_V0_DISABLE_SEC,
_(NVDEV_ENGINE_MSVLD , 0),
_(NVDEV_ENGINE_CE0 , 0),
_(NVDEV_ENGINE_CE1 , 0),
- _(NVDEV_ENGINE_VENC , 0),
+ _(NVDEV_ENGINE_MSENC , 0),
};
#undef _
#define FIFO_ENGINE_NR ARRAY_SIZE(fifo_engine)
case NVDEV_ENGINE_VP : engn = 3; break;
case NVDEV_ENGINE_CE0 : engn = 4; break;
case NVDEV_ENGINE_CE1 : engn = 5; break;
- case NVDEV_ENGINE_VENC : engn = 6; break;
+ case NVDEV_ENGINE_MSENC: engn = 6; break;
default:
return -1;
}
{ 0x15, "CE0", NULL, NVDEV_ENGINE_CE0 },
{ 0x16, "CE1", NULL, NVDEV_ENGINE_CE1 },
{ 0x17, "PMU" },
- { 0x19, "MSENC", NULL, NVDEV_ENGINE_VENC },
+ { 0x19, "MSENC", NULL, NVDEV_ENGINE_MSENC },
{ 0x1b, "CE2", NULL, NVDEV_ENGINE_CE2 },
{}
};
if (r022500 & 0x00000004)
disable |= (1ULL << NVDEV_ENGINE_MSVLD);
if (r022500 & 0x00000008)
- disable |= (1ULL << NVDEV_ENGINE_VENC);
+ disable |= (1ULL << NVDEV_ENGINE_MSENC);
if (r022500 & 0x00000100)
disable |= (1ULL << NVDEV_ENGINE_CE0);
if (r022500 & 0x00000200)