ipq807x: mark merged patches as backports

These 3 patches have been merged upstream, so mark them as backports
along with the kernel version they have been merged into.

Signed-off-by: Robert Marko <robimarko@gmail.com>

diff --git a/target/linux/ipq807x/patches-5.15/0080-v6.3-arm64-dts-qcom-ipq8074-set-Gen2-PCIe-pcie-max-link-s.patch b/target/linux/ipq807x/patches-5.15/0080-v6.3-arm64-dts-qcom-ipq8074-set-Gen2-PCIe-pcie-max-link-s.patch
new file mode 100644 (file)
index 0000000..8719bf7
--- /dev/null
+++ b/target/linux/ipq807x/patches-5.15/0080-v6.3-arm64-dts-qcom-ipq8074-set-Gen2-PCIe-pcie-max-link-s.patch
@@ -0,0 +1,24 @@
+From a4748d2850783d36f77ccf2b5fcc86ccf1800ef1 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Wed, 16 Nov 2022 22:48:36 +0100
+Subject: [PATCH] arm64: dts: qcom: ipq8074: set Gen2 PCIe pcie max-link-speed
+
+Add the generic 'max-link-speed' property to describe the Gen2 PCIe link
+generation limit.
+This allows the generic DWC code to configure the link speed correctly.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -766,6 +766,7 @@
+                       linux,pci-domain = <1>;
+                       bus-range = <0x00 0xff>;
+                       num-lanes = <1>;
++                      max-link-speed = <2>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+ 

diff --git a/target/linux/ipq807x/patches-5.15/0081-v6.3-PCI-qcom-Add-support-for-IPQ8074-Gen3-port.patch b/target/linux/ipq807x/patches-5.15/0081-v6.3-PCI-qcom-Add-support-for-IPQ8074-Gen3-port.patch
new file mode 100644 (file)
index 0000000..c7a7e7a
--- /dev/null
+++ b/target/linux/ipq807x/patches-5.15/0081-v6.3-PCI-qcom-Add-support-for-IPQ8074-Gen3-port.patch
@@ -0,0 +1,23 @@
+From 76893579a74e7e5c79f0c717d95d13f4cbbb5f4d Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Sat, 24 Dec 2022 17:11:16 +0100
+Subject: [PATCH] PCI: qcom: Add support for IPQ8074 Gen3 port
+
+IPQ8074 has one Gen2 and one Gen3 port, with Gen2 port already supported.
+Add compatible for Gen3 port which uses the same controller as IPQ6018.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ drivers/pci/controller/dwc/pcie-qcom.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/pci/controller/dwc/pcie-qcom.c
++++ b/drivers/pci/controller/dwc/pcie-qcom.c
+@@ -1733,6 +1733,7 @@ static const struct of_device_id qcom_pc
+       { .compatible = "qcom,pcie-apq8064", .data = &ipq8064_cfg },
+       { .compatible = "qcom,pcie-msm8996", .data = &msm8996_cfg },
+       { .compatible = "qcom,pcie-ipq8074", .data = &ipq8074_cfg },
++      { .compatible = "qcom,pcie-ipq8074-gen3", .data = &ipq6018_cfg },
+       { .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg },
+       { .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg },
+       { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg },

diff --git a/target/linux/ipq807x/patches-5.15/0082-v6.3-clk-qcom-ipq8074-populate-fw_name-for-usb3phy-s.patch b/target/linux/ipq807x/patches-5.15/0082-v6.3-clk-qcom-ipq8074-populate-fw_name-for-usb3phy-s.patch
new file mode 100644 (file)
index 0000000..eb772be
--- /dev/null
+++ b/target/linux/ipq807x/patches-5.15/0082-v6.3-clk-qcom-ipq8074-populate-fw_name-for-usb3phy-s.patch
@@ -0,0 +1,38 @@
+From 614d31c231c7707322b643f409eeb7e28adc7f8c Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Sun, 8 Jan 2023 13:36:28 +0100
+Subject: [PATCH] clk: qcom: ipq8074: populate fw_name for usb3phy-s
+
+Having only .name populated in parent_data for clocks which are only
+globally searchable currently will not work as the clk core won't copy
+that name if there is no .fw_name present as well.
+
+So, populate .fw_name for usb3phy clocks in parent_data as they were
+missed by me in ("clk: qcom: ipq8074: populate fw_name for all parents").
+
+Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data")
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ drivers/clk/qcom/gcc-ipq8074.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/clk/qcom/gcc-ipq8074.c
++++ b/drivers/clk/qcom/gcc-ipq8074.c
+@@ -934,7 +934,7 @@ static struct clk_rcg2 usb0_mock_utmi_cl
+ };
+ 
+ static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
+-      { .name = "usb3phy_0_cc_pipe_clk" },
++      { .fw_name = "usb3phy_0_cc_pipe_clk", .name = "usb3phy_0_cc_pipe_clk" },
+       { .fw_name = "xo", .name = "xo" },
+ };
+ 
+@@ -1002,7 +1002,7 @@ static struct clk_rcg2 usb1_mock_utmi_cl
+ };
+ 
+ static const struct clk_parent_data gcc_usb3phy_1_cc_pipe_clk_xo[] = {
+-      { .name = "usb3phy_1_cc_pipe_clk" },
++      { .fw_name = "usb3phy_1_cc_pipe_clk", .name = "usb3phy_1_cc_pipe_clk" },
+       { .fw_name = "xo", .name = "xo" },
+ };
+ 

diff --git a/target/linux/ipq807x/patches-5.15/0106-arm64-dts-qcom-ipq8074-set-Gen2-PCIe-pcie-max-link-s.patch b/target/linux/ipq807x/patches-5.15/0106-arm64-dts-qcom-ipq8074-set-Gen2-PCIe-pcie-max-link-s.patch
deleted file mode 100644 (file)
index 0fa3839..0000000
--- a/target/linux/ipq807x/patches-5.15/0106-arm64-dts-qcom-ipq8074-set-Gen2-PCIe-pcie-max-link-s.patch
+++ /dev/null
@@ -1,24 +0,0 @@
-From a4748d2850783d36f77ccf2b5fcc86ccf1800ef1 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Wed, 16 Nov 2022 22:48:36 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq8074: set Gen2 PCIe pcie max-link-speed
-
-Add the generic 'max-link-speed' property to describe the Gen2 PCIe link
-generation limit.
-This allows the generic DWC code to configure the link speed correctly.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -801,6 +801,7 @@
-                       linux,pci-domain = <1>;
-                       bus-range = <0x00 0xff>;
-                       num-lanes = <1>;
-+                      max-link-speed = <2>;
-                       #address-cells = <3>;
-                       #size-cells = <2>;
- 

diff --git a/target/linux/ipq807x/patches-5.15/0107-PCI-qcom-Add-support-for-IPQ8074-Gen3-port.patch b/target/linux/ipq807x/patches-5.15/0107-PCI-qcom-Add-support-for-IPQ8074-Gen3-port.patch
deleted file mode 100644 (file)
index c7a7e7a..0000000
--- a/target/linux/ipq807x/patches-5.15/0107-PCI-qcom-Add-support-for-IPQ8074-Gen3-port.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-From 76893579a74e7e5c79f0c717d95d13f4cbbb5f4d Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sat, 24 Dec 2022 17:11:16 +0100
-Subject: [PATCH] PCI: qcom: Add support for IPQ8074 Gen3 port
-
-IPQ8074 has one Gen2 and one Gen3 port, with Gen2 port already supported.
-Add compatible for Gen3 port which uses the same controller as IPQ6018.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- drivers/pci/controller/dwc/pcie-qcom.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/pci/controller/dwc/pcie-qcom.c
-+++ b/drivers/pci/controller/dwc/pcie-qcom.c
-@@ -1733,6 +1733,7 @@ static const struct of_device_id qcom_pc
-       { .compatible = "qcom,pcie-apq8064", .data = &ipq8064_cfg },
-       { .compatible = "qcom,pcie-msm8996", .data = &msm8996_cfg },
-       { .compatible = "qcom,pcie-ipq8074", .data = &ipq8074_cfg },
-+      { .compatible = "qcom,pcie-ipq8074-gen3", .data = &ipq6018_cfg },
-       { .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg },
-       { .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg },
-       { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg },

diff --git a/target/linux/ipq807x/patches-5.15/0131-clk-qcom-ipq8074-populate-fw_name-for-usb3phy-s.patch b/target/linux/ipq807x/patches-5.15/0131-clk-qcom-ipq8074-populate-fw_name-for-usb3phy-s.patch
deleted file mode 100644 (file)
index eb772be..0000000
--- a/target/linux/ipq807x/patches-5.15/0131-clk-qcom-ipq8074-populate-fw_name-for-usb3phy-s.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 614d31c231c7707322b643f409eeb7e28adc7f8c Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sun, 8 Jan 2023 13:36:28 +0100
-Subject: [PATCH] clk: qcom: ipq8074: populate fw_name for usb3phy-s
-
-Having only .name populated in parent_data for clocks which are only
-globally searchable currently will not work as the clk core won't copy
-that name if there is no .fw_name present as well.
-
-So, populate .fw_name for usb3phy clocks in parent_data as they were
-missed by me in ("clk: qcom: ipq8074: populate fw_name for all parents").
-
-Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data")
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- drivers/clk/qcom/gcc-ipq8074.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq8074.c
-+++ b/drivers/clk/qcom/gcc-ipq8074.c
-@@ -934,7 +934,7 @@ static struct clk_rcg2 usb0_mock_utmi_cl
- };
- 
- static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
--      { .name = "usb3phy_0_cc_pipe_clk" },
-+      { .fw_name = "usb3phy_0_cc_pipe_clk", .name = "usb3phy_0_cc_pipe_clk" },
-       { .fw_name = "xo", .name = "xo" },
- };
- 
-@@ -1002,7 +1002,7 @@ static struct clk_rcg2 usb1_mock_utmi_cl
- };
- 
- static const struct clk_parent_data gcc_usb3phy_1_cc_pipe_clk_xo[] = {
--      { .name = "usb3phy_1_cc_pipe_clk" },
-+      { .fw_name = "usb3phy_1_cc_pipe_clk", .name = "usb3phy_1_cc_pipe_clk" },
-       { .fw_name = "xo", .name = "xo" },
- };
-