coh_limit - coh_start, \
MT_DEVICE | MT_RW | MT_SECURE); \
mmap_add(plat_rk_mmap); \
- rockchip_plat_sram_mmu_el##_el(); \
+ rockchip_plat_mmu_el##_el(); \
init_xlat_tables(); \
\
enable_mmu_el ## _el(0); \
bl32_ep_info = *from_bl2->bl32_ep_info;
bl33_ep_info = *from_bl2->bl33_ep_info;
- plat_rockchip_pmusram_prepare();
-
/* there may have some board sepcific message need to initialize */
params_early_setup(plat_params_from_bl2);
}
#define __sramdata __attribute__((section(".sram.data")))
#define __sramconst __attribute__((section(".sram.rodata")))
-#define __sramfunc __attribute__((section(".sram.text"))) \
- __attribute__((noinline))
+#define __sramfunc __attribute__((section(".sram.text")))
+
+#define __pmusramdata __attribute__((section(".pmusram.data")))
+#define __pmusramconst __attribute__((section(".pmusram.rodata")))
+#define __pmusramfunc __attribute__((section(".pmusram.text")))
extern uint32_t __bl31_sram_text_start, __bl31_sram_text_end;
extern uint32_t __bl31_sram_data_start, __bl31_sram_data_end;
+extern uint32_t __bl31_sram_stack_start, __bl31_sram_stack_end;
extern uint32_t __sram_incbin_start, __sram_incbin_end;
void plat_rockchip_gic_cpuif_disable(void);
void plat_rockchip_gic_pcpu_init(void);
-void plat_rockchip_pmusram_prepare(void);
void plat_rockchip_pmu_init(void);
void plat_rockchip_soc_init(void);
uintptr_t plat_get_sec_entrypoint(void);
extern const unsigned char rockchip_power_domain_tree_desc[];
-extern void *pmu_cpuson_entrypoint_start;
-extern void *pmu_cpuson_entrypoint_end;
+extern void *pmu_cpuson_entrypoint;
extern uint64_t cpuson_entry_point[PLATFORM_CORE_COUNT];
extern uint32_t cpuson_flags[PLATFORM_CORE_COUNT];
extern const mmap_region_t plat_rk_mmap[];
-void rockchip_plat_sram_mmu_el3(void);
-void plat_rockchip_mem_prepare(void);
+void rockchip_plat_mmu_el3(void);
#endif /* __ASSEMBLY__ */
+++ /dev/null
-/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <console.h>
-#include <debug.h>
-#include <platform.h>
-#include <plat_private.h>
-
-/*****************************************************************************
- * sram only surpport 32-bits access
- ******************************************************************************/
-void u32_align_cpy(uint32_t *dst, const uint32_t *src, size_t bytes)
-{
- uint32_t i;
-
- for (i = 0; i < bytes; i++)
- dst[i] = src[i];
-}
-
-void rockchip_plat_sram_mmu_el3(void)
-{
-#ifdef PLAT_EXTRA_LD_SCRIPT
- size_t sram_size;
-
- /* sram.text size */
- sram_size = (char *)&__bl31_sram_text_end -
- (char *)&__bl31_sram_text_start;
- mmap_add_region((unsigned long)&__bl31_sram_text_start,
- (unsigned long)&__bl31_sram_text_start,
- sram_size, MT_MEMORY | MT_RO | MT_SECURE);
-
- /* sram.data size */
- sram_size = (char *)&__bl31_sram_data_end -
- (char *)&__bl31_sram_data_start;
- mmap_add_region((unsigned long)&__bl31_sram_data_start,
- (unsigned long)&__bl31_sram_data_start,
- sram_size, MT_MEMORY | MT_RW | MT_SECURE);
-
- /* sram.incbin size */
- sram_size = (char *)&__sram_incbin_end - (char *)&__sram_incbin_start;
- mmap_add_region((unsigned long)&__sram_incbin_start,
- (unsigned long)&__sram_incbin_start,
- sram_size, MT_NON_CACHEABLE | MT_RW | MT_SECURE);
-#else
- /* TODO: Support other SoCs, Just support RK3399 now */
- return;
-#endif
-}
-
-void plat_rockchip_mem_prepare(void)
-{
- /* The code for resuming cpu from suspend must be excuted in pmusram */
- plat_rockchip_pmusram_prepare();
-}
+++ /dev/null
-/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __PMU_SRAM_H__
-#define __PMU_SRAM_H__
-
-/*****************************************************************************
- * define data offset in struct psram_data
- *****************************************************************************/
-#define PSRAM_DT_SP 0x0
-#define PSRAM_DT_DDR_FUNC 0x8
-#define PSRAM_DT_DDR_DATA 0x10
-#define PSRAM_DT_DDRFLAG 0x18
-#define PSRAM_DT_MPIDR 0x1c
-#define PSRAM_DT_END 0x20
-/******************************************************************************
- * Allocate data region for struct psram_data_t in pmusram
- ******************************************************************************/
-/* Needed aligned 16 bytes for sp stack top */
-#define PSRAM_DT_SIZE (((PSRAM_DT_END + 16) / 16) * 16)
-#define PSRAM_DT_BASE ((PMUSRAM_BASE + PMUSRAM_RSIZE) - PSRAM_DT_SIZE)
-#define PSRAM_SP_TOP PSRAM_DT_BASE
-
-#ifndef __ASSEMBLY__
-
-struct psram_data_t {
- uint64_t sp;
- uint64_t ddr_func;
- uint64_t ddr_data;
- uint32_t ddr_flag;
- uint32_t boot_mpidr;
-};
-
-CASSERT(sizeof(struct psram_data_t) <= PSRAM_DT_SIZE,
- assert_psram_dt_size_mismatch);
-CASSERT(__builtin_offsetof(struct psram_data_t, sp) == PSRAM_DT_SP,
- assert_psram_dt_sp_offset_mistmatch);
-CASSERT(__builtin_offsetof(struct psram_data_t, ddr_func) == PSRAM_DT_DDR_FUNC,
- assert_psram_dt_ddr_func_offset_mistmatch);
-CASSERT(__builtin_offsetof(struct psram_data_t, ddr_data) == PSRAM_DT_DDR_DATA,
- assert_psram_dt_ddr_data_offset_mistmatch);
-CASSERT(__builtin_offsetof(struct psram_data_t, ddr_flag) == PSRAM_DT_DDRFLAG,
- assert_psram_dt_ddr_flag_offset_mistmatch);
-CASSERT(__builtin_offsetof(struct psram_data_t, boot_mpidr) == PSRAM_DT_MPIDR,
- assert_psram_dt_mpidr_offset_mistmatch);
-void u32_align_cpy(uint32_t *dst, const uint32_t *src, size_t bytes);
-
-#endif /* __ASSEMBLY__ */
-
-#endif
#include <arch.h>
#include <asm_macros.S>
#include <platform_def.h>
-#include <pmu_sram.h>
- .globl pmu_cpuson_entrypoint_start
- .globl pmu_cpuson_entrypoint_end
+ .globl pmu_cpuson_entrypoint
+ .macro pmusram_entry_func _name
+ .section .pmusram.entry, "ax"
+ .type \_name, %function
+ .func \_name
+ .cfi_startproc
+ \_name:
+ .endm
-func pmu_cpuson_entrypoint
-pmu_cpuson_entrypoint_start:
- ldr x5, psram_data
-check_wake_cpus:
- mrs x0, MPIDR_EL1
- and x1, x0, #MPIDR_CPU_MASK
- and x0, x0, #MPIDR_CLUSTER_MASK
- orr x0, x0, x1
- /* primary_cpu */
- ldr w1, [x5, #PSRAM_DT_MPIDR]
- cmp w0, w1
- b.eq sys_wakeup
- /*
- * If the core is not the primary cpu,
- * force the core into wfe.
- */
-wfe_loop:
- wfe
- b wfe_loop
-sys_wakeup:
- /* check ddr flag for resume ddr */
- ldr w2, [x5, #PSRAM_DT_DDRFLAG]
- cmp w2, #0x0
- b.eq sys_resume
+pmusram_entry_func pmu_cpuson_entrypoint
+
+#if PSRAM_DO_DDR_RESUME
ddr_resume:
- ldr x2, [x5, #PSRAM_DT_SP]
- mov sp, x2
- ldr x1, [x5, #PSRAM_DT_DDR_FUNC]
- ldr x0, [x5, #PSRAM_DT_DDR_DATA]
- blr x1
-sys_resume:
- ldr x1, sys_wakeup_entry
- br x1
+ ldr x2, =__bl31_sram_stack_end
+ mov sp, x2
+ bl dmc_restore
+#endif
- .align 3
-psram_data:
- .quad PSRAM_DT_BASE
-sys_wakeup_entry:
- .quad psci_entrypoint
-pmu_cpuson_entrypoint_end:
- .word 0
+sys_resume:
+ bl psci_entrypoint
endfunc pmu_cpuson_entrypoint
#include <platform.h>
#include <platform_def.h>
#include <plat_private.h>
-#include <pmu_sram.h>
#include <pmu.h>
#include <rk3328_def.h>
#include <pmu_com.h>
DEFINE_BAKERY_LOCK(rockchip_pd_lock);
-static struct psram_data_t *psram_sleep_cfg =
- (struct psram_data_t *)PSRAM_DT_BASE;
-
static struct rk3328_sleep_ddr_data ddr_data;
static __sramdata struct rk3328_sleep_sram_data sram_data;
#pragma weak rk3328_pmic_suspend
#pragma weak rk3328_pmic_resume
-void plat_rockchip_pmusram_prepare(void)
-{
- uint32_t *sram_dst, *sram_src;
- size_t sram_size = 2;
- /*
- * pmu sram code and data prepare
- */
- sram_dst = (uint32_t *)PMUSRAM_BASE;
- sram_src = (uint32_t *)&pmu_cpuson_entrypoint_start;
- sram_size = (uint32_t *)&pmu_cpuson_entrypoint_end -
- (uint32_t *)sram_src;
- u32_align_cpy(sram_dst, sram_src, sram_size);
-
- psram_sleep_cfg->sp = PSRAM_DT_BASE;
-}
-
static inline uint32_t get_cpus_pwr_domain_cfg_info(uint32_t cpu_id)
{
uint32_t pd_reg, apm_reg;
}
}
+void sram_save(void)
+{
+ /* TODO: support the sdram save for rk3328 SoCs*/
+}
+
+void sram_restore(void)
+{
+ /* TODO: support the sdram restore for rk3328 SoCs */
+}
+
int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint)
{
uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr);
sram_udelay(100);
}
-static inline void rockchip_set_sram_sp(uint64_t set_sp)
-{
- __asm volatile("mov sp, %0\n"::"r" (set_sp) : "sp");
-}
-
static __sramfunc void ddr_suspend(void)
{
sram_data.pd_sr_idle_save = mmio_read_32(DDR_UPCTL_BASE +
dpll_suspend();
}
-static __sramfunc void ddr_resume(void)
+__sramfunc void dmc_restore(void)
{
dpll_resume();
mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(2), 0x00040004);
}
-static __sramfunc void sram_dbg_uart_resume(void)
+__sramfunc void sram_dbg_uart_resume(void)
{
/* restore uart clk and reset fifo */
mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(16), 0x20000000);
disable_mmu_icache_el3();
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1),
- (PMUSRAM_BASE >> CPU_BOOT_ADDR_ALIGN) |
+ ((uintptr_t)&pmu_cpuson_entrypoint >> CPU_BOOT_ADDR_ALIGN) |
CPU_BOOT_ADDR_WMASK);
/* ddr self-refresh and gating phy */
sram_soc_enter_lp();
}
-static __sramfunc void sys_resume_first(void)
-{
- sram_dbg_uart_resume();
-
- rk3328_pmic_resume();
-
- /* ddr self-refresh exit */
- ddr_resume();
-
- /* disable apm cfg */
- mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(0), CORES_PM_DISABLE);
-
- /* the warm booting address of cpus */
- mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1),
- (cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) |
- CPU_BOOT_ADDR_WMASK);
-}
-
void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void)
{
- rockchip_set_sram_sp(PSRAM_DT_BASE);
-
sram_suspend();
/* should never reach here */
return 0;
}
+void rockchip_plat_mmu_el3(void)
+{
+ /* TODO: support the el3 for rk3328 SoCs */
+}
+
void plat_rockchip_pmu_init(void)
{
uint32_t cpu;
cpuson_flags[cpu] = 0;
cpu_warm_boot_addr = (uint64_t)platform_cpu_warmboot;
- psram_sleep_cfg->ddr_func = (uint64_t)sys_resume_first;
- psram_sleep_cfg->ddr_data = 0x00;
- psram_sleep_cfg->ddr_flag = 0x01;
- psram_sleep_cfg->boot_mpidr = read_mpidr_el1() & 0xffff;
/* the warm booting address of cpus */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1),
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#define __ROCKCHIP_PLAT_LD_S__
MEMORY {
- SRAM (rwx): ORIGIN = SRAM_LDS_BASE, LENGTH = SRAM_LDS_SIZE
+ PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE
}
SECTIONS
{
- . = SRAM_LDS_BASE;
- ASSERT(. == ALIGN(4096),
- "SRAM_BASE address is not aligned on a page boundary.")
+ . = PMUSRAM_BASE;
/*
- * The SRAM space allocation for RK3328
- * ----------------
- * | sram text
- * ----------------
- * | sram data
- * ----------------
+ * pmu_cpuson_entrypoint request address
+ * align 64K when resume, so put it in the
+ * start of pmusram
*/
- .text_sram : ALIGN(4096) {
- __bl31_sram_text_start = .;
- *(.sram.text)
- *(.sram.rodata)
- . = ALIGN(4096);
- __bl31_sram_text_end = .;
- } >SRAM
+ .text_pmusram : {
+ ASSERT(. == ALIGN(64 * 1024),
+ ".pmusram.entry request 64K aligned.");
+ *(.pmusram.entry)
+ __bl31_pmusram_text_start = .;
+ *(.pmusram.text)
+ *(.pmusram.rodata)
+ __bl31_pmusram_text_end = .;
+ __bl31_pmusram_data_start = .;
+ *(.pmusram.data)
+ __bl31_pmusram_data_end = .;
- .data_sram : ALIGN(4096) {
- __bl31_sram_data_start = .;
- *(.sram.data)
- . = ALIGN(4096);
- __bl31_sram_data_end = .;
- } >SRAM
- __sram_incbin_start = .;
- __sram_incbin_end = .;
+ } >PMUSRAM
}
#endif /* __ROCKCHIP_PLAT_LD_S__ */
#define PLAT_RK_PRIMARY_CPU 0x0
+#define PSRAM_DO_DDR_RESUME 0
+
#endif /* __PLATFORM_DEF_H__ */
${RK_PLAT_COMMON}/drivers/parameter/ddr_parameter.c \
${RK_PLAT_COMMON}/aarch64/plat_helpers.S \
${RK_PLAT_COMMON}/bl31_plat_setup.c \
- ${RK_PLAT_COMMON}/pmusram/pmu_sram.c \
${RK_PLAT_COMMON}/pmusram/pmu_sram_cpus_on.S \
${RK_PLAT_COMMON}/plat_pm.c \
${RK_PLAT_COMMON}/plat_topology.c \
#include <platform_def.h>
#include <plat_private.h>
#include <rk3368_def.h>
-#include <pmu_sram.h>
#include <soc.h>
#include <pmu.h>
#include <ddr_rk3368.h>
DEFINE_BAKERY_LOCK(rockchip_pd_lock);
-static struct psram_data_t *psram_sleep_cfg =
- (struct psram_data_t *)PSRAM_DT_BASE;
-
static uint32_t cpu_warm_boot_addr;
void rk3368_flash_l2_b(void)
dsb();
}
-static void ddr_suspend_save(void)
-{
- ddr_reg_save(1, psram_sleep_cfg->ddr_data);
-}
-
static void pmu_set_sleep_mode(void)
{
- ddr_suspend_save();
pmu_sleep_mode_config();
soc_sleep_config();
regs_updata_bit_set(PMU_BASE + PMU_PWRMD_CORE, pmu_mdcr_global_int_dis);
regs_updata_bit_set(PMU_BASE + PMU_SFT_CON, pmu_sft_glbl_int_dis_b);
pmu_scu_b_pwrdn();
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1),
- (PMUSRAM_BASE >> CPU_BOOT_ADDR_ALIGN) |
- CPU_BOOT_ADDR_WMASK);
+ ((uintptr_t)&pmu_cpuson_entrypoint >>
+ CPU_BOOT_ADDR_ALIGN) | CPU_BOOT_ADDR_WMASK);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(2),
- (PMUSRAM_BASE >> CPU_BOOT_ADDR_ALIGN) |
- CPU_BOOT_ADDR_WMASK);
-}
-
-void plat_rockchip_pmusram_prepare(void)
-{
- uint32_t *sram_dst, *sram_src;
- size_t sram_size = 2;
- uint32_t code_size;
-
- /* pmu sram code and data prepare */
- sram_dst = (uint32_t *)PMUSRAM_BASE;
- sram_src = (uint32_t *)&pmu_cpuson_entrypoint_start;
- sram_size = (uint32_t *)&pmu_cpuson_entrypoint_end -
- (uint32_t *)sram_src;
- u32_align_cpy(sram_dst, sram_src, sram_size);
-
- /* ddr code */
- sram_dst += sram_size;
- sram_src = ddr_get_resume_code_base();
- code_size = ddr_get_resume_code_size();
- u32_align_cpy(sram_dst, sram_src, code_size / 4);
- psram_sleep_cfg->ddr_func = (uint64_t)sram_dst;
-
- /* ddr data */
- sram_dst += (code_size / 4);
- psram_sleep_cfg->ddr_data = (uint64_t)sram_dst;
-
- assert((uint64_t)(sram_dst + ddr_get_resume_data_size() / 4)
- < PSRAM_SP_BOTTOM);
- psram_sleep_cfg->sp = PSRAM_SP_TOP;
+ ((uintptr_t)&pmu_cpuson_entrypoint >>
+ CPU_BOOT_ADDR_ALIGN) | CPU_BOOT_ADDR_WMASK);
}
static int cpus_id_power_domain(uint32_t cluster,
nonboot_cpus_off();
pmu_set_sleep_mode();
- psram_sleep_cfg->ddr_flag = 0;
-
return 0;
}
+void rockchip_plat_mmu_el3(void)
+{
+ /* TODO: support the el3 for rk3368 SoCs */
+}
+
void plat_rockchip_pmu_init(void)
{
uint32_t cpu;
for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++)
cpuson_flags[cpu] = 0;
- psram_sleep_cfg->boot_mpidr = read_mpidr_el1() & 0xffff;
-
nonboot_cpus_off();
INFO("%s(%d): pd status %x\n", __func__, __LINE__,
mmio_read_32(PMU_BASE + PMU_PWRDN_ST));
--- /dev/null
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef __ROCKCHIP_PLAT_LD_S__
+#define __ROCKCHIP_PLAT_LD_S__
+
+MEMORY {
+ PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE
+}
+
+SECTIONS
+{
+ . = PMUSRAM_BASE;
+
+ /*
+ * pmu_cpuson_entrypoint request address
+ * align 64K when resume, so put it in the
+ * start of pmusram
+ */
+ .text_pmusram : {
+ ASSERT(. == ALIGN(64 * 1024),
+ ".pmusram.entry request 64K aligned.");
+ *(.pmusram.entry)
+ __bl31_pmusram_text_start = .;
+ *(.pmusram.text)
+ *(.pmusram.rodata)
+ __bl31_pmusram_text_end = .;
+ __bl31_pmusram_data_start = .;
+ *(.pmusram.data)
+ __bl31_pmusram_data_end = .;
+
+ } >PMUSRAM
+}
+
+#endif /* __ROCKCHIP_PLAT_LD_S__ */
#define PLAT_RK_PRIMARY_CPU 0x0
+#define PSRAM_DO_DDR_RESUME 0
+
#endif /* __PLATFORM_DEF_H__ */
${RK_PLAT_COMMON}/bl31_plat_setup.c \
${RK_PLAT_COMMON}/params_setup.c \
${RK_PLAT_COMMON}/pmusram/pmu_sram_cpus_on.S \
- ${RK_PLAT_COMMON}/pmusram/pmu_sram.c \
${RK_PLAT_COMMON}/plat_pm.c \
${RK_PLAT_COMMON}/plat_topology.c \
${RK_PLAT_COMMON}/aarch64/platform_common.c \
${RK_PLAT_SOC}/drivers/ddr/ddr_rk3368.c \
ENABLE_PLAT_COMPAT := 0
+
+$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
#include <plat_params.h>
#include <plat_private.h>
#include <rk3399_def.h>
-#include <pmu_sram.h>
#include <secure.h>
#include <soc.h>
#include <pmu.h>
DEFINE_BAKERY_LOCK(rockchip_pd_lock);
-static struct psram_data_t *psram_sleep_cfg =
- (struct psram_data_t *)PSRAM_DT_BASE;
-
static uint32_t cpu_warm_boot_addr;
/*
mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(ACINACTM_CLUSTER_B_CFG));
}
-void plat_rockchip_pmusram_prepare(void)
-{
- uint32_t *sram_dst, *sram_src;
- size_t sram_size;
-
- /*
- * pmu sram code and data prepare
- */
- sram_dst = (uint32_t *)PMUSRAM_BASE;
- sram_src = (uint32_t *)&pmu_cpuson_entrypoint_start;
- sram_size = (uint32_t *)&pmu_cpuson_entrypoint_end -
- (uint32_t *)sram_src;
-
- u32_align_cpy(sram_dst, sram_src, sram_size);
-
- psram_sleep_cfg->sp = PSRAM_DT_BASE;
-}
-
static inline uint32_t get_cpus_pwr_domain_cfg_info(uint32_t cpu_id)
{
assert(cpu_id < PLATFORM_CORE_COUNT);
pmu_sgrf_rst_hld();
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1),
- (PMUSRAM_BASE >> CPU_BOOT_ADDR_ALIGN) |
- CPU_BOOT_ADDR_WMASK);
+ ((uintptr_t)&pmu_cpuson_entrypoint >>
+ CPU_BOOT_ADDR_ALIGN) | CPU_BOOT_ADDR_WMASK);
mmio_write_32(PMU_BASE + PMU_ADB400_CON,
BIT_WITH_WMSK(PMU_PWRDWN_REQ_CORE_B_2GIC_SW) |
;
}
+void rockchip_plat_mmu_el3(void)
+{
+ size_t sram_size;
+
+ /* sram.text size */
+ sram_size = (char *)&__bl31_sram_text_end -
+ (char *)&__bl31_sram_text_start;
+ mmap_add_region((unsigned long)&__bl31_sram_text_start,
+ (unsigned long)&__bl31_sram_text_start,
+ sram_size, MT_MEMORY | MT_RO | MT_SECURE);
+
+ /* sram.data size */
+ sram_size = (char *)&__bl31_sram_data_end -
+ (char *)&__bl31_sram_data_start;
+ mmap_add_region((unsigned long)&__bl31_sram_data_start,
+ (unsigned long)&__bl31_sram_data_start,
+ sram_size, MT_MEMORY | MT_RW | MT_SECURE);
+
+ sram_size = (char *)&__bl31_sram_stack_end -
+ (char *)&__bl31_sram_stack_start;
+ mmap_add_region((unsigned long)&__bl31_sram_stack_start,
+ (unsigned long)&__bl31_sram_stack_start,
+ sram_size, MT_MEMORY | MT_RW | MT_SECURE);
+
+ sram_size = (char *)&__sram_incbin_end - (char *)&__sram_incbin_start;
+ mmap_add_region((unsigned long)&__sram_incbin_start,
+ (unsigned long)&__sram_incbin_start,
+ sram_size, MT_NON_CACHEABLE | MT_RW | MT_SECURE);
+}
+
void plat_rockchip_pmu_init(void)
{
uint32_t cpu;
for (cpu = 0; cpu < PLATFORM_CLUSTER_COUNT; cpu++)
clst_warmboot_data[cpu] = 0;
- psram_sleep_cfg->ddr_func = (uint64_t)dmc_restore;
- psram_sleep_cfg->ddr_data = (uint64_t)&sdram_config;
- psram_sleep_cfg->ddr_flag = 0x01;
-
- psram_sleep_cfg->boot_mpidr = read_mpidr_el1() & 0xffff;
-
/* config cpu's warm boot address */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1),
(cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) |
MEMORY {
SRAM (rwx): ORIGIN = SRAM_BASE, LENGTH = SRAM_SIZE
+ PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE
}
SECTIONS
. = ALIGN(4096);
__bl31_sram_data_end = .;
} >SRAM
+
+ .stack_sram : ALIGN(4096) {
+ __bl31_sram_stack_start = .;
+ . += 4096;
+ __bl31_sram_stack_end = .;
+ } >SRAM
+
+ . = PMUSRAM_BASE;
+
+ /*
+ * pmu_cpuson_entrypoint request address
+ * align 64K when resume, so put it in the
+ * start of pmusram
+ */
+ .pmusram : {
+ ASSERT(. == ALIGN(64 * 1024),
+ ".pmusram.entry request 64K aligned.");
+ *(.pmusram.entry)
+ __bl31_pmusram_text_start = .;
+ *(.pmusram.text)
+ *(.pmusram.rodata)
+ __bl31_pmusram_text_end = .;
+ __bl31_pmusram_data_start = .;
+ *(.pmusram.data)
+ __bl31_pmusram_data_end = .;
+
+ } >PMUSRAM
}
#endif /* __ROCKCHIP_PLAT_LD_S__ */
#define PLAT_RK_PRIMARY_CPU 0x0
+#define PSRAM_DO_DDR_RESUME 1
#endif /* __PLATFORM_DEF_H__ */
${RK_PLAT_COMMON}/bl31_plat_setup.c \
${RK_PLAT_COMMON}/params_setup.c \
${RK_PLAT_COMMON}/pmusram/pmu_sram_cpus_on.S \
- ${RK_PLAT_COMMON}/pmusram/pmu_sram.c \
${RK_PLAT_COMMON}/plat_pm.c \
${RK_PLAT_COMMON}/plat_topology.c \
${RK_PLAT_COMMON}/aarch64/platform_common.c \
projects / project / bcm63xx / atf.git / commitdiff