drm/i915: Removed the read of RP_STATE_CAP from sysfs/debugfs functions

The frequency values(Rp0, Rp1, Rpn) reported by RP_STATE_CAP register
are stored, initially by the Driver, inside the dev_priv->rps structure.
Since these values are expected to remain same throughout, there is no real
need to read this register, on dynamic basis, from certain debugfs/sysfs
functions and the values can be instead retrieved from the dev_priv->rps
structure when needed.
For the i915_frequency_info debugfs interface, the frequency values from the
RP_STATE_CAP register only should be used, to indicate the actual Hw state,
since it is principally used for the debugging purpose.

v2: Reverted the changes in i915_frequency_info function, to continue report
    back the frequency values, as per the actual Hw state (Chris)

Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 843b471090f33f19f64e4c85489270b6f6f370ec..81e27d4171307b31ae746778b078dacb46f49cf8 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4180,7 +4180,7 @@ i915_max_freq_set(void *data, u64 val)
 {
        struct drm_device *dev = data;
        struct drm_i915_private *dev_priv = dev->dev_private;
-       u32 rp_state_cap, hw_max, hw_min;
+       u32 hw_max, hw_min;
        int ret;
 
        if (INTEL_INFO(dev)->gen < 6)
@@ -4197,18 +4197,10 @@ i915_max_freq_set(void *data, u64 val)
        /*
         * Turbo will still be enabled, but won't go above the set value.
         */
-       if (IS_VALLEYVIEW(dev)) {
-               val = intel_freq_opcode(dev_priv, val);
+       val = intel_freq_opcode(dev_priv, val);
 
-               hw_max = dev_priv->rps.max_freq;
-               hw_min = dev_priv->rps.min_freq;
-       } else {
-               val = intel_freq_opcode(dev_priv, val);
-
-               rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
-               hw_max = dev_priv->rps.max_freq;
-               hw_min = (rp_state_cap >> 16) & 0xff;
-       }
+       hw_max = dev_priv->rps.max_freq;
+       hw_min = dev_priv->rps.min_freq;
 
        if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
                mutex_unlock(&dev_priv->rps.hw_lock);
@@ -4255,7 +4247,7 @@ i915_min_freq_set(void *data, u64 val)
 {
        struct drm_device *dev = data;
        struct drm_i915_private *dev_priv = dev->dev_private;
-       u32 rp_state_cap, hw_max, hw_min;
+       u32 hw_max, hw_min;
        int ret;
 
        if (INTEL_INFO(dev)->gen < 6)
@@ -4272,18 +4264,10 @@ i915_min_freq_set(void *data, u64 val)
        /*
         * Turbo will still be enabled, but won't go below the set value.
         */
-       if (IS_VALLEYVIEW(dev)) {
-               val = intel_freq_opcode(dev_priv, val);
+       val = intel_freq_opcode(dev_priv, val);
 
-               hw_max = dev_priv->rps.max_freq;
-               hw_min = dev_priv->rps.min_freq;
-       } else {
-               val = intel_freq_opcode(dev_priv, val);
-
-               rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
-               hw_max = dev_priv->rps.max_freq;
-               hw_min = (rp_state_cap >> 16) & 0xff;
-       }
+       hw_max = dev_priv->rps.max_freq;
+       hw_min = dev_priv->rps.min_freq;
 
        if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
                mutex_unlock(&dev_priv->rps.hw_lock);

diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index cdc9da001484a8cd2bd5de2494318619019c2ff3..186ab95056b09cd1b86fd79dbeb5ded9de4d7771 100644 (file)
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -487,38 +487,17 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr
        struct drm_minor *minor = dev_to_drm_minor(kdev);
        struct drm_device *dev = minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
-       u32 val, rp_state_cap;
-       ssize_t ret;
-
-       ret = mutex_lock_interruptible(&dev->struct_mutex);
-       if (ret)
-               return ret;
-       intel_runtime_pm_get(dev_priv);
-       rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
-       intel_runtime_pm_put(dev_priv);
-       mutex_unlock(&dev->struct_mutex);
+       u32 val;
 
-       if (attr == &dev_attr_gt_RP0_freq_mhz) {
-               if (IS_VALLEYVIEW(dev))
-                       val = intel_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);
-               else
-                       val = intel_gpu_freq(dev_priv,
-                                            ((rp_state_cap & 0x0000ff) >> 0));
-       } else if (attr == &dev_attr_gt_RP1_freq_mhz) {
-               if (IS_VALLEYVIEW(dev))
-                       val = intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);
-               else
-                       val = intel_gpu_freq(dev_priv,
-                                            ((rp_state_cap & 0x00ff00) >> 8));
-       } else if (attr == &dev_attr_gt_RPn_freq_mhz) {
-               if (IS_VALLEYVIEW(dev))
-                       val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq);
-               else
-                       val = intel_gpu_freq(dev_priv,
-                                            ((rp_state_cap & 0xff0000) >> 16));
-       } else {
+       if (attr == &dev_attr_gt_RP0_freq_mhz)
+               val = intel_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);
+       else if (attr == &dev_attr_gt_RP1_freq_mhz)
+               val = intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);
+       else if (attr == &dev_attr_gt_RPn_freq_mhz)
+               val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq);
+       else
                BUG();
-       }
+
        return snprintf(buf, PAGE_SIZE, "%d\n", val);
 }