imx6: apply upstream mmc fix for DDR50 cards on UHS-I capable boards

https://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc.git/commit/?h=fixes&id=9f327845358d3dd0d8a5a7a5436b0aa5c432e757

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/target/linux/imx6/patches-4.9/0003-mmc-sdhci-esdhc-imx-increase-the-pad-I-O-drive-stren.patch b/target/linux/imx6/patches-4.9/0003-mmc-sdhci-esdhc-imx-increase-the-pad-I-O-drive-stren.patch
new file mode 100644 (file)
index 0000000..f97e829
--- /dev/null
+++ b/target/linux/imx6/patches-4.9/0003-mmc-sdhci-esdhc-imx-increase-the-pad-I-O-drive-stren.patch
@@ -0,0 +1,42 @@
+From 9f327845358d3dd0d8a5a7a5436b0aa5c432e757 Mon Sep 17 00:00:00 2001
+From: Haibo Chen <haibo.chen@nxp.com>
+Date: Wed, 19 Apr 2017 10:53:51 +0800
+Subject: [PATCH] mmc: sdhci-esdhc-imx: increase the pad I/O drive strength for
+ DDR50 card
+
+Currently for DDR50 card, it need tuning in default. We meet tuning fail
+issue for DDR50 card and some data CRC error when DDR50 sd card works.
+
+This is because the default pad I/O drive strength can't make sure DDR50
+card work stable. So increase the pad I/O drive strength for DDR50 card,
+and use pins_100mhz.
+
+This fixes DDR50 card support for IMX since DDR50 tuning was enabled from
+commit 9faac7b95ea4 ("mmc: sdhci: enable tuning for DDR50")
+
+Tested-and-reported-by: Tim Harvey <tharvey@gateworks.com>
+Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
+Cc: stable@vger.kernel.org # v4.4+
+Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
+Acked-by: Adrian Hunter <adrian.hunter@intel.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Tim Harvey <tharvey@gateworks.com>
+---
+ drivers/mmc/host/sdhci-esdhc-imx.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
+index 7123ef9..445fc47 100644
+--- a/drivers/mmc/host/sdhci-esdhc-imx.c
++++ b/drivers/mmc/host/sdhci-esdhc-imx.c
+@@ -830,6 +830,7 @@ static int esdhc_change_pinstate(struct sdhci_host *host,
+ 
+       switch (uhs) {
+       case MMC_TIMING_UHS_SDR50:
++      case MMC_TIMING_UHS_DDR50:
+               pinctrl = imx_data->pins_100mhz;
+               break;
+       case MMC_TIMING_UHS_SDR104:
+-- 
+2.7.4
+