ath79: ar724x: fix pll settings

Add the syscon compatible, otherwise used functions like
syscon_regmap_lookup_by_phandle() will return an error and setting the
ethernet pll data wont work at all.

Fix the pll register width. Writing to registers out of the range via
syscon isn't possible and returns an error. On ar7242 the last pll
register - Current Audio Modulation Logic Output - is at 0x1805003c.

Signed-off-by: Mathias Kresin <dev@kresin.me>

diff --git a/target/linux/ath79/dts/ar724x.dtsi b/target/linux/ath79/dts/ar724x.dtsi
index 41087451131d6f171a7aa081ae8f0da941c90f56..fe1b4eb681a307bba6ce0bc98dec44ef1245bd89 100644 (file)
--- a/target/linux/ath79/dts/ar724x.dtsi
+++ b/target/linux/ath79/dts/ar724x.dtsi
@@ -65,9 +65,8 @@
                        };
 
                        pll: pll-controller@18050000 {
-                               compatible = "qca,ar7240-pll",
-                                               "qca,ar7240-pll";
-                               reg = <0x18050000 0x20>;
+                               compatible = "qca,ar7240-pll", "syscon";
+                               reg = <0x18050000 0x3c>;
 
                                clock-names = "ref";
                                /* The board must provides the ref clock */