bcma: move define of BCMA_CLKCTLST register

Recent experiments have shown many cores share 0x1E0 register used for
clock management.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

diff --git a/include/linux/bcma/bcma_driver_chipcommon.h b/include/linux/bcma/bcma_driver_chipcommon.h
index 68c3d941a215b5def8cea95ff4a2367286600abb..a0f684615ae561a6c1cc241808512655533ee420 100644 (file)
--- a/include/linux/bcma/bcma_driver_chipcommon.h
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
@@ -179,15 +179,7 @@
 #define BCMA_CC_PROG_WAITCNT           0x0124
 #define BCMA_CC_FLASH_CFG              0x0128
 #define BCMA_CC_FLASH_WAITCNT          0x012C
-#define BCMA_CC_CLKCTLST               0x01E0 /* Clock control and status (rev >= 20) */
-#define  BCMA_CC_CLKCTLST_FORCEALP     0x00000001 /* Force ALP request */
-#define  BCMA_CC_CLKCTLST_FORCEHT      0x00000002 /* Force HT request */
-#define  BCMA_CC_CLKCTLST_FORCEILP     0x00000004 /* Force ILP request */
-#define  BCMA_CC_CLKCTLST_HAVEALPREQ   0x00000008 /* ALP available request */
-#define  BCMA_CC_CLKCTLST_HAVEHTREQ    0x00000010 /* HT available request */
-#define  BCMA_CC_CLKCTLST_HWCROFF      0x00000020 /* Force HW clock request off */
-#define  BCMA_CC_CLKCTLST_HAVEHT       0x00010000 /* HT available */
-#define  BCMA_CC_CLKCTLST_HAVEALP      0x00020000 /* APL available */
+/* 0x1E0 is defined as shared BCMA_CLKCTLST */
 #define BCMA_CC_HW_WORKAROUND          0x01E4 /* Hardware workaround (rev >= 20) */
 #define BCMA_CC_UART0_DATA             0x0300
 #define BCMA_CC_UART0_IMR              0x0304

diff --git a/include/linux/bcma/bcma_regs.h b/include/linux/bcma/bcma_regs.h
index 889219535a833bd0ea11e54c829d09bb932055e6..9faae2ae02e8c34abecffc6bcb86f2d0c0fcb72b 100644 (file)
--- a/include/linux/bcma/bcma_regs.h
+++ b/include/linux/bcma/bcma_regs.h
@@ -1,6 +1,25 @@
 #ifndef LINUX_BCMA_REGS_H_
 #define LINUX_BCMA_REGS_H_
 
+/* Some single registers are shared between many cores */
+/* BCMA_CLKCTLST: ChipCommon (rev >= 20), PCIe, 80211 */
+#define BCMA_CLKCTLST                  0x01E0 /* Clock control and status */
+#define  BCMA_CLKCTLST_FORCEALP                0x00000001 /* Force ALP request */
+#define  BCMA_CLKCTLST_FORCEHT         0x00000002 /* Force HT request */
+#define  BCMA_CLKCTLST_FORCEILP                0x00000004 /* Force ILP request */
+#define  BCMA_CLKCTLST_HAVEALPREQ      0x00000008 /* ALP available request */
+#define  BCMA_CLKCTLST_HAVEHTREQ       0x00000010 /* HT available request */
+#define  BCMA_CLKCTLST_HWCROFF         0x00000020 /* Force HW clock request off */
+#define  BCMA_CLKCTLST_EXTRESREQ       0x00000700 /* Mask of external resource requests */
+#define  BCMA_CLKCTLST_HAVEALP         0x00010000 /* ALP available */
+#define  BCMA_CLKCTLST_HAVEHT          0x00020000 /* HT available */
+#define  BCMA_CLKCTLST_BP_ON_ALP       0x00040000 /* RO: running on ALP clock */
+#define  BCMA_CLKCTLST_BP_ON_HT                0x00080000 /* RO: running on HT clock */
+#define  BCMA_CLKCTLST_EXTRESST                0x07000000 /* Mask of external resource status */
+/* Is there any BCM4328 on BCMA bus? */
+#define  BCMA_CLKCTLST_4328A0_HAVEHT   0x00010000 /* 4328a0 has reversed bits */
+#define  BCMA_CLKCTLST_4328A0_HAVEALP  0x00020000 /* 4328a0 has reversed bits */
+
 /* Agent registers (common for every core) */
 #define BCMA_IOCTL                     0x0408 /* IO control */
 #define  BCMA_IOCTL_CLK                        0x0001