-obj-y := reset.o prom.o setup.o interrupt.o dma-core.o pmu.o board.o clock.o timer.o gpio.o
+obj-y := reset.o prom.o setup.o interrupt.o dma-core.o pmu.o board.o clock.o gpio.o
static struct ifxmips_board boards[] = {
{
+ /* infineon eval kit */
.type = EASY50712,
.name = "EASY50712",
.system_type = SYSTEM_DANUBE_CHIPID1,
.end = (1 << 0) | (1 << 1)},
.ifxmips_leds = easy50712_leds,
}, {
+ /* infineon eval kit */
.type = EASY4010,
.name = "EASY4010",
.system_type = SYSTEM_TWINPASS_CHIPID,
.end = (1 << 0) | (1 << 1)},
.ifxmips_leds = easy4010_leds,
}, {
+ /* arcaydian annex-a board used by thompson, airties, ... */
.type = ARV4519,
.name = "ARV4519",
.system_type = SYSTEM_DANUBE_CHIPID2,
ifxmips_led_data.num_leds = ARRAY_SIZE(easy4010_leds);
break;
case ARV4519:
+ /* set some sane defaults for the gpios */
gpio_set_value(3, 0);
gpio_set_value(4, 0);
gpio_set_value(5, 0);
.end = ifxmips_end_irq,
};
+/* silicon bug causes only the msb set to 1 to be valid. all
+ other bits might be bogus */
static inline int ls1bit32(unsigned long x)
{
__asm__ (
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*
* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
+ *
+ * code used for handling the power management unit of the danube. using
+ * the pmu we can turn the power of the seperate ip cores on/off.
*/
#include <linux/kernel.h>
/* for Multithreading (APRP) on MIPS34K */
unsigned long physical_memsize;
+/* early printk on asc0 or asc1 ? */
#ifdef CONFIG_IFXMIPS_PROM_ASC0
#define IFXMIPS_ASC_DIFF 0
#else
+++ /dev/null
-//*************************************************************************
-//* Summary of definitions which are used in each peripheral *
-//*************************************************************************
-
-#ifndef peripheral_definitions_h
-#define peripheral_definitions_h
-
-////#include "cpu.h"
-//
-///* These files have to be included by each peripheral */
-//#include <sysdefs.h>
-//#include <excep.h>
-//#include <cpusubsys.h>
-//#include <sys_api.h>
-//#include <mips.h>
-//#include "SRAM_address_map.h"
-//
-///* common header files for all CPU's */
-//#include "iiu.h"
-//#include "bcu.h"
-//#include "FPI_address_map.h"
-//#include "direct_interrupts.h"
-
-/////////////////////////////////////////////////////////////////////////
-
-//extern int _clz();
-//extern void _nop();
-//extern void _sleep();
-//extern void sys_enable_int();
-
-typedef unsigned char UINT8;
-typedef signed char INT8;
-typedef unsigned short UINT16;
-typedef signed short INT16;
-typedef unsigned int UINT32;
-typedef signed int INT32;
-typedef unsigned long long UINT64;
-typedef signed long long INT64;
-
-#define REG8( addr ) (*(volatile UINT8 *) (addr))
-#define REG16( addr ) (*(volatile UINT16 *)(addr))
-#define REG32( addr ) (*(volatile UINT32 *)(addr))
-#define REG64( addr ) (*(volatile UINT64 *)(addr))
-
-/* define routine to set FPI access in Supervisor Mode */
-#define IFX_SUPERVISOR_ON() REG32(FB0_CFG) = 0x01
-/* Supervisor mode ends, following functions will be done in User mode */
-#define IFX_SUPERVISOR_OFF() REG32(FB0_CFG) = 0x00
-/* Supervisor mode ends, following functions will be done in User mode */
-#define IFX_SUPERVISOR_MODE() REG32(FB0_CFG)
-/* Supervisor mode ends, following functions will be done in User mode */
-#define IFX_SUPERVISOR_SET(svm) REG32(FB0_CFG) = svm
-/* enable all Interrupts in IIU */
-//#define IFX_ENABLE_IRQ(irq_mask, im_base) REG32(im_base | IIU_MASK) = irq_mask
-///* get all high priority interrupt bits in IIU */
-//#define IFX_GET_IRQ_MASKED(im_base) REG32(im_base | IIU_IRMASKED)
-///* signal ends of interrupt to IIU */
-//#define IFX_CLEAR_DIRECT_IRQ(irq_bit, im_base) REG32(im_base | IIU_IR) = irq_bit
-///* force IIU interrupt register */
-//#define IFX_FORCE_IIU_REGISTER(data, im_base) REG32(im_base | IIU_IRDEBUG) = data
-///* get all bits of interrupt register */
-//#define IFX_GET_IRQ_UNMASKED(im_base) REG32(im_base | IIU_IR)
-/* insert a NOP instruction */
-#define NOP _nop()
-/* CPU goes to power down mode until interrupt occurs */
-#define IFX_CPU_SLEEP _sleep()
-/* enable all interrupts to CPU */
-#define IFX_CPU_ENABLE_ALL_INTERRUPT sys_enable_int()
-/* get all low priority interrupt bits in peripheral */
-#define IFX_GET_LOW_PRIO_IRQ(int_reg) REG32(int_reg)
-/* clear low priority interrupt bit in peripheral */
-#define IFX_CLEAR_LOW_PRIO_IRQ(irq_bit, int_reg) REG32(int_reg) = irq_bit
-/* write FPI bus */
-#define WRITE_FPI_BYTE(data, addr) REG8(addr) = data
-#define WRITE_FPI_16BIT(data, addr) REG16(addr) = data
-#define WRITE_FPI_32BIT(data, addr) REG32(addr) = data
-/* read FPI bus */
-#define READ_FPI_BYTE(addr) REG8(addr)
-#define READ_FPI_16BIT(addr) REG16(addr)
-#define READ_FPI_32BIT(addr) REG32(addr)
-/* write peripheral register */
-#define WRITE_PERIPHERAL_REGISTER(data, addr) REG32(addr) = data
-
-#ifdef CONFIG_CPU_LITTLE_ENDIAN
-#define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr) = data
-#define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr) = data
-#else //not CONFIG_CPU_LITTLE_ENDIAN
-#define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr+2) = data
-#define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr+3) = data
-#endif //CONFIG_CPU_LITTLE_ENDIAN
-
-/* read peripheral register */
-#define READ_PERIPHERAL_REGISTER(addr) REG32(addr)
-
-/* read/modify(or)/write peripheral register */
-#define RMW_OR_PERIPHERAL_REGISTER(data, addr) REG32(addr) = REG32(addr) | data
-/* read/modify(and)/write peripheral register */
-#define RMW_AND_PERIPHERAL_REGISTER(data, addr) REG32(addr) = REG32(addr) & (UINT32)data
-
-/* CPU-independent mnemonic constants */
-/* CLC register bits */
-#define IFX_CLC_ENABLE 0x00000000
-#define IFX_CLC_DISABLE 0x00000001
-#define IFX_CLC_DISABLE_STATUS 0x00000002
-#define IFX_CLC_SUSPEND_ENABLE 0x00000004
-#define IFX_CLC_CLOCK_OFF_DISABLE 0x00000008
-#define IFX_CLC_OVERWRITE_SPEN_FSOE 0x00000010
-#define IFX_CLC_FAST_CLOCK_SWITCH_OFF 0x00000020
-#define IFX_CLC_RUN_DIVIDER_MASK 0x0000FF00
-#define IFX_CLC_RUN_DIVIDER_OFFSET 8
-#define IFX_CLC_SLEEP_DIVIDER_MASK 0x00FF0000
-#define IFX_CLC_SLEEP_DIVIDER_OFFSET 16
-#define IFX_CLC_SPECIFIC_DIVIDER_MASK 0x00FF0000
-#define IFX_CLC_SPECIFIC_DIVIDER_OFFSET 24
-
-/* number of cycles to wait for interrupt service routine to be called */
-#define WAIT_CYCLES 50
-
-#endif /* PERIPHERAL_DEFINITIONS_H not yet defined */
+++ /dev/null
-/*
- * ifx_ssc.h defines some data sructures used in ifx_ssc.c
- *
- * Copyright (C) 2004 Michael Schoenenborn (IFX COM TI BT)
- *
- *
- */
-
-#ifndef __IFX_SSC_H
-#define __IFX_SSC_H
-#ifdef __KERNEL__
-#include <asm/ifxmips/ifx_ssc_defines.h>
-#endif //__KERNEL__
-
-#define PORT_CNT 1 // assume default value
-
-/* symbolic constants to be used in SSC routines */
-
-// ### TO DO: bad performance
-#define IFX_SSC_TXFIFO_ITL 1
-#define IFX_SSC_RXFIFO_ITL 1
-
-struct ifx_ssc_statistics {
- unsigned int abortErr; /* abort error */
- unsigned int modeErr; /* master/slave mode error */
- unsigned int txOvErr; /* TX Overflow error */
- unsigned int txUnErr; /* TX Underrun error */
- unsigned int rxOvErr; /* RX Overflow error */
- unsigned int rxUnErr; /* RX Underrun error */
- unsigned int rxBytes;
- unsigned int txBytes;
-};
-
-struct ifx_ssc_hwopts {
- unsigned int AbortErrDetect:1; /* Abort Error detection (in slave mode) */
- unsigned int rxOvErrDetect:1; /* Receive Overflow Error detection */
- unsigned int rxUndErrDetect:1; /* Receive Underflow Error detection */
- unsigned int txOvErrDetect:1; /* Transmit Overflow Error detection */
- unsigned int txUndErrDetect:1; /* Transmit Underflow Error detection */
- unsigned int echoMode:1; /* Echo mode */
- unsigned int loopBack:1; /* Loopback mode */
- unsigned int idleValue:1; /* Idle value */
- unsigned int clockPolarity:1; /* Idle clock is high or low */
- unsigned int clockPhase:1; /* Tx on trailing or leading edge */
- unsigned int headingControl:1; /* LSB first or MSB first */
- unsigned int dataWidth:6; /* from 2 up to 32 bits */
- unsigned int masterSelect:1; /* Master or Slave mode */
- unsigned int modeRxTx:2; /* rx/tx mode */
- unsigned int gpoCs:8; /* choose outputs to use for chip select */
- unsigned int gpoInv:8; /* invert GPO outputs */
-};
-
-struct ifx_ssc_frm_opts {
- bool FrameEnable; // SFCON.SFEN
- unsigned int DataLength; // SFCON.DLEN
- unsigned int PauseLength; // SFCON.PLEN
- unsigned int IdleData; // SFCON.IDAT
- unsigned int IdleClock; // SFCON.ICLK
- bool StopAfterPause; // SFCON.STOP
-};
-
-struct ifx_ssc_frm_status {
- bool DataBusy; // SFSTAT.DBSY
- bool PauseBusy; // SFSTAT.PBSY
- unsigned int DataCount; // SFSTAT.DCNT
- unsigned int PauseCount; // SFSTAT.PCNT
- bool EnIntAfterData; // SFCON.IBEN
- bool EnIntAfterPause; // SFCON.IAEN
-};
-
-typedef struct {
- char *buf;
- size_t len;
-} ifx_ssc_buf_item_t;
-
-// data structures for batch execution
-typedef union {
- struct {
- bool save_options;
- } init;
- ifx_ssc_buf_item_t read;
- ifx_ssc_buf_item_t write;
- ifx_ssc_buf_item_t rd_wr;
- unsigned int set_baudrate;
- struct ifx_ssc_frm_opts set_frm;
- unsigned int set_gpo;
- struct ifx_ssc_hwopts set_hwopts;
-} ifx_ssc_batch_cmd_param;
-
-struct ifx_ssc_batch_list {
- unsigned int cmd;
- ifx_ssc_batch_cmd_param cmd_param;
- struct ifx_ssc_batch_list *next;
-};
-
-#ifdef __KERNEL__
-#define IFX_SSC_IS_MASTER(p) ((p)->opts.masterSelect == SSC_MASTER_MODE)
-
-struct ifx_ssc_port {
- unsigned long mapbase;
- struct ifx_ssc_hwopts opts;
- struct ifx_ssc_statistics stats;
- struct ifx_ssc_frm_status frm_status;
- struct ifx_ssc_frm_opts frm_opts;
- /* wait queue for ifx_ssc_read() */
- wait_queue_head_t rwait, pwait;
- int port_nr;
- char port_is_open; /* exclusive open - boolean */
-// int no_of_bits; /* number of _valid_ bits */
-// int elem_size; /* shift for element (no of bytes)*/
- /* buffer and pointers to the read/write position */
- char *rxbuf; /* buffer for RX */
- char *rxbuf_end; /* buffer end pointer for RX */
- volatile char *rxbuf_ptr; /* buffer write pointer for RX */
- char *txbuf; /* buffer for TX */
- char *txbuf_end; /* buffer end pointer for TX */
- volatile char *txbuf_ptr; /* buffer read pointer for TX */
- unsigned int baud;
- /* each channel has its own interrupts */
- /* (transmit/receive/error/frame) */
- unsigned int txirq, rxirq, errirq, frmirq;
-};
-/* default values for SSC configuration */
-// values of CON
-#define IFX_SSC_DEF_IDLE_DATA 1 /* enable */
-#define IFX_SSC_DEF_BYTE_VALID_CTL 1 /* enable */
-#define IFX_SSC_DEF_DATA_WIDTH 32 /* bits */
-#define IFX_SSC_DEF_ABRT_ERR_DETECT 0 /* disable */
-#define IFX_SSC_DEF_RO_ERR_DETECT 1 /* enable */
-#define IFX_SSC_DEF_RU_ERR_DETECT 0 /* disable */
-#define IFX_SSC_DEF_TO_ERR_DETECT 0 /* disable */
-#define IFX_SSC_DEF_TU_ERR_DETECT 0 /* disable */
-#define IFX_SSC_DEF_LOOP_BACK 0 /* disable */
-#define IFX_SSC_DEF_ECHO_MODE 0 /* disable */
-#define IFX_SSC_DEF_CLOCK_POLARITY 0 /* low */
-#define IFX_SSC_DEF_CLOCK_PHASE 1 /* 0: shift on leading edge, latch on trailling edge, 1, otherwise */
-#define IFX_SSC_DEF_HEADING_CONTROL IFX_SSC_MSB_FIRST
-#define IFX_SSC_DEF_MODE_RXTX IFX_SSC_MODE_RXTX
-// other values
-#define IFX_SSC_DEF_MASTERSLAVE IFX_SSC_MASTER_MODE /* master */
-#ifdef CONFIG_USE_EMULATOR
-#define IFX_SSC_DEF_BAUDRATE 10000
-#else
-#define IFX_SSC_DEF_BAUDRATE 2000000
-#endif
-#define IFX_SSC_DEF_RMC 0x10
-
-#define IFX_SSC_DEF_TXFIFO_FL 8
-#define IFX_SSC_DEF_RXFIFO_FL 1
-
-#if 1 //TODO
-#define IFX_SSC_DEF_GPO_CS 0x3 /* no chip select */
-#define IFX_SSC_DEF_GPO_INV 0 /* no chip select */
-#else
-#error "what is ur Chip Select???"
-#endif
-#define IFX_SSC_DEF_SFCON 0 /* no serial framing */
-#if 0
-#define IFX_SSC_DEF_IRNEN IFX_SSC_T_BIT | /* enable all int's */\
- IFX_SSC_R_BIT | IFX_SSC_E_BIT | IFX_SSC_F_BIT
-#endif
-#define IFX_SSC_DEF_IRNEN IFX_SSC_T_BIT | /* enable all int's */\
- IFX_SSC_R_BIT | IFX_SSC_E_BIT
-#endif /* __KERNEL__ */
-
-// batch execution commands
-#define IFX_SSC_BATCH_CMD_INIT 1
-#define IFX_SSC_BATCH_CMD_READ 2
-#define IFX_SSC_BATCH_CMD_WRITE 3
-#define IFX_SSC_BATCH_CMD_RD_WR 4
-#define IFX_SSC_BATCH_CMD_SET_BAUDRATE 5
-#define IFX_SSC_BATCH_CMD_SET_HWOPTS 6
-#define IFX_SSC_BATCH_CMD_SET_FRM 7
-#define IFX_SSC_BATCH_CMD_SET_GPO 8
-#define IFX_SSC_BATCH_CMD_FIFO_FLUSH 9
-//#define IFX_SSC_BATCH_CMD_
-//#define IFX_SSC_BATCH_CMD_
-#define IFX_SSC_BATCH_CMD_END_EXEC 0
-
-/* Macros to configure SSC hardware */
-/* headingControl: */
-#define IFX_SSC_LSB_FIRST 0
-#define IFX_SSC_MSB_FIRST 1
-/* dataWidth: */
-#define IFX_SSC_MIN_DATA_WIDTH 2
-#define IFX_SSC_MAX_DATA_WIDTH 32
-/* master/slave mode select */
-#define IFX_SSC_MASTER_MODE 1
-#define IFX_SSC_SLAVE_MODE 0
-/* rx/tx mode */
-// ### TO DO: !!! ATTENTION! Hardware dependency => move to ifx_ssc_defines.h
-#define IFX_SSC_MODE_RXTX 0
-#define IFX_SSC_MODE_RX 1
-#define IFX_SSC_MODE_TX 2
-#define IFX_SSC_MODE_OFF 3
-#define IFX_SSC_MODE_MASK IFX_SSC_MODE_RX | IFX_SSC_MODE_TX
-
-/* GPO values */
-#define IFX_SSC_MAX_GPO_OUT 7
-
-#define IFX_SSC_RXREQ_BLOCK_SIZE 32768
-
-/***********************/
-/* defines for ioctl's */
-/***********************/
-#define IFX_SSC_IOCTL_MAGIC 'S'
-/* read out the statistics */
-#define IFX_SSC_STATS_READ _IOR(IFX_SSC_IOCTL_MAGIC, 1, struct ifx_ssc_statistics)
-/* clear the statistics */
-#define IFX_SSC_STATS_RESET _IO(IFX_SSC_IOCTL_MAGIC, 2)
-/* set the baudrate */
-#define IFX_SSC_BAUD_SET _IOW(IFX_SSC_IOCTL_MAGIC, 3, unsigned int)
-/* get the current baudrate */
-#define IFX_SSC_BAUD_GET _IOR(IFX_SSC_IOCTL_MAGIC, 4, unsigned int)
-/* set hardware options */
-#define IFX_SSC_HWOPTS_SET _IOW(IFX_SSC_IOCTL_MAGIC, 5, struct ifx_ssc_hwopts)
-/* get the current hardware options */
-#define IFX_SSC_HWOPTS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 6, struct ifx_ssc_hwopts)
-/* set transmission mode */
-#define IFX_SSC_RXTX_MODE_SET _IOW(IFX_SSC_IOCTL_MAGIC, 7, unsigned int)
-/* get the current transmission mode */
-#define IFX_SSC_RXTX_MODE_GET _IOR(IFX_SSC_IOCTL_MAGIC, 8, unsigned int)
-/* abort transmission */
-#define IFX_SSC_ABORT _IO(IFX_SSC_IOCTL_MAGIC, 9)
-#define IFX_SSC_FIFO_FLUSH _IO(IFX_SSC_IOCTL_MAGIC, 9)
-
-/* set general purpose outputs */
-#define IFX_SSC_GPO_OUT_SET _IOW(IFX_SSC_IOCTL_MAGIC, 32, unsigned int)
-/* clear general purpose outputs */
-#define IFX_SSC_GPO_OUT_CLR _IOW(IFX_SSC_IOCTL_MAGIC, 33, unsigned int)
-/* get general purpose outputs */
-#define IFX_SSC_GPO_OUT_GET _IOR(IFX_SSC_IOCTL_MAGIC, 34, unsigned int)
-
-/*** serial framing ***/
-/* get status of serial framing */
-#define IFX_SSC_FRM_STATUS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 48, struct ifx_ssc_frm_status)
-/* get counter reload values and control bits */
-#define IFX_SSC_FRM_CONTROL_GET _IOR(IFX_SSC_IOCTL_MAGIC, 49, struct ifx_ssc_frm_opts)
-/* set counter reload values and control bits */
-#define IFX_SSC_FRM_CONTROL_SET _IOW(IFX_SSC_IOCTL_MAGIC, 50, struct ifx_ssc_frm_opts)
-
-/*** batch execution ***/
-/* do batch execution */
-#define IFX_SSC_BATCH_EXEC _IOW(IFX_SSC_IOCTL_MAGIC, 64, struct ifx_ssc_batch_list)
-
-#ifdef __KERNEL__
-// routines from ifx_ssc.c
-// ### TO DO
-/* kernel interface for read and write */
-ssize_t ifx_ssc_kread (int, char *, size_t);
-ssize_t ifx_ssc_kwrite (int, const char *, size_t);
-
-#ifdef CONFIG_IFX_VP_KERNEL_TEST
-void ifx_ssc_tc (void);
-#endif // CONFIG_IFX_VP_KERNEL_TEST
-
-#endif //__KERNEL__
-#endif // __IFX_SSC_H
+++ /dev/null
-#ifndef IFX_SSC_DEFINES_H
-#define IFX_SSC_DEFINES_H
-
-#include "ifx_peripheral_definitions.h"
-
-/* maximum SSC FIFO size */
-#define IFX_SSC_MAX_FIFO_SIZE 32
-
-/* register map of SSC */
-
-/* address of the Clock Control Register of the SSC */
-#define IFX_SSC_CLC 0x00000000
-/* IFX_SSC_CLC register is significant in bits 23 downto 8 and in bits 5, 3, 2, 0
- bit 1 is hardware modified*/
-#define IFX_SSC_CLC_readmask 0x00FFFFEF
-#define IFX_SSC_CLC_writemask 0x00FFFF3D
-#define IFX_SSC_CLC_hwmask 0x00000002
-#define IFX_SSC_CLC_dontcare (IFX_SSC_CLC_readmask & IFX_SSC_CLC_writemask & ~IFX_SSC_CLC_hwmask)
-
-/* address of Port Input Select Register of the SSC */
-#define IFX_SSC_PISEL 0x00000004
-/* IFX_SSC_PISEL register is significant in lowest three bits only */
-#define IFX_SSC_PISEL_readmask 0x00000007
-#define IFX_SSC_PISEL_writemask 0x00000007
-#define IFX_SSC_PISEL_hwmask 0x00000000
-#define IFX_SSC_PISEL_dontcare (IFX_SSC_PISEL_readmask & IFX_SSC_PISEL_writemask & ~IFX_SSC_PISEL_hwmask)
-
-/* address of Identification Register of the SSC */
-#define IFX_SSC_ID 0x00000008
-/* IFX_SSC_ID register is significant in no bit */
-#define IFX_SSC_ID_readmask 0x0000FF3F
-#define IFX_SSC_ID_writemask 0x00000000
-#define IFX_SSC_ID_hwmask 0x00000000
-#define IFX_SSC_ID_dontcare (IFX_SSC_ID_readmask & IFX_SSC_ID_writemask & ~IFX_SSC_ID_hwmask)
-
-/* address of the Control Register of the SSC */
-#define IFX_SSC_CON 0x00000010
-/* IFX_SSC_CON register is significant in bits 23:22, 20:16 and 12:0 */
-#define IFX_SSC_CON_readmask 0x01DF1FFF
-#define IFX_SSC_CON_writemask 0x01DF1FFF
-#define IFX_SSC_CON_hwmask 0x00000000
-#define IFX_SSC_CON_dontcare (IFX_SSC_CON_readmask & IFX_SSC_CON_writemask & ~IFX_SSC_CON_hwmask)
-
-/* address of the Status Register of the SSC */
-#define IFX_SSC_STATE 0x00000014
-/* IFX_SSC_STATE register is readable in bits 30:28, 26:24, 20:16, 12:7 and 2:0
- all bits except 1:0 are hardware modified */
-#define IFX_SSC_STATE_readmask 0x771F3F87
-#define IFX_SSC_STATE_writemask 0x00000000
-#define IFX_SSC_STATE_hwmask 0x771F3F84
-#define IFX_SSC_STATE_dontcare (IFX_SSC_STATE_readmask & IFX_SSC_STATE_writemask & ~IFX_SSC_STATE_hwmask)
-
-/* address of the Write Hardware Modified Control Register Bits of the SSC */
-#define IFX_SSC_WHBSTATE 0x00000018
-/* IFX_SSC_WHBSTATE register is write only */
-#define IFX_SSC_WHBSTATE_readmask 0x00000000
-#define IFX_SSC_WHBSTATE_writemask 0x0000FFFF
-#define IFX_SSC_WHBSTATE_hwmask 0x00000000
-#define IFX_SSC_WHBSTATE_dontcare (IFX_SSC_WHBSTATE_readmask & IFX_SSC_WHBSTATE_writemask & ~IFX_SSC_WHBSTATE_hwmask)
-
-/* address of the Baudrate Timer Reload Register of the SSC */
-#define IFX_SSC_BR 0x00000040
-/* IFX_SSC_BR register is significant in bit 15 downto 0*/
-#define IFX_SSC_BR_readmask 0x0000FFFF
-#define IFX_SSC_BR_writemask 0x0000FFFF
-#define IFX_SSC_BR_hwmask 0x00000000
-#define IFX_SSC_BR_dontcare (IFX_SSC_BR_readmask & IFX_SSC_BR_writemask & ~IFX_SSC_BR_hwmask)
-
-/* address of the Baudrate Timer Status Register of the SSC */
-#define IFX_SSC_BRSTAT 0x00000044
-/* IFX_SSC_BRSTAT register is significant in bit 15 downto 0*/
-#define IFX_SSC_BRSTAT_readmask 0x0000FFFF
-#define IFX_SSC_BRSTAT_writemask 0x00000000
-#define IFX_SSC_BRSTAT_hwmask 0x0000FFFF
-#define IFX_SSC_BRSTAT_dontcare (IFX_SSC_BRSTAT_readmask & IFX_SSC_BRSTAT_writemask & ~IFX_SSC_BRSTAT_hwmask)
-
-/* address of the Transmitter Buffer Register of the SSC */
-#define IFX_SSC_TB 0x00000020
-/* IFX_SSC_TB register is significant in bit 31 downto 0*/
-#define IFX_SSC_TB_readmask 0xFFFFFFFF
-#define IFX_SSC_TB_writemask 0xFFFFFFFF
-#define IFX_SSC_TB_hwmask 0x00000000
-#define IFX_SSC_TB_dontcare (IFX_SSC_TB_readmask & IFX_SSC_TB_writemask & ~IFX_SSC_TB_hwmask)
-
-/* address of the Reciver Buffer Register of the SSC */
-#define IFX_SSC_RB 0x00000024
-/* IFX_SSC_RB register is significant in no bits*/
-#define IFX_SSC_RB_readmask 0xFFFFFFFF
-#define IFX_SSC_RB_writemask 0x00000000
-#define IFX_SSC_RB_hwmask 0xFFFFFFFF
-#define IFX_SSC_RB_dontcare (IFX_SSC_RB_readmask & IFX_SSC_RB_writemask & ~IFX_SSC_RB_hwmask)
-
-/* address of the Receive FIFO Control Register of the SSC */
-#define IFX_SSC_RXFCON 0x00000030
-/* IFX_SSC_RXFCON register is significant in bit 13 downto 8 and bit 1 downto 0 */
-#define IFX_SSC_RXFCON_readmask 0x00003F03
-#define IFX_SSC_RXFCON_writemask 0x00003F03
-#define IFX_SSC_RXFCON_hwmask 0x00000000
-#define IFX_SSC_RXFCON_dontcare (IFX_SSC_RXFCON_readmask & IFX_SSC_RXFCON_writemask & ~IFX_SSC_RXFCON_hwmask)
-
-/* address of the Transmit FIFO Control Register of the SSC */
-#define IFX_SSC_TXFCON 0x00000034
-/* IFX_SSC_TXFCON register is significant in bit 13 downto 8 and bit 1 downto 0 */
-#define IFX_SSC_TXFCON_readmask 0x00003F03
-#define IFX_SSC_TXFCON_writemask 0x00003F03
-#define IFX_SSC_TXFCON_hwmask 0x00000000
-#define IFX_SSC_TXFCON_dontcare (IFX_SSC_TXFCON_readmask & IFX_SSC_TXFCON_writemask & ~IFX_SSC_TXFCON_hwmask)
-
-/* address of the FIFO Status Register of the SSC */
-#define IFX_SSC_FSTAT 0x00000038
-/* IFX_SSC_FSTAT register is significant in no bit*/
-#define IFX_SSC_FSTAT_readmask 0x00003F3F
-#define IFX_SSC_FSTAT_writemask 0x00000000
-#define IFX_SSC_FSTAT_hwmask 0x00003F3F
-#define IFX_SSC_FSTAT_dontcare (IFX_SSC_FSTAT_readmask & IFX_SSC_FSTAT_writemask & ~IFX_SSC_FSTAT_hwmask)
-
-/* address of the Data Frame Control register of the SSC */
-#define IFX_SSC_SFCON 0x00000060
-#define IFX_SSC_SFCON_readmask 0xFFDFFFFD
-#define IFX_SSC_SFCON_writemask 0xFFDFFFFD
-#define IFX_SSC_SFCON_hwmask 0x00000000
-#define IFX_SSC_SFCON_dontcare (IFX_SSC_SFCON_readmask & IFX_SSC_SFCON_writemask & ~IFX_SSC_SFCON_hwmask)
-
-/* address of the Data Frame Status register of the SSC */
-#define IFX_SSC_SFSTAT 0x00000064
-#define IFX_SSC_SFSTAT_readmask 0xFFC0FFF3
-#define IFX_SSC_SFSTAT_writemask 0x00000000
-#define IFX_SSC_SFSTAT_hwmask 0xFFC0FFF3
-#define IFX_SSC_SFSTAT_dontcare (IFX_SSC_SFSTAT_readmask & IFX_SSC_SFSTAT_writemask & ~IFX_SSC_SFSTAT_hwmask)
-
-/* address of the General Purpose Output Control register of the SSC */
-#define IFX_SSC_GPOCON 0x00000070
-#define IFX_SSC_GPOCON_readmask 0x0000FFFF
-#define IFX_SSC_GPOCON_writemask 0x0000FFFF
-#define IFX_SSC_GPOCON_hwmask 0x00000000
-#define IFX_SSC_GPOCON_dontcare (IFX_SSC_GPOCON_readmask & IFX_SSC_GPOCON_writemask & ~IFX_SSC_GPOCON_hwmask)
-
-/* address of the General Purpose Output Status register of the SSC */
-#define IFX_SSC_GPOSTAT 0x00000074
-#define IFX_SSC_GPOSTAT_readmask 0x000000FF
-#define IFX_SSC_GPOSTAT_writemask 0x00000000
-#define IFX_SSC_GPOSTAT_hwmask 0x00000000
-#define IFX_SSC_GPOSTAT_dontcare (IFX_SSC_GPOSTAT_readmask & IFX_SSC_GPOSTAT_writemask & ~IFX_SSC_GPOSTAT_hwmask)
-
-/* address of the Force GPO Status register of the SSC */
-#define IFX_SSC_WHBGPOSTAT 0x00000078
-#define IFX_SSC_WHBGPOSTAT_readmask 0x00000000
-#define IFX_SSC_WHBGPOSTAT_writemask 0x0000FFFF
-#define IFX_SSC_WHBGPOSTAT_hwmask 0x00000000
-#define IFX_SSC_WHBGPOSTAT_dontcare (IFX_SSC_WHBGPOSTAT_readmask & IFX_SSC_WHBGPOSTAT_writemask & ~IFX_SSC_WHBGPOSTAT_hwmask)
-
-/* address of the Receive Request Register of the SSC */
-#define IFX_SSC_RXREQ 0x00000080
-#define IFX_SSC_RXREQ_readmask 0x0000FFFF
-#define IFX_SSC_RXREQ_writemask 0x0000FFFF
-#define IFX_SSC_RXREQ_hwmask 0x00000000
-#define IFX_SSC_RXREQ_dontcare (IFX_SSC_RXREQ_readmask & IFX_SSC_RXREQ_writemask & ~IFX_SSC_RXREQ_hwmask)
-
-/* address of the Receive Count Register of the SSC */
-#define IFX_SSC_RXCNT 0x00000084
-#define IFX_SSC_RXCNT_readmask 0x0000FFFF
-#define IFX_SSC_RXCNT_writemask 0x00000000
-#define IFX_SSC_RXCNT_hwmask 0x0000FFFF
-#define IFX_SSC_RXCNT_dontcare (IFX_SSC_RXCNT_readmask & IFX_SSC_RXCNT_writemask & ~IFX_SSC_RXCNT_hwmask)
-
-/* address of the DMA Configuration Register of the SSC */
-#define IFX_SSC_DMACON 0x000000EC
-#define IFX_SSC_DMACON_readmask 0x0000FFFF
-#define IFX_SSC_DMACON_writemask 0x00000000
-#define IFX_SSC_DMACON_hwmask 0x0000FFFF
-#define IFX_SSC_DMACON_dontcare (IFX_SSC_DMACON_readmask & IFX_SSC_DMACON_writemask & ~IFX_SSC_DMACON_hwmask)
-
-//------------------------------------------------------
-// interrupt register for enabling interrupts, mask register of irq_reg
-#define IFX_SSC_IRN_EN 0xF4
-// read/write
-#define IFX_SSC_IRN_EN_readmask 0x0000000F
-#define IFX_SSC_IRN_EN_writemask 0x0000000F
-#define IFX_SSC_IRN_EN_hwmask 0x00000000
-#define IFX_SSC_IRN_EN_dontcare (IFX_SSC_IRN_EN_readmask & IFX_SSC_IRN_EN_writemask & ~IFX_SSC_IRN_EN_hwmask)
-
-// interrupt register for accessing interrupts
-#define IFX_SSC_IRN_CR 0xF8
-// read/write
-#define IFX_SSC_IRN_CR_readmask 0x0000000F
-#define IFX_SSC_IRN_CR_writemask 0x0000000F
-#define IFX_SSC_IRN_CR_hwmask 0x0000000F
-#define IFX_SSC_IRN_CR_dontcare (IFX_SSC_IRN_CR_readmask & IFX_SSC_IRN_CR_writemask & ~IFX_SSC_IRN_CR_hwmask)
-
-// interrupt register for stimulating interrupts
-#define IFX_SSC_IRN_ICR 0xFC
-// read/write
-#define IFX_SSC_IRN_ICR_readmask 0x0000000F
-#define IFX_SSC_IRN_ICR_writemask 0x0000000F
-#define IFX_SSC_IRN_ICR_hwmask 0x00000000
-#define IFX_SSC_IRN_ICR_dontcare (IFX_SSC_IRN_ICR_readmask & IFX_SSC_IRN_ICR_writemask & ~IFX_SSC_IRN_ICR_hwmask)
-
-//---------------------------------------------------------------------
-// Number of IRQs and bitposition of IRQ
-#define IFX_SSC_NUM_IRQ 4
-#define IFX_SSC_T_BIT 0x00000001
-#define IFX_SSC_R_BIT 0x00000002
-#define IFX_SSC_E_BIT 0x00000004
-#define IFX_SSC_F_BIT 0x00000008
-
-/* bit masks for SSC registers */
-
-/* ID register */
-#define IFX_SSC_PERID_REV_MASK 0x0000001F
-#define IFX_SSC_PERID_CFG_MASK 0x00000020
-#define IFX_SSC_PERID_ID_MASK 0x0000FF00
-#define IFX_SSC_PERID_REV_OFFSET 0
-#define IFX_SSC_PERID_CFG_OFFSET 5
-#define IFX_SSC_PERID_ID_OFFSET 8
-#define IFX_SSC_PERID_ID 0x45
-#define IFX_SSC_PERID_DMA_ON 0x00000020
-#define IFX_SSC_PERID_RXFS_MASK 0x003F0000
-#define IFX_SSC_PERID_RXFS_OFFSET 16
-#define IFX_SSC_PERID_TXFS_MASK 0x3F000000
-#define IFX_SSC_PERID_TXFS_OFFSET 24
-
-/* PISEL register */
-#define IFX_SSC_PISEL_MASTER_IN_A 0x0000
-#define IFX_SSC_PISEL_MASTER_IN_B 0x0001
-#define IFX_SSC_PISEL_SLAVE_IN_A 0x0000
-#define IFX_SSC_PISEL_SLAVE_IN_B 0x0002
-#define IFX_SSC_PISEL_CLOCK_IN_A 0x0000
-#define IFX_SSC_PISEL_CLOCK_IN_B 0x0004
-
-/* IFX_SSC_CON register */
-#define IFX_SSC_CON_ECHO_MODE_ON 0x01000000
-#define IFX_SSC_CON_ECHO_MODE_OFF 0x00000000
-#define IFX_SSC_CON_IDLE_HIGH 0x00800000
-#define IFX_SSC_CON_IDLE_LOW 0x00000000
-#define IFX_SSC_CON_ENABLE_BYTE_VALID 0x00400000
-#define IFX_SSC_CON_DISABLE_BYTE_VALID 0x00000000
-#define IFX_SSC_CON_DATA_WIDTH_OFFSET 16
-#define IFX_SSC_CON_DATA_WIDTH_MASK 0x001F0000
-#define IFX_SSC_ENCODE_DATA_WIDTH(width) (((width - 1) << IFX_SSC_CON_DATA_WIDTH_OFFSET) & IFX_SSC_CON_DATA_WIDTH_MASK)
-
-#define IFX_SSC_CON_RESET_ON_BAUDERR 0x00002000
-#define IFX_SSC_CON_GO_ON_ON_BAUDERR 0x00000000
-
-#define IFX_SSC_CON_RX_UFL_CHECK 0x00001000
-#define IFX_SSC_CON_RX_UFL_IGNORE 0x00000000
-#define IFX_SSC_CON_TX_UFL_CHECK 0x00000800
-#define IFX_SSC_CON_TX_UFL_IGNORE 0x00000000
-#define IFX_SSC_CON_ABORT_ERR_CHECK 0x00000400
-#define IFX_SSC_CON_ABORT_ERR_IGNORE 0x00000000
-#define IFX_SSC_CON_RX_OFL_CHECK 0x00000200
-#define IFX_SSC_CON_RX_OFL_IGNORE 0x00000000
-#define IFX_SSC_CON_TX_OFL_CHECK 0x00000100
-#define IFX_SSC_CON_TX_OFL_IGNORE 0x00000000
-#define IFX_SSC_CON_ALL_ERR_CHECK 0x00001F00
-#define IFX_SSC_CON_ALL_ERR_IGNORE 0x00000000
-
-#define IFX_SSC_CON_LOOPBACK_MODE 0x00000080
-#define IFX_SSC_CON_NO_LOOPBACK 0x00000000
-#define IFX_SSC_CON_HALF_DUPLEX 0x00000080
-#define IFX_SSC_CON_FULL_DUPLEX 0x00000000
-#define IFX_SSC_CON_CLOCK_FALL 0x00000040
-#define IFX_SSC_CON_CLOCK_RISE 0x00000000
-#define IFX_SSC_CON_SHIFT_THEN_LATCH 0x00000000
-#define IFX_SSC_CON_LATCH_THEN_SHIFT 0x00000020
-#define IFX_SSC_CON_MSB_FIRST 0x00000010
-#define IFX_SSC_CON_LSB_FIRST 0x00000000
-#define IFX_SSC_CON_ENABLE_CSB 0x00000008
-#define IFX_SSC_CON_DISABLE_CSB 0x00000000
-#define IFX_SSC_CON_INVERT_CSB 0x00000004
-#define IFX_SSC_CON_TRUE_CSB 0x00000000
-#define IFX_SSC_CON_RX_OFF 0x00000002
-#define IFX_SSC_CON_RX_ON 0x00000000
-#define IFX_SSC_CON_TX_OFF 0x00000001
-#define IFX_SSC_CON_TX_ON 0x00000000
-
-/* IFX_SSC_STATE register */
-#define IFX_SSC_STATE_RX_BYTE_VALID_OFFSET 28
-#define IFX_SSC_STATE_RX_BYTE_VALID_MASK 0x70000000
-#define IFX_SSC_DECODE_RX_BYTE_VALID(con_state) ((con_state & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET)
-#define IFX_SSC_STATE_TX_BYTE_VALID_OFFSET 24
-#define IFX_SSC_STATE_TX_BYTE_VALID_MASK 0x07000000
-#define IFX_SSC_DECODE_TX_BYTE_VALID(con_state) ((con_state & IFX_SSC_STATE_TX_BYTE_VALID_MASK) >> IFX_SSC_STATE_TX_BYTE_VALID_OFFSET)
-#define IFX_SSC_STATE_BIT_COUNT_OFFSET 16
-#define IFX_SSC_STATE_BIT_COUNT_MASK 0x001F0000
-#define IFX_SSC_DECODE_DATA_WIDTH(con_state) (((con_state & IFX_SSC_STATE_BIT_COUNT_MASK) >> IFX_SSC_STATE_BIT_COUNT_OFFSET) + 1)
-#define IFX_SSC_STATE_BUSY 0x00002000
-#define IFX_SSC_STATE_RX_UFL 0x00001000
-#define IFX_SSC_STATE_TX_UFL 0x00000800
-#define IFX_SSC_STATE_ABORT_ERR 0x00000400
-#define IFX_SSC_STATE_RX_OFL 0x00000200
-#define IFX_SSC_STATE_TX_OFL 0x00000100
-#define IFX_SSC_STATE_MODE_ERR 0x00000080
-#define IFX_SSC_STATE_SLAVE_IS_SELECTED 0x00000004
-#define IFX_SSC_STATE_IS_MASTER 0x00000002
-#define IFX_SSC_STATE_IS_ENABLED 0x00000001
-
-/* WHBSTATE register */
-#define IFX_SSC_WHBSTATE_DISABLE_SSC 0x0001
-#define IFX_SSC_WHBSTATE_CONFIGURATION_MODE 0x0001
-#define IFX_SSC_WHBSTATE_CLR_ENABLE 0x0001
-
-#define IFX_SSC_WHBSTATE_ENABLE_SSC 0x0002
-#define IFX_SSC_WHBSTATE_RUN_MODE 0x0002
-#define IFX_SSC_WHBSTATE_SET_ENABLE 0x0002
-
-#define IFX_SSC_WHBSTATE_SLAVE_MODE 0x0004
-#define IFX_SSC_WHBSTATE_CLR_MASTER_SELECT 0x0004
-
-#define IFX_SSC_WHBSTATE_MASTER_MODE 0x0008
-#define IFX_SSC_WHBSTATE_SET_MASTER_SELECT 0x0008
-
-#define IFX_SSC_WHBSTATE_CLR_RX_UFL_ERROR 0x0010
-#define IFX_SSC_WHBSTATE_SET_RX_UFL_ERROR 0x0020
-
-#define IFX_SSC_WHBSTATE_CLR_MODE_ERROR 0x0040
-#define IFX_SSC_WHBSTATE_SET_MODE_ERROR 0x0080
-
-#define IFX_SSC_WHBSTATE_CLR_TX_OFL_ERROR 0x0100
-#define IFX_SSC_WHBSTATE_CLR_RX_OFL_ERROR 0x0200
-#define IFX_SSC_WHBSTATE_CLR_ABORT_ERROR 0x0400
-#define IFX_SSC_WHBSTATE_CLR_TX_UFL_ERROR 0x0800
-#define IFX_SSC_WHBSTATE_SET_TX_OFL_ERROR 0x1000
-#define IFX_SSC_WHBSTATE_SET_RX_OFL_ERROR 0x2000
-#define IFX_SSC_WHBSTATE_SET_ABORT_ERROR 0x4000
-#define IFX_SSC_WHBSTATE_SET_TX_UFL_ERROR 0x8000
-#define IFX_SSC_WHBSTATE_CLR_ALL_ERROR 0x0F50
-#define IFX_SSC_WHBSTATE_SET_ALL_ERROR 0xF0A0
-
-/* BR register */
-#define IFX_SSC_BR_BAUDRATE_OFFSET 0
-#define IFX_SSC_BR_BAUDRATE_MASK 0xFFFF
-
-/* BR_STAT register */
-#define IFX_SSC_BRSTAT_BAUDTIMER_OFFSET 0
-#define IFX_SSC_BRSTAT_BAUDTIMER_MASK 0xFFFF
-
-/* TB register */
-#define IFX_SSC_TB_DATA_OFFSET 0
-#define IFX_SSC_TB_DATA_MASK 0xFFFFFFFF
-
-/* RB register */
-#define IFX_SSC_RB_DATA_OFFSET 0
-#define IFX_SSC_RB_DATA_MASK 0xFFFFFFFF
-
-/* RXFCON and TXFCON registers */
-#define IFX_SSC_XFCON_FIFO_DISABLE 0x0000
-#define IFX_SSC_XFCON_FIFO_ENABLE 0x0001
-#define IFX_SSC_XFCON_FIFO_FLUSH 0x0002
-#define IFX_SSC_XFCON_ITL_MASK 0x00003F00
-#define IFX_SSC_XFCON_ITL_OFFSET 8
-
-/* FSTAT register */
-#define IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET 0
-#define IFX_SSC_FSTAT_RECEIVED_WORDS_MASK 0x003F
-#define IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET 8
-#define IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK 0x3F00
-
-/* GPOCON register */
-#define IFX_SSC_GPOCON_INVOUT0_POS 0
-#define IFX_SSC_GPOCON_INV_OUT0 0x00000001
-#define IFX_SSC_GPOCON_TRUE_OUT0 0x00000000
-#define IFX_SSC_GPOCON_INVOUT1_POS 1
-#define IFX_SSC_GPOCON_INV_OUT1 0x00000002
-#define IFX_SSC_GPOCON_TRUE_OUT1 0x00000000
-#define IFX_SSC_GPOCON_INVOUT2_POS 2
-#define IFX_SSC_GPOCON_INV_OUT2 0x00000003
-#define IFX_SSC_GPOCON_TRUE_OUT2 0x00000000
-#define IFX_SSC_GPOCON_INVOUT3_POS 3
-#define IFX_SSC_GPOCON_INV_OUT3 0x00000008
-#define IFX_SSC_GPOCON_TRUE_OUT3 0x00000000
-#define IFX_SSC_GPOCON_INVOUT4_POS 4
-#define IFX_SSC_GPOCON_INV_OUT4 0x00000010
-#define IFX_SSC_GPOCON_TRUE_OUT4 0x00000000
-#define IFX_SSC_GPOCON_INVOUT5_POS 5
-#define IFX_SSC_GPOCON_INV_OUT5 0x00000020
-#define IFX_SSC_GPOCON_TRUE_OUT5 0x00000000
-#define IFX_SSC_GPOCON_INVOUT6_POS 6
-#define IFX_SSC_GPOCON_INV_OUT6 0x00000040
-#define IFX_SSC_GPOCON_TRUE_OUT6 0x00000000
-#define IFX_SSC_GPOCON_INVOUT7_POS 7
-#define IFX_SSC_GPOCON_INV_OUT7 0x00000080
-#define IFX_SSC_GPOCON_TRUE_OUT7 0x00000000
-#define IFX_SSC_GPOCON_INV_OUT_ALL 0x000000FF
-#define IFX_SSC_GPOCON_TRUE_OUT_ALL 0x00000000
-
-#define IFX_SSC_GPOCON_ISCSB0_POS 8
-#define IFX_SSC_GPOCON_IS_CSB0 0x00000100
-#define IFX_SSC_GPOCON_IS_GPO0 0x00000000
-#define IFX_SSC_GPOCON_ISCSB1_POS 9
-#define IFX_SSC_GPOCON_IS_CSB1 0x00000200
-#define IFX_SSC_GPOCON_IS_GPO1 0x00000000
-#define IFX_SSC_GPOCON_ISCSB2_POS 10
-#define IFX_SSC_GPOCON_IS_CSB2 0x00000400
-#define IFX_SSC_GPOCON_IS_GPO2 0x00000000
-#define IFX_SSC_GPOCON_ISCSB3_POS 11
-#define IFX_SSC_GPOCON_IS_CSB3 0x00000800
-#define IFX_SSC_GPOCON_IS_GPO3 0x00000000
-#define IFX_SSC_GPOCON_ISCSB4_POS 12
-#define IFX_SSC_GPOCON_IS_CSB4 0x00001000
-#define IFX_SSC_GPOCON_IS_GPO4 0x00000000
-#define IFX_SSC_GPOCON_ISCSB5_POS 13
-#define IFX_SSC_GPOCON_IS_CSB5 0x00002000
-#define IFX_SSC_GPOCON_IS_GPO5 0x00000000
-#define IFX_SSC_GPOCON_ISCSB6_POS 14
-#define IFX_SSC_GPOCON_IS_CSB6 0x00004000
-#define IFX_SSC_GPOCON_IS_GPO6 0x00000000
-#define IFX_SSC_GPOCON_ISCSB7_POS 15
-#define IFX_SSC_GPOCON_IS_CSB7 0x00008000
-#define IFX_SSC_GPOCON_IS_GPO7 0x00000000
-#define IFX_SSC_GPOCON_IS_CSB_ALL 0x0000FF00
-#define IFX_SSC_GPOCON_IS_GPO_ALL 0x00000000
-
-/* GPOSTAT register */
-#define IFX_SSC_GPOSTAT_OUT0 0x00000001
-#define IFX_SSC_GPOSTAT_OUT1 0x00000002
-#define IFX_SSC_GPOSTAT_OUT2 0x00000004
-#define IFX_SSC_GPOSTAT_OUT3 0x00000008
-#define IFX_SSC_GPOSTAT_OUT4 0x00000010
-#define IFX_SSC_GPOSTAT_OUT5 0x00000020
-#define IFX_SSC_GPOSTAT_OUT6 0x00000040
-#define IFX_SSC_GPOSTAT_OUT7 0x00000080
-#define IFX_SSC_GPOSTAT_OUT_ALL 0x000000FF
-
-/* WHBGPOSTAT register */
-#define IFX_SSC_WHBGPOSTAT_CLROUT0_POS 0
-#define IFX_SSC_WHBGPOSTAT_CLR_OUT0 0x00000001
-#define IFX_SSC_WHBGPOSTAT_CLROUT1_POS 1
-#define IFX_SSC_WHBGPOSTAT_CLR_OUT1 0x00000002
-#define IFX_SSC_WHBGPOSTAT_CLROUT2_POS 2
-#define IFX_SSC_WHBGPOSTAT_CLR_OUT2 0x00000004
-#define IFX_SSC_WHBGPOSTAT_CLROUT3_POS 3
-#define IFX_SSC_WHBGPOSTAT_CLR_OUT3 0x00000008
-#define IFX_SSC_WHBGPOSTAT_CLROUT4_POS 4
-#define IFX_SSC_WHBGPOSTAT_CLR_OUT4 0x00000010
-#define IFX_SSC_WHBGPOSTAT_CLROUT5_POS 5
-#define IFX_SSC_WHBGPOSTAT_CLR_OUT5 0x00000020
-#define IFX_SSC_WHBGPOSTAT_CLROUT6_POS 6
-#define IFX_SSC_WHBGPOSTAT_CLR_OUT6 0x00000040
-#define IFX_SSC_WHBGPOSTAT_CLROUT7_POS 7
-#define IFX_SSC_WHBGPOSTAT_CLR_OUT7 0x00000080
-#define IFX_SSC_WHBGPOSTAT_CLR_OUT_ALL 0x000000FF
-
-#define IFX_SSC_WHBGPOSTAT_OUT0_POS 0
-#define IFX_SSC_WHBGPOSTAT_OUT1_POS 1
-#define IFX_SSC_WHBGPOSTAT_OUT2_POS 2
-#define IFX_SSC_WHBGPOSTAT_OUT3_POS 3
-#define IFX_SSC_WHBGPOSTAT_OUT4_POS 4
-#define IFX_SSC_WHBGPOSTAT_OUT5_POS 5
-#define IFX_SSC_WHBGPOSTAT_OUT6_POS 6
-#define IFX_SSC_WHBGPOSTAT_OUT7_POS 7
-
-#define IFX_SSC_WHBGPOSTAT_SETOUT0_POS 8
-#define IFX_SSC_WHBGPOSTAT_SET_OUT0 0x00000100
-#define IFX_SSC_WHBGPOSTAT_SETOUT1_POS 9
-#define IFX_SSC_WHBGPOSTAT_SET_OUT1 0x00000200
-#define IFX_SSC_WHBGPOSTAT_SETOUT2_POS 10
-#define IFX_SSC_WHBGPOSTAT_SET_OUT2 0x00000400
-#define IFX_SSC_WHBGPOSTAT_SETOUT3_POS 11
-#define IFX_SSC_WHBGPOSTAT_SET_OUT3 0x00000800
-#define IFX_SSC_WHBGPOSTAT_SETOUT4_POS 12
-#define IFX_SSC_WHBGPOSTAT_SET_OUT4 0x00001000
-#define IFX_SSC_WHBGPOSTAT_SETOUT5_POS 13
-#define IFX_SSC_WHBGPOSTAT_SET_OUT5 0x00002000
-#define IFX_SSC_WHBGPOSTAT_SETOUT6_POS 14
-#define IFX_SSC_WHBGPOSTAT_SET_OUT6 0x00004000
-#define IFX_SSC_WHBGPOSTAT_SETOUT7_POS 15
-#define IFX_SSC_WHBGPOSTAT_SET_OUT7 0x00008000
-#define IFX_SSC_WHBGPOSTAT_SET_OUT_ALL 0x0000FF00
-
-/* SFCON register */
-#define IFX_SSC_SFCON_SF_ENABLE 0x00000001
-#define IFX_SSC_SFCON_SF_DISABLE 0x00000000
-#define IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE 0x00000004
-#define IFX_SSC_SFCON_FIR_DISABLE_BEFORE_PAUSE 0x00000000
-#define IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE 0x00000008
-#define IFX_SSC_SFCON_FIR_DISABLE_AFTER_PAUSE 0x00000000
-#define IFX_SSC_SFCON_DATA_LENGTH_MASK 0x0000FFF0
-#define IFX_SSC_SFCON_DATA_LENGTH_OFFSET 4
-#define IFX_SSC_SFCON_PAUSE_DATA_MASK 0x00030000
-#define IFX_SSC_SFCON_PAUSE_DATA_OFFSET 16
-#define IFX_SSC_SFCON_PAUSE_DATA_0 0x00000000
-#define IFX_SSC_SFCON_PAUSE_DATA_1 0x00010000
-#define IFX_SSC_SFCON_PAUSE_DATA_IDLE 0x00020000
-#define IFX_SSC_SFCON_PAUSE_CLOCK_MASK 0x000C0000
-#define IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET 18
-#define IFX_SSC_SFCON_PAUSE_CLOCK_0 0x00000000
-#define IFX_SSC_SFCON_PAUSE_CLOCK_1 0x00040000
-#define IFX_SSC_SFCON_PAUSE_CLOCK_IDLE 0x00080000
-#define IFX_SSC_SFCON_PAUSE_CLOCK_RUN 0x000C0000
-#define IFX_SSC_SFCON_STOP_AFTER_PAUSE 0x00100000
-#define IFX_SSC_SFCON_CONTINUE_AFTER_PAUSE 0x00000000
-#define IFX_SSC_SFCON_PAUSE_LENGTH_MASK 0xFFC00000
-#define IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET 22
-#define IFX_SSC_SFCON_DATA_LENGTH_MAX 4096
-#define IFX_SSC_SFCON_PAUSE_LENGTH_MAX 1024
-
-#define IFX_SSC_SFCON_EXTRACT_DATA_LENGTH(sfcon) ((sfcon & IFX_SSC_SFCON_DATA_LENGTH_MASK) >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET)
-#define IFX_SSC_SFCON_EXTRACT_PAUSE_LENGTH(sfcon) ((sfcon & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET)
-#define IFX_SSC_SFCON_SET_DATA_LENGTH(value) ((value << IFX_SSC_SFCON_DATA_LENGTH_OFFSET) & IFX_SSC_SFCON_DATA_LENGTH_MASK)
-#define IFX_SSC_SFCON_SET_PAUSE_LENGTH(value) ((value << IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET) & IFX_SSC_SFCON_PAUSE_LENGTH_MASK)
-
-/* SFSTAT register */
-#define IFX_SSC_SFSTAT_IN_DATA 0x00000001
-#define IFX_SSC_SFSTAT_IN_PAUSE 0x00000002
-#define IFX_SSC_SFSTAT_DATA_COUNT_MASK 0x0000FFF0
-#define IFX_SSC_SFSTAT_DATA_COUNT_OFFSET 4
-#define IFX_SSC_SFSTAT_PAUSE_COUNT_MASK 0xFFF00000
-#define IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET 20
-
-#define IFX_SSC_SFSTAT_EXTRACT_DATA_COUNT(sfstat) ((sfstat & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET)
-#define IFX_SSC_SFSTAT_EXTRACT_PAUSE_COUNT(sfstat) ((sfstat & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET)
-
-/* RXREQ register */
-#define IFX_SSC_RXREQ_RXCOUNT_MASK 0x0000FFFF
-#define IFX_SSC_RXREQ_RXCOUNT_OFFSET 0
-
-/* RXCNT register */
-#define IFX_SSC_RXCNT_TODO_MASK 0x0000FFFF
-#define IFX_SSC_RXCNT_TODO_OFFSET 0
-
-/* DMACON register */
-#define IFX_SSC_DMACON_RXON 0x00000001
-#define IFX_SSC_DMACON_RXOFF 0x00000000
-#define IFX_SSC_DMACON_TXON 0x00000002
-#define IFX_SSC_DMACON_TXOFF 0x00000000
-#define IFX_SSC_DMACON_DMAON 0x00000003
-#define IFX_SSC_DMACON_DMAOFF 0x00000000
-#define IFX_SSC_DMACON_CLASS_MASK 0x0000000C
-#define IFX_SSC_DMACON_CLASS_OFFSET 2
-
-/* register access macros */
-#define ifx_ssc_fstat_received_words(status) (status & 0x003F)
-#define ifx_ssc_fstat_words_to_transmit(status) ((status & 0x3F00) >> 8)
-
-#define ifx_ssc_change_status(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_WHBSTATE))
-#define ifx_ssc_set_config(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_CON))
-#define ifx_ssc_get_config(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_CON))
-#define ifx_ssc_get_status(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_STATE))
-#define ifx_ssc_receive(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_RB))
-#define ifx_ssc_transmit(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_TB))
-#define ifx_ssc_fifo_status(addr) READ_PERIPHERAL_REGISTER((PHYS_OFFSET + addr + IFX_SSC_FSTAT))
-#define ifx_ssc_set_baudrate(data, addr) WRITE_PERIPHERAL_REGISTER(data, (PHYS_OFFSET + addr + IFX_SSC_BR))
-
-#define ifx_ssc_extract_rx_fifo_size(id) ((id & IFX_SSC_PERID_RXFS_MASK) >> IFX_SSC_PERID_RXFS_OFFSET)
-#define ifx_ssc_extract_tx_fifo_size(id) ((id & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET)
-
-#endif
+++ /dev/null
-/******************************************************************************
-**
-** FILE NAME : danube_mei.h
-** PROJECT : Danube
-** MODULES : MEI
-**
-** DATE : 1 Jan 2006
-** AUTHOR : TC Chen
-** DESCRIPTION : MEI Driver
-** COPYRIGHT : Copyright (c) 2006
-** Infineon Technologies AG
-** Am Campeon 1-12, 85579 Neubiberg, Germany
-**
-** This program is free software; you can redistribute it and/or modify
-** it under the terms of the GNU General Public License as published by
-** the Free Software Foundation; either version 2 of the License, or
-** (at your option) any later version.
-**
-** HISTORY
-** $Version $Date $Author $Comment
-*******************************************************************************/
-#ifndef _IFXMIPS_MEI_H
-#define _IFXMIPS_MEI_H
-/////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-#include "ifxmips_mei_app.h"
-
-#define IFXMIPS_MEI_DEBUG
-#define IFXMIPS_MEI_CMV_EXTRA
-#define IFXMIPS_MEI_MAJOR 106
-
-/*
-** Define where in ME Processor's memory map the Stratify chip lives
-*/
-
-#define MAXSWAPSIZE 8 * 1024 //8k *(32bits)
-
-// Mailboxes
-#define MSG_LENGTH 16 // x16 bits
-#define YES_REPLY 1
-#define NO_REPLY 0
-
-#define CMV_TIMEOUT 100 //jiffies
-#define MIB_INTERVAL 10000 //msec
-
-/*** Bit definitions ***/
-
-#define FALSE 0
-#define TRUE 1
-#define BIT0 1<<0
-#define BIT1 1<<1
-#define BIT2 1<<2
-#define BIT3 1<<3
-#define BIT4 1<<4
-#define BIT5 1<<5
-#define BIT6 1<<6
-#define BIT7 1<<7
-#define BIT8 1<<8
-#define BIT9 1<<9
-#define BIT10 1<<10
-#define BIT11 1<<11
-#define BIT12 1<<12
-#define BIT13 1<<13
-#define BIT14 1<<14
-#define BIT15 1<<15
-#define BIT16 1<<16
-#define BIT17 1<<17
-#define BIT18 1<<18
-#define BIT19 1<<19
-#define BIT20 1<<20
-#define BIT21 1<<21
-#define BIT22 1<<22
-#define BIT23 1<<23
-#define BIT24 1<<24
-#define BIT25 1<<25
-#define BIT26 1<<26
-#define BIT27 1<<27
-#define BIT28 1<<28
-#define BIT29 1<<29
-#define BIT30 1<<30
-#define BIT31 1<<31
-
-// ARC register addresss
-#define ARC_STATUS 0x0
-#define ARC_LP_START 0x2
-#define ARC_LP_END 0x3
-#define ARC_DEBUG 0x5
-#define ARC_INT_MASK 0x10A
-
-#define IRAM0_BASE (0x00000)
-#define IRAM1_BASE (0x04000)
-#define BRAM_BASE (0x0A000)
-
-#define ADSL_BASE (0x20000)
-#define CRI_BASE (ADSL_BASE + 0x11F00)
-#define CRI_CCR0 (CRI_BASE + 0x00)
-#define CRI_RST (CRI_BASE + 0x04*4)
-#define ADSL_DILV_BASE (ADSL_BASE+0x20000)
-
-//
-#define IRAM0_ADDR_BIT_MASK 0xFFF
-#define IRAM1_ADDR_BIT_MASK 0xFFF
-#define BRAM_ADDR_BIT_MASK 0xFFF
-#define RX_DILV_ADDR_BIT_MASK 0x1FFF
-
-// CRI_CCR0 Register definitions
-#define CLK_2M_MODE_ENABLE BIT6
-#define ACL_CLK_MODE_ENABLE BIT4
-#define FDF_CLK_MODE_ENABLE BIT2
-#define STM_CLK_MODE_ENABLE BIT0
-
-// CRI_RST Register definitions
-#define FDF_SRST BIT3
-#define MTE_SRST BIT2
-#define FCI_SRST BIT1
-#define AAI_SRST BIT0
-
-// MEI_TO_ARC_INTERRUPT Register definitions
-#define MEI_TO_ARC_INT1 BIT3
-#define MEI_TO_ARC_INT0 BIT2
-#define MEI_TO_ARC_CS_DONE BIT1 //need to check
-#define MEI_TO_ARC_MSGAV BIT0
-
-// ARC_TO_MEI_INTERRUPT Register definitions
-#define ARC_TO_MEI_INT1 BIT8
-#define ARC_TO_MEI_INT0 BIT7
-#define ARC_TO_MEI_CS_REQ BIT6
-#define ARC_TO_MEI_DBG_DONE BIT5
-#define ARC_TO_MEI_MSGACK BIT4
-#define ARC_TO_MEI_NO_ACCESS BIT3
-#define ARC_TO_MEI_CHECK_AAITX BIT2
-#define ARC_TO_MEI_CHECK_AAIRX BIT1
-#define ARC_TO_MEI_MSGAV BIT0
-
-// ARC_TO_MEI_INTERRUPT_MASK Register definitions
-#define GP_INT1_EN BIT8
-#define GP_INT0_EN BIT7
-#define CS_REQ_EN BIT6
-#define DBG_DONE_EN BIT5
-#define MSGACK_EN BIT4
-#define NO_ACC_EN BIT3
-#define AAITX_EN BIT2
-#define AAIRX_EN BIT1
-#define MSGAV_EN BIT0
-
-#define MEI_SOFT_RESET BIT0
-
-#define HOST_MSTR BIT0
-
-#define JTAG_MASTER_MODE 0x0
-#define MEI_MASTER_MODE HOST_MSTR
-
-// MEI_DEBUG_DECODE Register definitions
-#define MEI_DEBUG_DEC_MASK (0x3)
-#define MEI_DEBUG_DEC_AUX_MASK (0x0)
-#define MEI_DEBUG_DEC_DMP1_MASK (0x1)
-#define MEI_DEBUG_DEC_DMP2_MASK (0x2)
-#define MEI_DEBUG_DEC_CORE_MASK (0x3)
-
-#define AUX_STATUS (0x0)
-// ARC_TO_MEI_MAILBOX[11] is a special location used to indicate
-// page swap requests.
-#define MEI_TO_ARC_MAILBOX (0xDFD0)
-#define MEI_TO_ARC_MAILBOXR (MEI_TO_ARC_MAILBOX + 0x2C)
-
-#define ARC_TO_MEI_MAILBOX (0xDFA0)
-#define ARC_MEI_MAILBOXR (ARC_TO_MEI_MAILBOX + 0x2C)
-
-// Codeswap request messages are indicated by setting BIT31
-#define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK (0x80000000)
-
-// Clear Eoc messages received are indicated by setting BIT17
-#define OMB_CLEAREOC_INTERRUPT_CODE (0x00020000)
-
-/*
-** Swap page header
-*/
-// Page must be loaded at boot time if size field has BIT31 set
-#define BOOT_FLAG (BIT31)
-#define BOOT_FLAG_MASK ~BOOT_FLAG
-
-#define FREE_RELOAD 1
-#define FREE_SHOWTIME 2
-#define FREE_ALL 3
-
-#define IFX_POP_EOC_DONE 0
-#define IFX_POP_EOC_FAIL -1
-
-#define CLREOC_BUFF_SIZE 12 //number of clreoc commands being buffered
-
-// marcos
-#define IFXMIPS_WRITE_REGISTER_L(data,addr) do{ *((volatile u32*)(addr)) = (u32)(data);} while (0)
-#define IFXMIPS_READ_REGISTER_L(addr) (*((volatile u32*)(addr)))
-#define SET_BIT(reg, mask) reg |= (mask)
-#define CLEAR_BIT(reg, mask) reg &= (~mask)
-#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask)
-#define SET_BITS(reg, mask) SET_BIT(reg, mask)
-#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);}
-
-#define ALIGN_SIZE ( 1L<<10 ) //1K size align
-#define MEM_ALIGN(addr) (((addr) + ALIGN_SIZE - 1) & ~ (ALIGN_SIZE -1) )
-
-// swap marco
-#define MEI_HALF_WORD_SWAP(data) {data = ((data & 0xffff)<<16) + ((data & 0xffff0000)>>16);}
-#define MEI_BYTE_SWAP(data) {data = ((data & 0xff)<<24) + ((data & 0xff00)<<8)+ ((data & 0xff0000)>>8)+ ((data & 0xff000000)>>24);}
-
-// Swap page header describes size in 32-bit words, load location, and image offset
-// for program and/or data segments
-typedef struct _arc_swp_page_hdr {
- u32 p_offset; //Offset bytes of progseg from beginning of image
- u32 p_dest; //Destination addr of progseg on processor
- u32 p_size; //Size in 32-bitwords of program segment
- u32 d_offset; //Offset bytes of dataseg from beginning of image
- u32 d_dest; //Destination addr of dataseg on processor
- u32 d_size; //Size in 32-bitwords of data segment
-} ARC_SWP_PAGE_HDR;
-
-#ifdef CONFIG_PROC_FS
-typedef struct reg_entry {
- int *flag;
- char name[30]; // big enough to hold names
- char description[100]; // big enough to hold description
- unsigned short low_ino;
-} reg_entry_t;
-#endif
-
-/*
-** Swap image header
-*/
-#define GET_PROG 0 // Flag used for program mem segment
-#define GET_DATA 1 // Flag used for data mem segment
-
-// Image header contains size of image, checksum for image, and count of
-// page headers. Following that are 'count' page headers followed by
-// the code and/or data segments to be loaded
-typedef struct _arc_img_hdr {
- u32 size; // Size of binary image in bytes
- u32 checksum; // Checksum for image
- u32 count; // Count of swp pages in image
- ARC_SWP_PAGE_HDR page[1]; // Should be "count" pages - '1' to make compiler happy
-} ARC_IMG_HDR;
-
-typedef struct smmu_mem_info {
- int type;
- unsigned long nCopy;
- unsigned long size;
- unsigned char *address;
- unsigned char *org_address;
-} smmu_mem_info_t;
-
-/*
-** Native size for the Stratiphy interface is 32-bits. All reads and writes
-** MUST be aligned on 32-bit boundaries. Trickery must be invoked to read word and/or
-** byte data. Read routines are provided. Write routines are probably a bad idea, as the
-** Arc has unrestrained, unseen access to the same memory, so a read-modify-write cycle
-** could very well have unintended results.
-*/
-MEI_ERROR meiCMV (u16 *, int, u16 *); // first arg is CMV to ARC, second to indicate whether need reply
-
-MEI_ERROR meiDebugWrite (u32 destaddr, u32 * databuff, u32 databuffsize);
-extern int ifx_mei_hdlc_send (char *hdlc_pkt, int hdlc_pkt_len);
-extern int ifx_mei_hdlc_read (char *hdlc_pkt, int max_hdlc_pkt_len);
-#if defined(__KERNEL__) || defined (IFXMIPS_PORT_RTEMS)
-extern void makeCMV (u8 opcode, u8 group, u16 address, u16 index, int size,
- u16 * data, u16 * CMVMSG);
-int ifx_mei_hdlc_send (char *, int);
-int ifx_mei_hdlc_read (char *, int);
-#endif
-
-#endif
+++ /dev/null
-/******************************************************************************
-**
-** FILE NAME : ifxmips_mei_app.h
-** PROJECT : Danube
-** MODULES : MEI
-**
-** DATE : 1 Jan 2006
-** AUTHOR : TC Chen
-** DESCRIPTION : MEI Driver
-** COPYRIGHT : Copyright (c) 2006
-** Infineon Technologies AG
-** Am Campeon 1-12, 85579 Neubiberg, Germany
-**
-** This program is free software; you can redistribute it and/or modify
-** it under the terms of the GNU General Public License as published by
-** the Free Software Foundation; either version 2 of the License, or
-** (at your option) any later version.
-**
-** HISTORY
-** $Version $Date $Author $Comment
-*******************************************************************************/
-#ifndef _IFXMIPS_MEI_APP_H
-#define _IFXMIPS_MEI_APP_H
- // ioctl control
-#define IFXMIPS_MEI_START 300
-#define IFXMIPS_MEI_REPLY 301
-#define IFXMIPS_MEI_NOREPLY 302
-
-#define IFXMIPS_MEI_RESET 303
-#define IFXMIPS_MEI_REBOOT 304
-#define IFXMIPS_MEI_HALT 305
-#define IFXMIPS_MEI_CMV_WINHOST 306
-#define IFXMIPS_MEI_CMV_READ 307
-#define IFXMIPS_MEI_CMV_WRITE 308
-#define IFXMIPS_MEI_MIB_DAEMON 309
-#define IFXMIPS_MEI_SHOWTIME 310
-#define IFXMIPS_MEI_REMOTE 311
-#define IFXMIPS_MEI_READDEBUG 312
-#define IFXMIPS_MEI_WRITEDEBUG 313
-#define IFXMIPS_MEI_LOP 314
-
-#define IFXMIPS_MEI_PCM_SETUP 315
-#define IFXMIPS_MEI_PCM_START_TIMER 316
-#define IFXMIPS_MEI_PCM_STOP_TIMER 317
-#define IFXMIPS_MEI_PCM_CHECK 318
-#define IFXMIPS_MEI_GET_EOC_LEN 319
-#define IFXMIPS_MEI_GET_EOC_DATA 320
-#define IFXMIPS_MEI_PCM_GETDATA 321
-#define IFXMIPS_MEI_PCM_GPIO 322
-#define IFXMIPS_MEI_EOC_SEND 323
-#define IFXMIPS_MEI_DOWNLOAD 326
-#define IFXMIPS_MEI_JTAG_ENABLE 327
-#define IFXMIPS_MEI_RUN 328
-#define IFXMIPS_MEI_DEBUG_MODE 329
-
-/* Loop diagnostics mode of the ADSL line related constants */
-#define SET_ADSL_LOOP_DIAGNOSTICS_MODE 330
-#define GET_ADSL_LOOP_DIAGNOSTICS_MODE 331
-#define LOOP_DIAGNOSTIC_MODE_COMPLETE 332
-#define IS_ADSL_LOOP_DIAGNOSTICS_MODE_COMPLETE 333
-
-/* L3 Power Mode */
-/* Get current Power Moaagement Mode Status*/
-#define GET_POWER_MANAGEMENT_MODE 334
-/* Set L3 Power Mode /disable L3 power mode */
-#define SET_L3_POWER_MODE 335
-
-/* get current dual latency configuration */
-#define GET_ADSL_DUAL_LATENCY 336
-/* enable/disable dual latency path */
-#define SET_ADSL_DUAL_LATENCY 337
-
-/* Enable/Disable autoboot mode. */
-/* When the autoboot mode is disabled, the driver will excute some cmv
- commands for led control and dual latency when DSL startup.*/
-#define AUTOBOOT_ENABLE_SET 338
-
-/* Enable/Disable Quiet Mode*/
-/* Quiet mode is used for firmware debug. if the quiet mode enable, the autoboot daemon will not reset arc when the arc need to reboot */
-#define QUIET_MODE_GET 339
-#define QUIET_MODE_SET 340
-
-/* Enable/Disable showtime lock*/
-/* showtime lock is used for firmware debug. if the showtime lock enable, the autoboot daemon will not reset arc when the arc reach showtime and need to reboot */
-#define SHOWTIME_LOCK_GET 341
-#define SHOWTIME_LOCK_SET 342
-
-#define L0_POWER_MODE 0
-#define L2_POWER_MODE 2
-#define L3_POWER_MODE 3
-
-#define DUAL_LATENCY_US_DS_DISABLE 0
-#define DUAL_LATENCY_US_ENABLE (1<<0)
-#define DUAL_LATENCY_DS_ENABLE (1<<1)
-#define DUAL_LATENCY_US_DS_ENABLE (DUAL_LATENCY_US_ENABLE|DUAL_LATENCY_DS_ENABLE)
-
-#define ME_HDLC_IDLE 0
-#define ME_HDLC_INVALID_MSG 1
-#define ME_HDLC_MSG_QUEUED 2
-#define ME_HDLC_MSG_SENT 3
-#define ME_HDLC_RESP_RCVD 4
-#define ME_HDLC_RESP_TIMEOUT 5
-#define ME_HDLC_RX_BUF_OVERFLOW 6
-#define ME_HDLC_UNRESOLVED 1
-#define ME_HDLC_RESOLVED 2
-
-/*** Enums ***/
-typedef enum mei_error {
- MEI_SUCCESS = 0,
- MEI_FAILURE = -1,
- MEI_MAILBOX_FULL = -2,
- MEI_MAILBOX_EMPTY = -3,
- MEI_MAILBOX_TIMEOUT = -4,
-} MEI_ERROR;
-
-#endif
+++ /dev/null
-/******************************************************************************
-**
-** FILE NAME : ifxmips_mei_app_ioctl.h
-** PROJECT : Danube
-** MODULES : MEI
-**
-** DATE : 1 Jan 2006
-** AUTHOR : TC Chen
-** DESCRIPTION : MEI Driver
-** COPYRIGHT : Copyright (c) 2006
-** Infineon Technologies AG
-** Am Campeon 1-12, 85579 Neubiberg, Germany
-**
-** This program is free software; you can redistribute it and/or modify
-** it under the terms of the GNU General Public License as published by
-** the Free Software Foundation; either version 2 of the License, or
-** (at your option) any later version.
-**
-** HISTORY
-** $Version $Date $Author $Comment
-*******************************************************************************/
-#ifndef __IFXMIPS_MEI_APP_IOCTL_H
-#define __IFXMIPS_MEI_APP_IOCTL_H
-
-#ifdef __KERNEL__
-#include "ifxmips_mei_ioctl.h"
-#endif
-
-/* Interface Name */
-//#define INTERFACE_NAME <define the interface>
-
-/* adslLineTable constants */
-#define GET_ADSL_LINE_CODE 1
-
-/* adslAtucPhysTable constants */
-#define GET_ADSL_ATUC_PHY 4
-
-/* adslAturPhysTable constants */
-#define GET_ADSL_ATUR_PHY 10
-
-/* adslAtucChanTable constants */
-#define GET_ADSL_ATUC_CHAN_INFO 15
-
-/* adslAturChanTable constants */
-#define GET_ADSL_ATUR_CHAN_INFO 18
-
-/* adslAtucPerfDataTable constants */
-#define GET_ADSL_ATUC_PERF_DATA 21
-
-/* adslAturPerfDataTable constants */
-#define GET_ADSL_ATUR_PERF_DATA 40
-
-/* adslAtucIntervalTable constants */
-#define GET_ADSL_ATUC_INTVL_INFO 60
-
-/* adslAturIntervalTable constants */
-#define GET_ADSL_ATUR_INTVL_INFO 65
-
-/* adslAtucChanPerfDataTable constants */
-#define GET_ADSL_ATUC_CHAN_PERF_DATA 70
-
-/* adslAturChanPerfDataTable constants */
-#define GET_ADSL_ATUR_CHAN_PERF_DATA 90
-
-/* adslAtucChanIntervalTable constants */
-#define GET_ADSL_ATUC_CHAN_INTVL_INFO 110
-
-/* adslAturChanIntervalTable constants */
-#define GET_ADSL_ATUR_CHAN_INTVL_INFO 115
-
-/* adslLineAlarmConfProfileTable constants */
-#define GET_ADSL_ALRM_CONF_PROF 120
-#define SET_ADSL_ALRM_CONF_PROF 121
-
-/* adslAturTrap constants */
-#define ADSL_ATUR_TRAPS 135
-
-////////////////// RFC-3440 //////////////
-
-#ifdef IFXMIPS_MEI_MIB_RFC3440
-/* adslLineExtTable */
-#define GET_ADSL_ATUC_LINE_EXT 201
-#define SET_ADSL_ATUC_LINE_EXT 203
-
-/* adslAtucPerfDateExtTable */
-#define GET_ADSL_ATUC_PERF_DATA_EXT 205
-
-/* adslAtucIntervalExtTable */
-#define GET_ADSL_ATUC_INTVL_EXT_INFO 221
-
-/* adslAturPerfDataExtTable */
-#define GET_ADSL_ATUR_PERF_DATA_EXT 225
-
-/* adslAturIntervalExtTable */
-#define GET_ADSL_ATUR_INTVL_EXT_INFO 233
-
-/* adslAlarmConfProfileExtTable */
-#define GET_ADSL_ALRM_CONF_PROF_EXT 235
-#define SET_ADSL_ALRM_CONF_PROF_EXT 236
-
-/* adslAturExtTrap */
-#define ADSL_ATUR_EXT_TRAPS 240
-
-#endif
-
-/* The following constants are added to support the WEB related ADSL Statistics */
-
-/* adslLineStatus constants */
-#define GET_ADSL_LINE_STATUS 245
-
-/* adslLineRate constants */
-#define GET_ADSL_LINE_RATE 250
-
-/* adslLineInformation constants */
-#define GET_ADSL_LINE_INFO 255
-
-/* adslNearEndPerformanceStats constants */
-#define GET_ADSL_NEAREND_STATS 270
-
-/* adslFarEndPerformanceStats constants */
-#define GET_ADSL_FAREND_STATS 290
-
-/* Sub-carrier related parameters */
-#define GET_ADSL_LINE_INIT_STATS 150
-#define GET_ADSL_POWER_SPECTRAL_DENSITY 151
-
-#define IFXMIPS_MIB_LO_ATUC 295
-#define IFXMIPS_MIB_LO_ATUR 296
-
-#define GET_ADSL_ATUC_SUBCARRIER_STATS 297
-#define GET_ADSL_ATUR_SUBCARRIER_STATS 298
-
-
-
-///////////////////////////////////////////////////////////
-// makeCMV(Opcode, Group, Address, Index, Size, Data)
-
-/* adslLineCode Flags */
-#define LINE_CODE_FLAG 0x1 /* BIT 0th position */
-
-/* adslAtucPhysTable Flags */
-#define ATUC_PHY_SER_NUM_FLAG 0x1 /* BIT 0th position */
-#define ATUC_PHY_SER_NUM_FLAG_MAKECMV1 makeCMV(H2D_CMV_READ, INFO, 57, 0, 12, data,TxMessage)
-#define ATUC_PHY_SER_NUM_FLAG_MAKECMV2 makeCMV(H2D_CMV_READ, INFO, 57, 12, 4, data,TxMessage)
-
-#define ATUC_PHY_VENDOR_ID_FLAG 0x2 /* BIT 1 */
-#define ATUC_PHY_VENDOR_ID_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 64, 0, 4, data,TxMessage)
-
-#define ATUC_PHY_VER_NUM_FLAG 0x4 /* BIT 2 */
-#define ATUC_PHY_VER_NUM_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 58, 0, 8, data,TxMessage)
-
-#define ATUC_CURR_STAT_FLAG 0x8 /* BIT 3 */
-
-#define ATUC_CURR_OUT_PWR_FLAG 0x10 /* BIT 4 */
-#define ATUC_CURR_OUT_PWR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 5, 1, data,TxMessage)
-
-#define ATUC_CURR_ATTR_FLAG 0x20 /* BIT 5 */
-#define ATUC_CURR_ATTR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 0, 2, data,TxMessage)
-
-
-/* adslAturPhysTable Flags */
-#define ATUR_PHY_SER_NUM_FLAG 0x1 /* BIT 0th position */
-#define ATUR_PHY_SER_NUM_FLAG_MAKECMV1 makeCMV(H2D_CMV_READ, INFO, 62, 0, 12, data,TxMessage)
-#define ATUR_PHY_SER_NUM_FLAG_MAKECMV2 makeCMV(H2D_CMV_READ, INFO, 62, 12, 4, data,TxMessage)
-
-#define ATUR_PHY_VENDOR_ID_FLAG 0x2 /* BIT 1 */
-#define ATUR_PHY_VENDOR_ID_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 65, 0, 4, data,TxMessage)
-
-#define ATUR_PHY_VER_NUM_FLAG 0x4 /* BIT 2 */
-#define ATUR_PHY_VER_NUM_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 61, 0, 8, data,TxMessage)
-
-#define ATUR_SNRMGN_FLAG 0x8
-#if 0 /* [ Ritesh. Use PLAM 45 0 for 0.1dB resolution rather than INFO 68 3 */
-#define ATUR_SNRMGN_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 4, 1, data,TxMessage)
-#else
-#define ATUR_SNRMGN_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, PLAM_SNRMargin_0_1db, 0, 1, data, TxMessage)
-#endif
-
-#define ATUR_ATTN_FLAG 0x10
-#define ATUR_ATTN_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 2, 1, data,TxMessage)
-
-#define ATUR_CURR_STAT_FLAG 0x20 /* BIT 3 */
-
-#define ATUR_CURR_OUT_PWR_FLAG 0x40 /* BIT 4 */
-#define ATUR_CURR_OUT_PWR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 5, 1, data,TxMessage)
-
-#define ATUR_CURR_ATTR_FLAG 0x80 /* BIT 5 */
-#define ATUR_CURR_ATTR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 0, 2, data,TxMessage)
-
-/* adslAtucChanTable Flags */
-#define ATUC_CHAN_INTLV_DELAY_FLAG 0x1 /* BIT 0th position */
-//KD #define ATUC_CHAN_INTLV_DELAY_FLAG_MAKECMV makeCMV(H2D_CMV_READ, RATE, 3, 1, 1, data,TxMessage)
-#define ATUC_CHAN_INTLV_DELAY_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 92, 1, 1, data,TxMessage)
-
-#define ATUC_CHAN_CURR_TX_RATE_FLAG 0x2 /* BIT 1 */
-#define ATUC_CHAN_CURR_TX_RATE_FLAG_MAKECMV makeCMV(H2D_CMV_READ, RATE, 1, 0, 2, data,TxMessage)
-
-#define ATUC_CHAN_PREV_TX_RATE_FLAG 0x4 /* BIT 2 */
-
-/* adslAturChanTable Flags */
-#define ATUR_CHAN_INTLV_DELAY_FLAG 0x1 /* BIT 0th position */
-//KD #define ATUR_CHAN_INTLV_DELAY_FLAG_MAKECMV makeCMV(H2D_CMV_READ, RATE, 2, 1, 1, data,TxMessage)
-#define ATUR_CHAN_INTLV_DELAY_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 93, 1, 1, data,TxMessage)
-
-#define ATUR_CHAN_CURR_TX_RATE_FLAG 0x2 /* BIT 1 */
-#define ATUR_CHAN_CURR_TX_RATE_FLAG_MAKECMV makeCMV(H2D_CMV_READ, RATE, 0, 0, 2, data,TxMessage)
-
-#define ATUR_CHAN_PREV_TX_RATE_FLAG 0x4 /* BIT 2 */
-
-#define ATUR_CHAN_CRC_BLK_LEN_FLAG 0x8 /* BIT 3 */
-
-/* adslAtucPerfDataTable Flags */
-#define ATUC_PERF_LOFS_FLAG 0x1 /* BIT 0th position */
-#define ATUC_PERF_LOSS_FLAG 0x2 /* BIT 1 */
-#define ATUC_PERF_LO_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 0, 0, 1, data,TxMessage)
-#define ATUC_PERF_ESS_FLAG 0x4 /* BIT 2 */
-#define ATUC_PERF_ESS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 7, 0, 1, data,TxMessage)
-#define ATUC_PERF_INITS_FLAG 0x8 /* BIT 3 */
-#define ATUC_PERF_VALID_INTVLS_FLAG 0x10 /* BIT 4 */
-#define ATUC_PERF_INVALID_INTVLS_FLAG 0x20 /* BIT 5 */
-#define ATUC_PERF_CURR_15MIN_TIME_ELAPSED_FLAG 0x40 /* BIT 6 */
-#define ATUC_PERF_CURR_15MIN_LOFS_FLAG 0x80 /* BIT 7 */
-#define ATUC_PERF_CURR_15MIN_LOSS_FLAG 0x100 /* BIT 8 */
-#define ATUC_PERF_CURR_15MIN_ESS_FLAG 0x200 /* BIT 9 */
-#define ATUC_PERF_CURR_15MIN_INIT_FLAG 0x400 /* BIT 10 */
-#define ATUC_PERF_CURR_1DAY_TIME_ELAPSED_FLAG 0x800 /* BIT 11 */
-#define ATUC_PERF_CURR_1DAY_LOFS_FLAG 0x1000 /* BIT 12 */
-#define ATUC_PERF_CURR_1DAY_LOSS_FLAG 0x2000 /* BIT 13 */
-#define ATUC_PERF_CURR_1DAY_ESS_FLAG 0x4000 /* BIT 14 */
-#define ATUC_PERF_CURR_1DAY_INIT_FLAG 0x8000 /* BIT 15 */
-#define ATUC_PERF_PREV_1DAY_MON_SEC_FLAG 0x10000 /* BIT 16 */
-#define ATUC_PERF_PREV_1DAY_LOFS_FLAG 0x20000 /* BIT 17 */
-#define ATUC_PERF_PREV_1DAY_LOSS_FLAG 0x40000 /* BIT 18 */
-#define ATUC_PERF_PREV_1DAY_ESS_FLAG 0x80000 /* BIT 19 */
-#define ATUC_PERF_PREV_1DAY_INITS_FLAG 0x100000 /* BIT 20 */
-
-/* adslAturPerfDataTable Flags */
-#define ATUR_PERF_LOFS_FLAG 0x1 /* BIT 0th position */
-#define ATUR_PERF_LOSS_FLAG 0x2 /* BIT 1 */
-#define ATUR_PERF_LPR_FLAG 0x4 /* BIT 2 */
-#define ATUR_PERF_LO_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 1, 0, 1, data,TxMessage)
-#define ATUR_PERF_ESS_FLAG 0x8 /* BIT 3 */
-#define ATUR_PERF_ESS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 33, 0, 1, data,TxMessage)
-#define ATUR_PERF_VALID_INTVLS_FLAG 0x10 /* BIT 4 */
-#define ATUR_PERF_INVALID_INTVLS_FLAG 0x20 /* BIT 5 */
-#define ATUR_PERF_CURR_15MIN_TIME_ELAPSED_FLAG 0x40 /* BIT 6 */
-#define ATUR_PERF_CURR_15MIN_LOFS_FLAG 0x80 /* BIT 7 */
-#define ATUR_PERF_CURR_15MIN_LOSS_FLAG 0x100 /* BIT 8 */
-#define ATUR_PERF_CURR_15MIN_LPR_FLAG 0x200 /* BIT 9 */
-#define ATUR_PERF_CURR_15MIN_ESS_FLAG 0x400 /* BIT 10 */
-#define ATUR_PERF_CURR_1DAY_TIME_ELAPSED_FLAG 0x800 /* BIT 11 */
-#define ATUR_PERF_CURR_1DAY_LOFS_FLAG 0x1000 /* BIT 12 */
-#define ATUR_PERF_CURR_1DAY_LOSS_FLAG 0x2000 /* BIT 13 */
-#define ATUR_PERF_CURR_1DAY_LPR_FLAG 0x4000 /* BIT 14 */
-#define ATUR_PERF_CURR_1DAY_ESS_FLAG 0x8000 /* BIT 15 */
-#define ATUR_PERF_PREV_1DAY_MON_SEC_FLAG 0x10000 /* BIT 16 */
-#define ATUR_PERF_PREV_1DAY_LOFS_FLAG 0x20000 /* BIT 17 */
-#define ATUR_PERF_PREV_1DAY_LOSS_FLAG 0x40000 /* BIT 18 */
-#define ATUR_PERF_PREV_1DAY_LPR_FLAG 0x80000 /* BIT 19 */
-#define ATUR_PERF_PREV_1DAY_ESS_FLAG 0x100000 /* BIT 20 */
-
-/* adslAtucIntervalTable Flags */
-#define ATUC_INTVL_LOF_FLAG 0x1 /* BIT 0th position */
-#define ATUC_INTVL_LOS_FLAG 0x2 /* BIT 1 */
-#define ATUC_INTVL_ESS_FLAG 0x4 /* BIT 2 */
-#define ATUC_INTVL_INIT_FLAG 0x8 /* BIT 3 */
-#define ATUC_INTVL_VALID_DATA_FLAG 0x10 /* BIT 4 */
-
-/* adslAturIntervalTable Flags */
-#define ATUR_INTVL_LOF_FLAG 0x1 /* BIT 0th position */
-#define ATUR_INTVL_LOS_FLAG 0x2 /* BIT 1 */
-#define ATUR_INTVL_LPR_FLAG 0x4 /* BIT 2 */
-#define ATUR_INTVL_ESS_FLAG 0x8 /* BIT 3 */
-#define ATUR_INTVL_VALID_DATA_FLAG 0x10 /* BIT 4 */
-
-/* adslAtucChanPerfDataTable Flags */
-#define ATUC_CHAN_RECV_BLK_FLAG 0x01 /* BIT 0th position */
-#define ATUC_CHAN_TX_BLK_FLAG 0x02 /* BIT 1 */
-#define ATUC_CHAN_CORR_BLK_FLAG 0x04 /* BIT 2 */
-#define ATUC_CHAN_UNCORR_BLK_FLAG 0x08 /* BIT 3 */
-#define ATUC_CHAN_PERF_VALID_INTVL_FLAG 0x10 /* BIT 4 */
-#define ATUC_CHAN_PERF_INVALID_INTVL_FLAG 0x20 /* BIT 5 */
-#define ATUC_CHAN_PERF_CURR_15MIN_TIME_ELAPSED_FLAG 0x40 /* BIT 6 */
-#define ATUC_CHAN_PERF_CURR_15MIN_RECV_BLK_FLAG 0x80 /* BIT 7 */
-#define ATUC_CHAN_PERF_CURR_15MIN_TX_BLK_FLAG 0x100 /* BIT 8 */
-#define ATUC_CHAN_PERF_CURR_15MIN_CORR_BLK_FLAG 0x200 /* BIT 9 */
-#define ATUC_CHAN_PERF_CURR_15MIN_UNCORR_BLK_FLAG 0x400 /* BIT 10 */
-#define ATUC_CHAN_PERF_CURR_1DAY_TIME_ELAPSED_FLAG 0x800 /* BIT 11*/
-#define ATUC_CHAN_PERF_CURR_1DAY_RECV_BLK_FLAG 0x1000 /* BIT 12 */
-#define ATUC_CHAN_PERF_CURR_1DAY_TX_BLK_FLAG 0x2000 /* BIT 13 */
-#define ATUC_CHAN_PERF_CURR_1DAY_CORR_BLK_FLAG 0x4000 /* BIT 14 */
-#define ATUC_CHAN_PERF_CURR_1DAY_UNCORR_BLK_FLAG 0x8000 /* BIT 15 */
-#define ATUC_CHAN_PERF_PREV_1DAY_MONI_SEC_FLAG 0x10000 /* BIT 16 */
-#define ATUC_CHAN_PERF_PREV_1DAY_RECV_BLK_FLAG 0x20000 /* BIT 17 */
-#define ATUC_CHAN_PERF_PREV_1DAY_TX_BLK_FLAG 0x40000 /* BIT 18 */
-#define ATUC_CHAN_PERF_PREV_1DAY_CORR_BLK_FLAG 0x80000 /* BIT 19 */
-#define ATUC_CHAN_PERF_PREV_1DAY_UNCORR_BLK_FLAG 0x100000 /* BIT 20 */
-
-
-/* adslAturChanPerfDataTable Flags */
-#define ATUR_CHAN_RECV_BLK_FLAG 0x01 /* BIT 0th position */
-#define ATUR_CHAN_RECV_BLK_FLAG_MAKECMV_LSW makeCMV(H2D_CMV_READ, PLAM, 20, 0, 1, data,TxMessage)
-#define ATUR_CHAN_RECV_BLK_FLAG_MAKECMV_MSW makeCMV(H2D_CMV_READ, PLAM, 21, 0, 1, data,TxMessage)
-#define ATUR_CHAN_TX_BLK_FLAG 0x02 /* BIT 1 */
-#define ATUR_CHAN_TX_BLK_FLAG_MAKECMV_LSW makeCMV(H2D_CMV_READ, PLAM, 20, 0, 1, data,TxMessage)
-#define ATUR_CHAN_TX_BLK_FLAG_MAKECMV_MSW makeCMV(H2D_CMV_READ, PLAM, 21, 0, 1, data,TxMessage)
-#define ATUR_CHAN_CORR_BLK_FLAG 0x04 /* BIT 2 */
-#define ATUR_CHAN_CORR_BLK_FLAG_MAKECMV_INTL makeCMV(H2D_CMV_READ, PLAM, 3, 0, 1, data,TxMessage)
-#define ATUR_CHAN_CORR_BLK_FLAG_MAKECMV_FAST makeCMV(H2D_CMV_READ, PLAM, 3, 1, 1, data,TxMessage)
-#define ATUR_CHAN_UNCORR_BLK_FLAG 0x08 /* BIT 3 */
-#define ATUR_CHAN_UNCORR_BLK_FLAG_MAKECMV_INTL makeCMV(H2D_CMV_READ, PLAM, 2, 0, 1, data,TxMessage)
-#define ATUR_CHAN_UNCORR_BLK_FLAG_MAKECMV_FAST makeCMV(H2D_CMV_READ, PLAM, 2, 1, 1, data,TxMessage)
-#define ATUR_CHAN_PERF_VALID_INTVL_FLAG 0x10 /* BIT 4 */
-#define ATUR_CHAN_PERF_INVALID_INTVL_FLAG 0x20 /* BIT 5 */
-#define ATUR_CHAN_PERF_CURR_15MIN_TIME_ELAPSED_FLAG 0x40 /* BIT 6 */
-#define ATUR_CHAN_PERF_CURR_15MIN_RECV_BLK_FLAG 0x80 /* BIT 7 */
-#define ATUR_CHAN_PERF_CURR_15MIN_TX_BLK_FLAG 0x100 /* BIT 8 */
-#define ATUR_CHAN_PERF_CURR_15MIN_CORR_BLK_FLAG 0x200 /* BIT 9 */
-#define ATUR_CHAN_PERF_CURR_15MIN_UNCORR_BLK_FLAG 0x400 /* BIT 10 */
-#define ATUR_CHAN_PERF_CURR_1DAY_TIME_ELAPSED_FLAG 0x800 /* BIT 11 */
-#define ATUR_CHAN_PERF_CURR_1DAY_RECV_BLK_FLAG 0x1000 /* BIT 12 */
-#define ATUR_CHAN_PERF_CURR_1DAY_TX_BLK_FLAG 0x2000 /* BIT 13 */
-#define ATUR_CHAN_PERF_CURR_1DAY_CORR_BLK_FLAG 0x4000 /* BIT 14 */
-#define ATUR_CHAN_PERF_CURR_1DAY_UNCORR_BLK_FLAG 0x8000 /* BIT 15 */
-#define ATUR_CHAN_PERF_PREV_1DAY_MONI_SEC_FLAG 0x10000 /* BIT 16 */
-#define ATUR_CHAN_PERF_PREV_1DAY_RECV_BLK_FLAG 0x20000 /* BIT 17 */
-#define ATUR_CHAN_PERF_PREV_1DAY_TRANS_BLK_FLAG 0x40000 /* BIT 18 */
-#define ATUR_CHAN_PERF_PREV_1DAY_CORR_BLK_FLAG 0x80000 /* BIT 19 */
-#define ATUR_CHAN_PERF_PREV_1DAY_UNCORR_BLK_FLAG 0x100000 /* BIT 20 */
-
-/* adslAtucChanIntervalTable Flags */
-#define ATUC_CHAN_INTVL_NUM_FLAG 0x1 /* BIT 0th position */
-#define ATUC_CHAN_INTVL_RECV_BLK_FLAG 0x2 /* BIT 1 */
-#define ATUC_CHAN_INTVL_TX_BLK_FLAG 0x4 /* BIT 2 */
-#define ATUC_CHAN_INTVL_CORR_BLK_FLAG 0x8 /* BIT 3 */
-#define ATUC_CHAN_INTVL_UNCORR_BLK_FLAG 0x10 /* BIT 4 */
-#define ATUC_CHAN_INTVL_VALID_DATA_FLAG 0x20 /* BIT 5 */
-
-/* adslAturChanIntervalTable Flags */
-#define ATUR_CHAN_INTVL_NUM_FLAG 0x1 /* BIT 0th Position */
-#define ATUR_CHAN_INTVL_RECV_BLK_FLAG 0x2 /* BIT 1 */
-#define ATUR_CHAN_INTVL_TX_BLK_FLAG 0x4 /* BIT 2 */
-#define ATUR_CHAN_INTVL_CORR_BLK_FLAG 0x8 /* BIT 3 */
-#define ATUR_CHAN_INTVL_UNCORR_BLK_FLAG 0x10 /* BIT 4 */
-#define ATUR_CHAN_INTVL_VALID_DATA_FLAG 0x20 /* BIT 5 */
-
-/* adslLineAlarmConfProfileTable Flags */
-#define ATUC_THRESH_15MIN_LOFS_FLAG 0x01 /* BIT 0th position */
-#define ATUC_THRESH_15MIN_LOSS_FLAG 0x02 /* BIT 1 */
-#define ATUC_THRESH_15MIN_ESS_FLAG 0x04 /* BIT 2 */
-#define ATUC_THRESH_FAST_RATEUP_FLAG 0x08 /* BIT 3 */
-#define ATUC_THRESH_INTERLEAVE_RATEUP_FLAG 0x10 /* BIT 4 */
-#define ATUC_THRESH_FAST_RATEDOWN_FLAG 0x20 /* BIT 5 */
-#define ATUC_THRESH_INTERLEAVE_RATEDOWN_FLAG 0x40 /* BIT 6 */
-#define ATUC_INIT_FAILURE_TRAP_ENABLE_FLAG 0x80 /* BIT 7 */
-#define ATUR_THRESH_15MIN_LOFS_FLAG 0x100 /* BIT 8 */
-#define ATUR_THRESH_15MIN_LOSS_FLAG 0x200 /* BIT 9 */
-#define ATUR_THRESH_15MIN_LPRS_FLAG 0x400 /* BIT 10 */
-#define ATUR_THRESH_15MIN_ESS_FLAG 0x800 /* BIT 11 */
-#define ATUR_THRESH_FAST_RATEUP_FLAG 0x1000 /* BIT 12 */
-#define ATUR_THRESH_INTERLEAVE_RATEUP_FLAG 0x2000 /* BIT 13 */
-#define ATUR_THRESH_FAST_RATEDOWN_FLAG 0x4000 /* BIT 14 */
-#define ATUR_THRESH_INTERLEAVE_RATEDOWN_FLAG 0x8000 /* BIT 15 */
-#define LINE_ALARM_CONF_PROFILE_ROWSTATUS_FLAG 0x10000 /* BIT 16 */
-
-
-/* adslAturTraps Flags */
-#define ATUC_PERF_LOFS_THRESH_FLAG 0x1 /* BIT 0th position */
-#define ATUC_PERF_LOSS_THRESH_FLAG 0x2 /* BIT 1 */
-#define ATUC_PERF_ESS_THRESH_FLAG 0x4 /* BIT 2 */
-#define ATUC_RATE_CHANGE_FLAG 0x8 /* BIT 3 */
-#define ATUR_PERF_LOFS_THRESH_FLAG 0x10 /* BIT 4 */
-#define ATUR_PERF_LOSS_THRESH_FLAG 0x20 /* BIT 5 */
-#define ATUR_PERF_LPRS_THRESH_FLAG 0x40 /* BIT 6 */
-#define ATUR_PERF_ESS_THRESH_FLAG 0x80 /* BIT 7 */
-#define ATUR_RATE_CHANGE_FLAG 0x100 /* BIT 8 */
-
-//RFC- 3440 FLAG DEFINITIONS
-
-#ifdef IFXMIPS_MEI_MIB_RFC3440
-/* adslLineExtTable flags */
-#define ATUC_LINE_TRANS_CAP_FLAG 0x1 /* BIT 0th position */
-#define ATUC_LINE_TRANS_CAP_FLAG_MAKECMV makeCMV(H2D_CMV_READ,INFO, 67, 0, 1, data,TxMessage)
-#define ATUC_LINE_TRANS_CONFIG_FLAG 0x2 /* BIT 1 */
-#define ATUC_LINE_TRANS_CONFIG_FLAG_MAKECMV makeCMV(H2D_CMV_READ,INFO, 67, 0, 1, data,TxMessage)
-#define ATUC_LINE_TRANS_CONFIG_FLAG_MAKECMV_WR makeCMV(H2D_CMV_WRITE,INFO, 67, 0, 1, data,TxMessage)
-#define ATUC_LINE_TRANS_ACTUAL_FLAG 0x4 /* BIT 2 */
-#define ATUC_LINE_TRANS_ACTUAL_FLAG_MAKECMV makeCMV(H2D_CMV_READ,STAT, 1, 0, 1, data,TxMessage)
-#define LINE_GLITE_POWER_STATE_FLAG 0x8 /* BIT 3 */
-#define LINE_GLITE_POWER_STATE_FLAG_MAKECMV makeCMV(H2D_CMV_READ,STAT, 0, 0, 1, data,TxMessage)
-
-/* adslAtucPerfDataExtTable flags */
-#define ATUC_PERF_STAT_FASTR_FLAG 0x1 /* BIT 0th position */
-#define ATUC_PERF_STAT_FASTR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 0, 0, 1, data, TxMessage)
-#define ATUC_PERF_STAT_FAILED_FASTR_FLAG 0x2 /* BIT 1 */
-#define ATUC_PERF_STAT_FAILED_FASTR_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 0, 0, 1, data, TxMessage)
-#define ATUC_PERF_STAT_SESL_FLAG 0X4 /* BIT 2 */
-#define ATUC_PERF_STAT_SESL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 8, 0, 1, data, TxMessage)
-#define ATUC_PERF_STAT_UASL_FLAG 0X8 /* BIT 3 */
-#define ATUC_PERF_STAT_UASL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 10, 0, 1, data, TxMessage)
-#define ATUC_PERF_CURR_15MIN_FASTR_FLAG 0X10 /* BIT 4 */
-#define ATUC_PERF_CURR_15MIN_FAILED_FASTR_FLAG 0X20 /* BIT 5 */
-#define ATUC_PERF_CURR_15MIN_SESL_FLAG 0X40 /* BIT 6 */
-#define ATUC_PERF_CURR_15MIN_UASL_FLAG 0X80 /* BIT 7 */
-#define ATUC_PERF_CURR_1DAY_FASTR_FLAG 0X100 /* BIT 8 */
-#define ATUC_PERF_CURR_1DAY_FAILED_FASTR_FLAG 0X200 /* BIT 9 */
-#define ATUC_PERF_CURR_1DAY_SESL_FLAG 0X400 /* BIT 10 */
-#define ATUC_PERF_CURR_1DAY_UASL_FLAG 0X800 /* BIT 11 */
-#define ATUC_PERF_PREV_1DAY_FASTR_FLAG 0X1000 /* BIT 12 */
-#define ATUC_PERF_PREV_1DAY_FAILED_FASTR_FLAG 0X2000 /* BIT 13 */
-#define ATUC_PERF_PREV_1DAY_SESL_FLAG 0X4000 /* BIT 14 */
-#define ATUC_PERF_PREV_1DAY_UASL_FLAG 0X8000 /* BIT 15 */
-
-/* adslAturPerfDataExtTable */
-#define ATUR_PERF_STAT_SESL_FLAG 0X1 /* BIT 0th position */
-#define ATUR_PERF_STAT_SESL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 34, 0, 1, data, TxMessage)
-#define ATUR_PERF_STAT_UASL_FLAG 0X2 /* BIT 1 */
-#define ATUR_PERF_STAT_UASL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 36, 0, 1, data, TxMessage)
-#define ATUR_PERF_CURR_15MIN_SESL_FLAG 0X4 /* BIT 2 */
-#define ATUR_PERF_CURR_15MIN_UASL_FLAG 0X8 /* BIT 3 */
-#define ATUR_PERF_CURR_1DAY_SESL_FLAG 0X10 /* BIT 4 */
-#define ATUR_PERF_CURR_1DAY_UASL_FLAG 0X20 /* BIT 5 */
-#define ATUR_PERF_PREV_1DAY_SESL_FLAG 0X40 /* BIT 6 */
-#define ATUR_PERF_PREV_1DAY_UASL_FLAG 0X80 /* BIT 7 */
-
-/* adslAutcIntervalExtTable flags */
-#define ATUC_INTERVAL_FASTR_FLAG 0x1 /* Bit 0 */
-#define ATUC_INTERVAL_FAILED_FASTR_FLAG 0x2 /* Bit 1 */
-#define ATUC_INTERVAL_SESL_FLAG 0x4 /* Bit 2 */
-#define ATUC_INTERVAL_UASL_FLAG 0x8 /* Bit 3 */
-
-/* adslAturIntervalExtTable */
-#define ATUR_INTERVAL_SESL_FLAG 0X1 /* BIT 0th position */
-#define ATUR_INTERVAL_UASL_FLAG 0X2 /* BIT 1 */
-
-/* adslAlarmConfProfileExtTable */
-#define ATUC_THRESH_15MIN_FAILED_FASTR_FLAG 0X1/* BIT 0th position */
-#define ATUC_THRESH_15MIN_SESL_FLAG 0X2 /* BIT 1 */
-#define ATUC_THRESH_15MIN_UASL_FLAG 0X4 /* BIT 2 */
-#define ATUR_THRESH_15MIN_SESL_FLAG 0X8 /* BIT 3 */
-#define ATUR_THRESH_15MIN_UASL_FLAG 0X10 /* BIT 4 */
-
-/* adslAturExtTraps */
-#define ATUC_15MIN_FAILED_FASTR_TRAP_FLAG 0X1 /* BIT 0th position */
-#define ATUC_15MIN_SESL_TRAP_FLAG 0X2 /* BIT 1 */
-#define ATUC_15MIN_UASL_TRAP_FLAG 0X4 /* BIT 2 */
-#define ATUR_15MIN_SESL_TRAP_FLAG 0X8 /* BIT 3 */
-#define ATUR_15MIN_UASL_TRAP_FLAG 0X10 /* BIT 4 */
-
-#endif
-
-/* adslLineStatus Flags */
-#define LINE_STAT_MODEM_STATUS_FLAG 0x1 /* BIT 0th position */
-#define LINE_STAT_MODEM_STATUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 0, 0, 1, data, TxMessage)
-#define LINE_STAT_MODE_SEL_FLAG 0x2 /* BIT 1 */
-#define LINE_STAT_MODE_SEL_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 1, 0, 1, data, TxMessage)
-#define LINE_STAT_TRELLCOD_ENABLE_FLAG 0x4 /* BIT 2 */
-#define LINE_STAT_TRELLCOD_ENABLE_FLAG_MAKECMV makeCMV(H2D_CMV_READ, OPTN, 2, 0, 1, data, TxMessage)
-#define LINE_STAT_LATENCY_FLAG 0x8 /* BIT 3 */
-#define LINE_STAT_LATENCY_FLAG_MAKECMV makeCMV(H2D_CMV_READ, STAT, 12, 0, 1, data, TxMessage)
-
-/* adslLineRate Flags */
-#define LINE_RATE_DATA_RATEDS_FLAG 0x1 /* BIT 0th position */
-#define LINE_RATE_DATA_RATEDS_FLAG_ADSL1_LP0_MAKECMV makeCMV(H2D_CMV_READ, RATE, 1, 0, 2, data, TxMessage)
-#define LINE_RATE_DATA_RATEDS_FLAG_ADSL1_LP1_MAKECMV makeCMV(H2D_CMV_READ, RATE, 1, 2, 2, data, TxMessage)
-
-
-#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_RP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 12, 0, 1, data, TxMessage)
-#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_MP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 13, 0, 1, data, TxMessage)
-#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_LP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 14, 0, 1, data, TxMessage)
-#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_TP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 15, 0, 1, data, TxMessage)
-#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_KP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 17, 0, 2, data, TxMessage)
-
-#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_RP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 12, 1, 1, data, TxMessage)
-#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_MP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 13, 1, 1, data, TxMessage)
-#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_LP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 14, 1, 1, data, TxMessage)
-#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_TP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 15, 1, 1, data, TxMessage)
-#define LINE_RATE_DATA_RATEDS_FLAG_ADSL2_KP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 17, 2, 2, data, TxMessage)
-
-#define LINE_RATE_DATA_RATEUS_FLAG 0x2 /* BIT 1 */
-#define LINE_RATE_DATA_RATEUS_FLAG_ADSL1_LP0_MAKECMV makeCMV(H2D_CMV_READ, RATE, 0, 0, 2, data, TxMessage)
-#define LINE_RATE_DATA_RATEUS_FLAG_ADSL1_LP1_MAKECMV makeCMV(H2D_CMV_READ, RATE, 0, 2, 2, data, TxMessage)
-
-
-#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_RP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 23, 0, 1, data, TxMessage)
-#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_MP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 24, 0, 1, data, TxMessage)
-#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_LP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 25, 0, 1, data, TxMessage)
-#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_TP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 26, 0, 1, data, TxMessage)
-#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_KP_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 28, 0, 2, data, TxMessage)
-
-#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_RP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 23, 1, 1, data, TxMessage)
-#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_MP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 24, 1, 1, data, TxMessage)
-#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_LP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 25, 1, 1, data, TxMessage)
-#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_TP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 26, 1, 1, data, TxMessage)
-#define LINE_RATE_DATA_RATEUS_FLAG_ADSL2_KP_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 28, 2, 2, data, TxMessage)
-
-#define LINE_RATE_ATTNDRDS_FLAG 0x4 /* BIT 2 */
-#define LINE_RATE_ATTNDRDS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 4, 2, data, TxMessage)
-
-#define LINE_RATE_ATTNDRUS_FLAG 0x8 /* BIT 3 */
-#define LINE_RATE_ATTNDRUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 4, 2, data, TxMessage)
-
-/* adslLineInformation Flags */
-#define LINE_INFO_INTLV_DEPTHDS_FLAG 0x1 /* BIT 0th position */
-#define LINE_INFO_INTLV_DEPTHDS_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 27, 0, 1, data, TxMessage)
-#define LINE_INFO_INTLV_DEPTHDS_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 27, 1, 1, data, TxMessage)
-#define LINE_INFO_INTLV_DEPTHUS_FLAG 0x2 /* BIT 1 */
-#define LINE_INFO_INTLV_DEPTHUS_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 16, 0, 1, data, TxMessage)
-#define LINE_INFO_INTLV_DEPTHUS_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, CNFG, 16, 1, 1, data, TxMessage)
-#define LINE_INFO_LATNDS_FLAG 0x4 /* BIT 2 */
-#define LINE_INFO_LATNDS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 1, 1, data, TxMessage)
-#define LINE_INFO_LATNUS_FLAG 0x8 /* BIT 3 */
-#define LINE_INFO_LATNUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 1, 1, data, TxMessage)
-#define LINE_INFO_SATNDS_FLAG 0x10 /* BIT 4 */
-#define LINE_INFO_SATNDS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 2, 1, data, TxMessage)
-#define LINE_INFO_SATNUS_FLAG 0x20 /* BIT 5 */
-#define LINE_INFO_SATNUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 2, 1, data, TxMessage)
-#define LINE_INFO_SNRMNDS_FLAG 0x40 /* BIT 6 */
-#define LINE_INFO_SNRMNDS_FLAG_ADSL1_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 3, 1, data, TxMessage)
-#define LINE_INFO_SNRMNDS_FLAG_ADSL2_MAKECMV makeCMV(H2D_CMV_READ, RATE, 3, 0, 1, data, TxMessage)
-#define LINE_INFO_SNRMNDS_FLAG_ADSL2PLUS_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 46, 0, 1, data, TxMessage)
-#define LINE_INFO_SNRMNUS_FLAG 0x80 /* BIT 7 */
-#define LINE_INFO_SNRMNUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 3, 1, data, TxMessage)
-#define LINE_INFO_ACATPDS_FLAG 0x100 /* BIT 8 */
-#define LINE_INFO_ACATPDS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 68, 6, 1, data, TxMessage)
-#define LINE_INFO_ACATPUS_FLAG 0x200 /* BIT 9 */
-#define LINE_INFO_ACATPUS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, INFO, 69, 6, 1, data, TxMessage)
-
-/* adslNearEndPerformanceStats Flags */
-#define NEAREND_PERF_SUPERFRAME_FLAG_LSW_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 20, 0, 1, data, TxMessage)
-#define NEAREND_PERF_SUPERFRAME_FLAG_MSW_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 21, 0, 1, data, TxMessage)
-#define NEAREND_PERF_SUPERFRAME_FLAG 0x1 /* BIT 0th position */
-#define NEAREND_PERF_LOS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 0, 0, 1, data, TxMessage)
-#define NEAREND_PERF_LOS_FLAG 0x2 /* BIT 1 */
-#define NEAREND_PERF_LOF_FLAG 0x4 /* BIT 2 */
-#define NEAREND_PERF_LPR_FLAG 0x8 /* BIT 3 */
-#define NEAREND_PERF_NCD_FLAG 0x10 /* BIT 4 */
-#define NEAREND_PERF_LCD_FLAG 0x20 /* BIT 5 */
-#define NEAREND_PERF_CRC_FLAG 0x40 /* BIT 6 */
-#define NEAREND_PERF_CRC_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 2, 0, 1, data, TxMessage)
-#define NEAREND_PERF_CRC_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 2, 1, 1, data, TxMessage)
-#define NEAREND_PERF_RSCORR_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 3, 0, 1, data, TxMessage)
-#define NEAREND_PERF_RSCORR_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 3, 1, 1, data, TxMessage)
-#define NEAREND_PERF_RSCORR_FLAG 0x80 /* BIT 7 */
-#define NEAREND_PERF_FECS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 6, 0, 1, data, TxMessage)
-#define NEAREND_PERF_FECS_FLAG 0x100 /* BIT 8 */
-#define NEAREND_PERF_ES_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 7, 0, 1, data, TxMessage)
-#define NEAREND_PERF_ES_FLAG 0x200 /* BIT 9 */
-#define NEAREND_PERF_SES_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 8, 0, 1, data, TxMessage)
-#define NEAREND_PERF_SES_FLAG 0x400 /* BIT 10 */
-#define NEAREND_PERF_LOSS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 9, 0, 1, data, TxMessage)
-#define NEAREND_PERF_LOSS_FLAG 0x800 /* BIT 11 */
-#define NEAREND_PERF_UAS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 10, 0, 1, data, TxMessage)
-#define NEAREND_PERF_UAS_FLAG 0x1000 /* BIT 12 */
-#define NEAREND_PERF_HECERR_FLAG_BC0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 11, 0, 2, data, TxMessage)
-#define NEAREND_PERF_HECERR_FLAG_BC1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 11, 2, 2, data, TxMessage)
-#define NEAREND_PERF_HECERR_FLAG 0x2000 /* BIT 13 */
-
-/* adslFarEndPerformanceStats Flags */
-#define FAREND_PERF_LOS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 1, 0, 1, data, TxMessage)
-#define FAREND_PERF_LOS_FLAG 0x1 /* BIT 0th position */
-#define FAREND_PERF_LOF_FLAG 0x2 /* BIT 1 */
-#define FAREND_PERF_LPR_FLAG 0x4 /* BIT 2 */
-#define FAREND_PERF_NCD_FLAG 0x8 /* BIT 3 */
-#define FAREND_PERF_LCD_FLAG 0x10 /* BIT 4 */
-#define FAREND_PERF_CRC_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 24, 0, 1, data, TxMessage)
-#define FAREND_PERF_CRC_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 24, 1, 1, data, TxMessage)
-#define FAREND_PERF_CRC_FLAG 0x20 /* BIT 5 */
-#define FAREND_PERF_RSCORR_FLAG_LP0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 28, 0, 1, data, TxMessage)
-#define FAREND_PERF_RSCORR_FLAG_LP1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 28, 1, 1, data, TxMessage)
-#define FAREND_PERF_RSCORR_FLAG 0x40 /* BIT 6 */
-#define FAREND_PERF_FECS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 32, 0, 1, data, TxMessage)
-#define FAREND_PERF_FECS_FLAG 0x80 /* BIT 7 */
-#define FAREND_PERF_ES_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 33, 0, 1, data, TxMessage)
-#define FAREND_PERF_ES_FLAG 0x100 /* BIT 8 */
-#define FAREND_PERF_SES_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 34, 0, 1, data, TxMessage)
-#define FAREND_PERF_SES_FLAG 0x200 /* BIT 9 */
-#define FAREND_PERF_LOSS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 35, 0, 1, data, TxMessage)
-#define FAREND_PERF_LOSS_FLAG 0x400 /* BIT 10 */
-#define FAREND_PERF_UAS_FLAG_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 36, 0, 1, data, TxMessage)
-#define FAREND_PERF_UAS_FLAG 0x800 /* BIT 11 */
-#define FAREND_PERF_HECERR_FLAG_BC0_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 37, 0, 2, data, TxMessage)
-#define FAREND_PERF_HECERR_FLAG_BC1_MAKECMV makeCMV(H2D_CMV_READ, PLAM, 37, 2, 2, data, TxMessage)
-#define FAREND_PERF_HECERR_FLAG 0x1000 /* BIT 12 */
-// 603221:tc.chen end
-/* TR-69 related additional parameters - defines */
-/* Defines for struct adslATURSubcarrierInfo */
-#define NEAREND_HLINSC 0x1
-#define NEAREND_HLINSC_MAKECMV(mode) makeCMV(mode, INFO, 71, 2, 1, data, TxMessage)
-#define NEAREND_HLINPS 0x2
-#define NEAREND_HLINPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 73, idx, size, data, TxMessage)
-#define NEAREND_HLOGMT 0x4
-#define NEAREND_HLOGMT_MAKECMV(mode) makeCMV(mode, INFO, 80, 0, 1, data, TxMessage)
-#define NEAREND_HLOGPS 0x8
-#define NEAREND_HLOGPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 75, idx, size, data, TxMessage)
-#define NEAREND_QLNMT 0x10
-#define NEAREND_QLNMT_MAKECMV(mode) makeCMV(mode, INFO, 80, 1, 1, data, TxMessage)
-#define NEAREND_QLNPS 0x20
-#define NEAREND_QLNPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 77, idx, size, data, TxMessage)
-#define NEAREND_SNRMT 0x40
-#define NEAREND_SNRMT_MAKECMV(mode) makeCMV(mode, INFO, 80, 2, 1, data, TxMessage)
-#define NEAREND_SNRPS 0x80
-#define NEAREND_SNRPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 78, idx, size, data, TxMessage)
-#define NEAREND_BITPS 0x100
-#define NEAREND_BITPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 22, idx, size, data, TxMessage)
-#define NEAREND_GAINPS 0x200
-#define NEAREND_GAINPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 24, idx, size, data, TxMessage)
-
-/* Defines for struct adslATUCSubcarrierInfo */
-#define FAREND_HLINSC 0x1
-
-/* As per the feedback from Knut on 21/08/2006, the cmv command of HLINSC should be INFO 70 2 */
-#define FAREND_HLINSC_MAKECMV(mode) makeCMV(mode, INFO, 70, 2, 1, data, TxMessage)
-#define FAREND_HLINPS 0x2
-#define FAREND_HLINPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 72, idx, size, data, TxMessage)
-#define FAREND_HLOGMT 0x4
-#define FAREND_HLOGMT_MAKECMV(mode) makeCMV(mode, INFO, 79, 0, 1, data, TxMessage)
-#define FAREND_HLOGPS 0x8
-#define FAREND_HLOGPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 74, idx, size, data, TxMessage)
-#define FAREND_QLNMT 0x10
-#define FAREND_QLNMT_MAKECMV(mode) makeCMV(mode, INFO, 79, 1, 1, data, TxMessage)
-#define FAREND_QLNPS 0x20
-#define FAREND_QLNPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 76, idx, size, data, TxMessage)
-#define FAREND_SNRMT 0x40
-#define FAREND_SNRMT_MAKECMV(mode) makeCMV(mode, INFO, 79, 2, 1, data, TxMessage)
-#define FAREND_SNRPS 0x80
-#define FAREND_SNRPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 11, idx, size, data, TxMessage)
-#define FAREND_SNRPS_DIAG_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 10, idx, size, data, TxMessage)
-#define FAREND_BITPS 0x100
-#define FAREND_BITPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 23, idx, size, data, TxMessage)
-#define FAREND_GAINPS 0x200
-#define FAREND_GAINPS_MAKECMV(mode,idx,size) makeCMV(mode, INFO, 25, idx, size, data, TxMessage)
-
-
-// GET_ADSL_POWER_SPECTRAL_DENSITY
-#define NOMPSD_US_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 0, 1, data, TxMessage)
-#define NOMPSD_DS_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 1, 1, data, TxMessage)
-#define PCB_US_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 6, 1, data, TxMessage)
-#define PCB_DS_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 7, 1, data, TxMessage)
-#define RMSGI_US_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 10, 1, data, TxMessage)
-#define RMSGI_DS_MAKECMV makeCMV(H2D_CMV_READ, INFO, 102, 11, 1, data, TxMessage)
-
-/////////////////////////////////////////////////Macro Definitions ? FLAG Setting & Testing
-
-#define SET_FLAG(flags, flag_val) ((*flags) = ((*flags) | flag_val))
-// -- This macro sets the flags with the flag_val. Here flags is passed as a pointer
-
-#define IS_FLAG_SET(flags, test_flag) (((*flags) & (test_flag)) == (test_flag)? test_flag:0)
-// -- This macro verifies whether test_flag has been set in flags. Here flags is passed as a pointer
-
-
-#define CLR_FLAG(flags, flag_bit) ((*flags) = (*flags) & (~flag_bit))
-// -- This macro resets the specified flag_bit in the flags. Here flags is passed as a pointer
-
-
-////////////////////////////////////////////////DATA STRUCTURES ORGANIZATION
-
-//Here are the data structures used for accessing mib parameters. The ioctl call includes the third parameter as a void pointer. This parameter has to be type-casted in the driver code to the corresponding structure depending upon the command type. For Ex: consider the ioctl used to get the adslLineCode type, ioctl(fd,GET_ADSL_LINE_CODE,void *struct_adslLineTableEntry). In the driver code we check on the type of the command, i.e GET_ADSL_LINE_CODE and type-cast the void pointer to struct adslLineTableEntry type.
- //
-#define u32 unsigned int
-#define u16 unsigned short
-#define s16 short
-#define u8 unsigned char
-
-
-typedef u32 AdslPerfTimeElapsed;
-typedef u32 AdslPerfPrevDayCount;
-typedef u32 PerfCurrentCount;
-typedef u32 PerfIntervalCount;
-typedef u32 AdslPerfCurrDayCount;
-
-
-//ioctl(int fd, GET_ADSL_LINE_CODE, void *struct_adslLineTableEntry)
-
-typedef struct adslLineTableEntry {
- int ifIndex;
- int adslLineCode;
- u8 flags;
-} adslLineTableEntry;
-
-#ifdef IFXMIPS_MEI_MIB_RFC3440
-typedef struct adslLineExtTableEntry {
- int ifIndex;
- u16 adslLineTransAtucCap;
- u16 adslLineTransAtucConfig;
- u16 adslLineTransAtucActual;
- int adslLineGlitePowerState;
- u32 flags;
-}adslLineExtTableEntry;
-#endif
-//ioctl(int fd, GET_ADSL_ATUC_PHY, void *struct_adslAtucPhysEntry)
-#ifndef u_char
-#define u_char u8
-#endif
-
-typedef struct adslVendorId {
- u16 country_code;
- u_char provider_id[4]; /* Ascii characters */
- u_char revision_info[2];
-}adslVendorId;
-
-typedef struct adslAtucPhysEntry {
- int ifIndex;
- char serial_no[32];
- union {
- char vendor_id[16];
- adslVendorId vendor_info;
- } vendor_id;
- char version_no[16];
- u32 status;
- int outputPwr;
- u32 attainableRate;
- u8 flags;
-} adslAtucPhysEntry;
-
-
-//ioctl(int fd, GET_ADSL_ATUR_PHY, void *struct_adslAturPhysEntry)
-
-typedef struct adslAturPhysEntry {
- int ifIndex;
- char serial_no[32];
- union {
- char vendor_id[16];
- adslVendorId vendor_info;
- } vendor_id;
- char version_no[16];
- int SnrMgn;
- u32 Attn;
- u32 status;
- int outputPwr;
- u32 attainableRate;
- u8 flags;
-} adslAturPhysEntry;
-
-
-//ioctl(int fd, GET_ADSL_ATUC_CHAN_INFO, void *struct_adslAtucChanInfo)
-
-typedef struct adslAtucChanInfo {
- int ifIndex;
- u32 interleaveDelay;
- u32 currTxRate;
- u32 prevTxRate;
- u8 flags;
-} adslAtucChanInfo;
-
-
-//ioctl(int fd, GET_ADSL_ATUR_CHAN_INFO, void *struct_adslAturChanInfo)
-
-typedef struct adslAturChanInfo {
- int ifIndex;
- u32 interleaveDelay;
- u32 currTxRate;
- u32 prevTxRate;
- u32 crcBlkLen;
- u8 flags;
-} adslAturChanInfo;
-
-
-//ioctl(int fd, GET_ADSL_ATUC_PERF_DATA, void *struct_atucPerfDataEntry)
-
-typedef struct atucPerfDataEntry
-{
- int ifIndex;
- u32 adslAtucPerfLofs;
- u32 adslAtucPerfLoss;
- u32 adslAtucPerfESs;
- u32 adslAtucPerfInits;
- int adslAtucPerfValidIntervals;
- int adslAtucPerfInvalidIntervals;
- AdslPerfTimeElapsed adslAtucPerfCurr15MinTimeElapsed;
- PerfCurrentCount adslAtucPerfCurr15MinLofs;
- PerfCurrentCount adslAtucPerfCurr15MinLoss;
- PerfCurrentCount adslAtucPerfCurr15MinESs;
- PerfCurrentCount adslAtucPerfCurr15MinInits;
- AdslPerfTimeElapsed adslAtucPerfCurr1DayTimeElapsed;
- AdslPerfCurrDayCount adslAtucPerfCurr1DayLofs;
- AdslPerfCurrDayCount adslAtucPerfCurr1DayLoss;
- AdslPerfCurrDayCount adslAtucPerfCurr1DayESs;
- AdslPerfCurrDayCount adslAtucPerfCurr1DayInits;
- int adslAtucPerfPrev1DayMoniSecs;
- AdslPerfPrevDayCount adslAtucPerfPrev1DayLofs;
- AdslPerfPrevDayCount adslAtucPerfPrev1DayLoss;
- AdslPerfPrevDayCount adslAtucPerfPrev1DayESs;
- AdslPerfPrevDayCount adslAtucPerfPrev1DayInits;
- u32 flags;
-} atucPerfDataEntry;
-
-#ifdef IFXMIPS_MEI_MIB_RFC3440
-typedef struct atucPerfDataExtEntry
- {
- int ifIndex;
- u32 adslAtucPerfStatFastR;
- u32 adslAtucPerfStatFailedFastR;
- u32 adslAtucPerfStatSesL;
- u32 adslAtucPerfStatUasL;
- u32 adslAtucPerfCurr15MinFastR;
- u32 adslAtucPerfCurr15MinFailedFastR;
- u32 adslAtucPerfCurr15MinSesL;
- u32 adslAtucPerfCurr15MinUasL;
- u32 adslAtucPerfCurr1DayFastR;
- u32 adslAtucPerfCurr1DayFailedFastR;
- u32 adslAtucPerfCurr1DaySesL;
- u32 adslAtucPerfCurr1DayUasL;
- u32 adslAtucPerfPrev1DayFastR;
- u32 adslAtucPerfPrev1DayFailedFastR;
- u32 adslAtucPerfPrev1DaySesL;
- u32 adslAtucPerfPrev1DayUasL;
- u32 flags;
-} atucPerfDataExtEntry;
-
-#endif
-//ioctl(int fd, GET_ADSL_ATUR_PERF_DATA, void *struct_aturPerfDataEntry)
-
-typedef struct aturPerfDataEntry
-{
- int ifIndex;
- u32 adslAturPerfLofs;
- u32 adslAturPerfLoss;
- u32 adslAturPerfLprs;
- u32 adslAturPerfESs;
- int adslAturPerfValidIntervals;
- int adslAturPerfInvalidIntervals;
- AdslPerfTimeElapsed adslAturPerfCurr15MinTimeElapsed;
- PerfCurrentCount adslAturPerfCurr15MinLofs;
- PerfCurrentCount adslAturPerfCurr15MinLoss;
- PerfCurrentCount adslAturPerfCurr15MinLprs;
- PerfCurrentCount adslAturPerfCurr15MinESs;
- AdslPerfTimeElapsed adslAturPerfCurr1DayTimeElapsed;
- AdslPerfCurrDayCount adslAturPerfCurr1DayLofs;
- AdslPerfCurrDayCount adslAturPerfCurr1DayLoss;
- AdslPerfCurrDayCount adslAturPerfCurr1DayLprs;
- AdslPerfCurrDayCount adslAturPerfCurr1DayESs;
- int adslAturPerfPrev1DayMoniSecs;
- AdslPerfPrevDayCount adslAturPerfPrev1DayLofs;
- AdslPerfPrevDayCount adslAturPerfPrev1DayLoss;
- AdslPerfPrevDayCount adslAturPerfPrev1DayLprs;
- AdslPerfPrevDayCount adslAturPerfPrev1DayESs;
- u32 flags;
-} aturPerfDataEntry;
-
-#ifdef IFXMIPS_MEI_MIB_RFC3440
-typedef struct aturPerfDataExtEntry
- {
- int ifIndex;
- u32 adslAturPerfStatSesL;
- u32 adslAturPerfStatUasL;
- u32 adslAturPerfCurr15MinSesL;
- u32 adslAturPerfCurr15MinUasL;
- u32 adslAturPerfCurr1DaySesL;
- u32 adslAturPerfCurr1DayUasL;
- u32 adslAturPerfPrev1DaySesL;
- u32 adslAturPerfPrev1DayUasL;
- u32 flags;
-} aturPerfDataExtEntry;
-#endif
-//ioctl(int fd, GET_ADSL_ATUC_INTVL_INFO, void *struct_adslAtucInvtInfo)
-
-typedef struct adslAtucIntvlInfo {
- int ifIndex;
- int IntervalNumber;
- PerfIntervalCount intervalLOF;
- PerfIntervalCount intervalLOS;
- PerfIntervalCount intervalES;
- PerfIntervalCount intervalInits;
- int intervalValidData;
- u8 flags;
-} adslAtucIntvlInfo;
-
-#ifdef IFXMIPS_MEI_MIB_RFC3440
-typedef struct adslAtucInvtlExtInfo
- {
- int ifIndex;
- int IntervalNumber;
- u32 adslAtucIntervalFastR;
- u32 adslAtucIntervalFailedFastR;
- u32 adslAtucIntervalSesL;
- u32 adslAtucIntervalUasL;
- u32 flags;
-} adslAtucInvtlExtInfo;
-#endif
-//ioctl(int fd, GET_ADSL_ATUR_INTVL_INFO, void *struct_adslAturInvtlInfo)
-
-typedef struct adslAturIntvlInfo {
- int ifIndex;
- int IntervalNumber;
- PerfIntervalCount intervalLOF;
- PerfIntervalCount intervalLOS;
- PerfIntervalCount intervalLPR;
- PerfIntervalCount intervalES;
- int intervalValidData;
- u8 flags;
-} adslAturIntvlInfo;
-
-#ifdef IFXMIPS_MEI_MIB_RFC3440
-typedef struct adslAturInvtlExtInfo
- {
- int ifIndex;
- int IntervalNumber;
- u32 adslAturIntervalSesL;
- u32 adslAturIntervalUasL;
- u32 flags;
-} adslAturInvtlExtInfo;
-#endif
-//ioctl(int fd, GET_ADSL_ATUC_CHAN_PERF_DATA, void *struct_atucChannelPerfDataEntry)
-
-typedef struct atucChannelPerfDataEntry
-{
- int ifIndex;
- u32 adslAtucChanReceivedBlks;
- u32 adslAtucChanTransmittedBlks;
- u32 adslAtucChanCorrectedBlks;
- u32 adslAtucChanUncorrectBlks;
- int adslAtucChanPerfValidIntervals;
- int adslAtucChanPerfInvalidIntervals;
- AdslPerfTimeElapsed adslAtucChanPerfCurr15MinTimeElapsed;
- PerfCurrentCount adslAtucChanPerfCurr15MinReceivedBlks;
- PerfCurrentCount adslAtucChanPerfCurr15MinTransmittedBlks;
- PerfCurrentCount adslAtucChanPerfCurr15MinCorrectedBlks;
- PerfCurrentCount adslAtucChanPerfCurr15MinUncorrectBlks;
- AdslPerfTimeElapsed adslAtucChanPerfCurr1DayTimeElapsed;
- AdslPerfCurrDayCount adslAtucChanPerfCurr1DayReceivedBlks;
- AdslPerfCurrDayCount adslAtucChanPerfCurr1DayTransmittedBlks;
- AdslPerfCurrDayCount adslAtucChanPerfCurr1DayCorrectedBlks;
- AdslPerfCurrDayCount adslAtucChanPerfCurr1DayUncorrectBlks;
- int adslAtucChanPerfPrev1DayMoniSecs;
- AdslPerfPrevDayCount adslAtucChanPerfPrev1DayReceivedBlks;
- AdslPerfPrevDayCount adslAtucChanPerfPrev1DayTransmittedBlks;
- AdslPerfPrevDayCount adslAtucChanPerfPrev1DayCorrectedBlks;
- AdslPerfPrevDayCount adslAtucChanPerfPrev1DayUncorrectBlks;
- u32 flags;
-}atucChannelPerfDataEntry;
-
-
-//ioctl(int fd, GET_ADSL_ATUR_CHAN_PERF_DATA, void *struct_aturChannelPerfDataEntry)
-
-typedef struct aturChannelPerfDataEntry
-{
- int ifIndex;
- u32 adslAturChanReceivedBlks;
- u32 adslAturChanTransmittedBlks;
- u32 adslAturChanCorrectedBlks;
- u32 adslAturChanUncorrectBlks;
- int adslAturChanPerfValidIntervals;
- int adslAturChanPerfInvalidIntervals;
- AdslPerfTimeElapsed adslAturChanPerfCurr15MinTimeElapsed;
- PerfCurrentCount adslAturChanPerfCurr15MinReceivedBlks;
- PerfCurrentCount adslAturChanPerfCurr15MinTransmittedBlks;
- PerfCurrentCount adslAturChanPerfCurr15MinCorrectedBlks;
- PerfCurrentCount adslAturChanPerfCurr15MinUncorrectBlks;
- AdslPerfTimeElapsed adslAturChanPerfCurr1DayTimeElapsed;
- AdslPerfCurrDayCount adslAturChanPerfCurr1DayReceivedBlks;
- AdslPerfCurrDayCount adslAturChanPerfCurr1DayTransmittedBlks;
- AdslPerfCurrDayCount adslAturChanPerfCurr1DayCorrectedBlks;
- AdslPerfCurrDayCount adslAturChanPerfCurr1DayUncorrectBlks;
- int adslAturChanPerfPrev1DayMoniSecs;
- AdslPerfPrevDayCount adslAturChanPerfPrev1DayReceivedBlks;
- AdslPerfPrevDayCount adslAturChanPerfPrev1DayTransmittedBlks;
- AdslPerfPrevDayCount adslAturChanPerfPrev1DayCorrectedBlks;
- AdslPerfPrevDayCount adslAturChanPerfPrev1DayUncorrectBlks;
- u32 flags;
-} aturChannelPerfDataEntry;
-
-
-//ioctl(int fd, GET_ADSL_ATUC_CHAN_INTVL_INFO, void *struct_adslAtucChanIntvlInfo)
-
-typedef struct adslAtucChanIntvlInfo {
- int ifIndex;
- int IntervalNumber;
- PerfIntervalCount chanIntervalRecvdBlks;
- PerfIntervalCount chanIntervalXmitBlks;
- PerfIntervalCount chanIntervalCorrectedBlks;
- PerfIntervalCount chanIntervalUncorrectBlks;
- int intervalValidData;
- u8 flags;
-} adslAtucChanIntvlInfo;
-
-
-//ioctl(int fd, GET_ADSL_ATUR_CHAN_INTVL_INFO, void *struct_adslAturChanIntvlInfo)
-
-typedef struct adslAturChanIntvlInfo {
- int ifIndex;
- int IntervalNumber;
- PerfIntervalCount chanIntervalRecvdBlks;
- PerfIntervalCount chanIntervalXmitBlks;
- PerfIntervalCount chanIntervalCorrectedBlks;
- PerfIntervalCount chanIntervalUncorrectBlks;
- int intervalValidData;
- u8 flags;
-} adslAturChanIntvlInfo;
-
-
-//ioctl(int fd, GET_ADSL_ALRM_CONF_PROF, void *struct_adslLineAlarmConfProfileEntry)
-//ioctl(int fd, SET_ADSL_ALRM_CONF_PROF, void *struct_adslLineAlarmConfProfileEntry)
-
-typedef struct adslLineAlarmConfProfileEntry
- {
- unsigned char adslLineAlarmConfProfileName[32];
- int adslAtucThresh15MinLofs;
- int adslAtucThresh15MinLoss;
- int adslAtucThresh15MinESs;
- u32 adslAtucThreshFastRateUp;
- u32 adslAtucThreshInterleaveRateUp;
- u32 adslAtucThreshFastRateDown;
- u32 adslAtucThreshInterleaveRateDown;
- int adslAtucInitFailureTrapEnable;
- int adslAturThresh15MinLofs;
- int adslAturThresh15MinLoss;
- int adslAturThresh15MinLprs;
- int adslAturThresh15MinESs;
- u32 adslAturThreshFastRateUp;
- u32 adslAturThreshInterleaveRateUp;
- u32 adslAturThreshFastRateDown;
- u32 adslAturThreshInterleaveRateDown;
- int adslLineAlarmConfProfileRowStatus;
- u32 flags;
-} adslLineAlarmConfProfileEntry;
-
-#ifdef IFXMIPS_MEI_MIB_RFC3440
-typedef struct adslLineAlarmConfProfileExtEntry
- {
- u8 adslLineAlarmConfProfileExtName[32];
- u32 adslAtucThreshold15MinFailedFastR;
- u32 adslAtucThreshold15MinSesL;
- u32 adslAtucThreshold15MinUasL;
- u32 adslAturThreshold15MinSesL;
- u32 adslAturThreshold15MinUasL;
- u32 flags;
-} adslLineAlarmConfProfileExtEntry;
-#endif
-//TRAPS
-
-/* The following Data Sturctures are added to support the WEB related parameters for ADSL Statistics */
-typedef struct adslLineStatus
- {
- int adslModemStatus;
- u32 adslModeSelected;
- int adslAtucThresh15MinESs;
- int adslTrellisCodeEnable;
- int adslLatency;
- u8 flags;
- } adslLineStatusInfo;
-
-typedef struct adslLineRate
- {
- u32 adslDataRateds;
- u32 adslDataRateus;
- u32 adslATTNDRds;
- u32 adslATTNDRus;
- u8 flags;
- } adslLineRateInfo;
-
-typedef struct adslLineInfo
- {
- u32 adslInterleaveDepthds;
- u32 adslInterleaveDepthus;
- u32 adslLATNds;
- u32 adslLATNus;
- u32 adslSATNds;
- u32 adslSATNus;
- int adslSNRMds;
- int adslSNRMus;
- int adslACATPds;
- int adslACATPus;
- u32 flags;
- } adslLineInfo;
-
-typedef struct adslNearEndPerfStats
- {
- u32 adslSuperFrames;
- u32 adslneLOS;
- u32 adslneLOF;
- u32 adslneLPR;
- u32 adslneNCD;
- u32 adslneLCD;
- u32 adslneCRC;
- u32 adslneRSCorr;
- u32 adslneFECS;
- u32 adslneES;
- u32 adslneSES;
- u32 adslneLOSS;
- u32 adslneUAS;
- u32 adslneHECErrors;
- u32 flags;
- } adslNearEndPerfStats;
-
-typedef struct adslFarEndPerfStats
- {
- u32 adslfeLOS;
- u32 adslfeLOF;
- u32 adslfeLPR;
- u32 adslfeNCD;
- u32 adslfeLCD;
- u32 adslfeCRC;
- u32 adslfeRSCorr;
- u32 adslfeFECS;
- u32 adslfeES;
- u32 adslfeSES;
- u32 adslfeLOSS;
- u32 adslfeUAS;
- u32 adslfeHECErrors;
- u32 flags;
- } adslFarEndPerfStats;
-
-/* The number of tones (and hence indexes) is dependent on the ADSL mode - G.992.1, G.992.2, G.992.3, * G.992.4 and G.992.5 */
-typedef struct adslATURSubcarrierInfo {
- int ifindex;
- u16 HLINSCds;
- u16 HLINpsds[1024];/* Even index = real part; Odd Index
- = imaginary part for each tone */
- u16 HLOGMTds;
- u16 HLOGpsds[512];
- u16 QLNMTds;
- u16 QLNpsds[512];
- u16 SNRMTds;
- u16 SNRpsds[512];
- u16 BITpsds[512];
- s16 GAINpsds[512]; /* Signed value in 0.1dB units. i.e dB * 10.
- Needs to be converted into linear scale*/
- u16 flags;
-}adslATURSubcarrierInfo;
-
-typedef struct adslATUCSubcarrierInfo {
- int ifindex;
- u16 HLINSCus;
- u16 HLINpsus[128];/* Even index = real part; Odd Index
- = imaginary part for each tone */
- u16 HLOGMTus;
- u16 HLOGpsus[64];
- u16 QLNMTus;
- u16 QLNpsus[64];
- u16 SNRMTus;
- u16 SNRpsus[64];
- u16 BITpsus[64];
- s16 GAINpsus[64]; /* Signed value in 0.1dB units. i.e dB * 10.
- Needs to be converted into linear scale*/
- u16 flags;
-}adslATUCSubcarrierInfo;
-
-#ifndef u_int16
-#define u_int16 u16
-#endif
-
-typedef struct adslInitStats {
- u_int16 FullInitializationCount;
- u_int16 FailedFullInitializationCount;
- u_int16 LINIT_Errors;
- u_int16 Init_Timeouts;
-}adslInitStats;
-
-typedef struct adslPowerSpectralDensity {
- int ACTPSDds;
- int ACTPSDus;
-}adslPowerSpectralDensity;
-
-//ioctl(int fd, ADSL_ATUR_TRAPS, void *uint16_flags)
-typedef union structpts {
- adslLineTableEntry * adslLineTableEntry_pt;
- adslAtucPhysEntry * adslAtucPhysEntry_pt;
- adslAturPhysEntry * adslAturPhysEntry_pt;
- adslAtucChanInfo * adslAtucChanInfo_pt;
- adslAturChanInfo * adslAturChanInfo_pt;
- atucPerfDataEntry * atucPerfDataEntry_pt;
- aturPerfDataEntry * aturPerfDataEntry_pt;
- adslAtucIntvlInfo * adslAtucIntvlInfo_pt;
- adslAturIntvlInfo * adslAturIntvlInfo_pt;
- atucChannelPerfDataEntry * atucChannelPerfDataEntry_pt;
- aturChannelPerfDataEntry * aturChannelPerfDataEntry_pt;
- adslAtucChanIntvlInfo * adslAtucChanIntvlInfo_pt;
- adslAturChanIntvlInfo * adslAturChanIntvlInfo_pt;
- adslLineAlarmConfProfileEntry * adslLineAlarmConfProfileEntry_pt;
- // RFC 3440
-
- #ifdef IFXMIPS_MEI_MIB_RFC3440
- adslLineExtTableEntry * adslLineExtTableEntry_pt;
- atucPerfDataExtEntry * atucPerfDataExtEntry_pt;
- adslAtucInvtlExtInfo * adslAtucInvtlExtInfo_pt;
- aturPerfDataExtEntry * aturPerfDataExtEntry_pt;
- adslAturInvtlExtInfo * adslAturInvtlExtInfo_pt;
- adslLineAlarmConfProfileExtEntry * adslLineAlarmConfProfileExtEntry_pt;
- #endif
- adslLineStatusInfo * adslLineStatusInfo_pt;
- adslLineRateInfo * adslLineRateInfo_pt;
- adslLineInfo * adslLineInfo_pt;
- adslNearEndPerfStats * adslNearEndPerfStats_pt;
- adslFarEndPerfStats * adslFarEndPerfStats_pt;
- adslATUCSubcarrierInfo * adslATUCSubcarrierInfo_pt;
- adslATURSubcarrierInfo * adslATURSubcarrierInfo_pt;
- adslPowerSpectralDensity * adslPowerSpectralDensity_pt;
-}structpts;
-
-#endif /* ] __IFXMIPS_MEI_APP_IOCTL_H */
+++ /dev/null
-/******************************************************************************
-**
-** FILE NAME : ifxmips_mei_bsp.h
-** PROJECT : Danube
-** MODULES : MEI
-**
-** DATE : 1 Jan 2006
-** AUTHOR : TC Chen
-** DESCRIPTION : MEI Driver
-** COPYRIGHT : Copyright (c) 2006
-** Infineon Technologies AG
-** Am Campeon 1-12, 85579 Neubiberg, Germany
-**
-** This program is free software; you can redistribute it and/or modify
-** it under the terms of the GNU General Public License as published by
-** the Free Software Foundation; either version 2 of the License, or
-** (at your option) any later version.
-**
-** HISTORY
-** $Version $Date $Author $Comment
-*******************************************************************************/
-#ifndef _IFXMIPS_MEI_BSP_H_
-#define _IFXMIPS_MEI_BSP_H_
-
-/*** Register address offsets, relative to MEI_SPACE_ADDRESS ***/
-#define MEI_DATA_XFR_OFFSET (0x0000)
-#define MEI_VERSION_OFFSET (0x0004)
-#define MEI_ARC_GP_STAT_OFFSET (0x0008)
-#define MEI_DATA_XFR_STAT_OFFSET (0x000C)
-#define MEI_XFR_ADDR_OFFSET (0x0010)
-#define MEI_MAX_WAIT_OFFSET (0x0014)
-#define MEI_TO_ARC_INT_OFFSET (0x0018)
-#define ARC_TO_MEI_INT_OFFSET (0x001C)
-#define ARC_TO_MEI_INT_MASK_OFFSET (0x0020)
-#define MEI_DEBUG_WAD_OFFSET (0x0024)
-#define MEI_DEBUG_RAD_OFFSET (0x0028)
-#define MEI_DEBUG_DATA_OFFSET (0x002C)
-#define MEI_DEBUG_DEC_OFFSET (0x0030)
-#define MEI_CONFIG_OFFSET (0x0034)
-#define MEI_RST_CONTROL_OFFSET (0x0038)
-#define MEI_DBG_MASTER_OFFSET (0x003C)
-#define MEI_CLK_CONTROL_OFFSET (0x0040)
-#define MEI_BIST_CONTROL_OFFSET (0x0044)
-#define MEI_BIST_STAT_OFFSET (0x0048)
-#define MEI_XDATA_BASE_SH_OFFSET (0x004c)
-#define MEI_XDATA_BASE_OFFSET (0x0050)
-#define MEI_XMEM_BAR_BASE_OFFSET (0x0054)
-#define MEI_XMEM_BAR0_OFFSET (0x0054)
-#define MEI_XMEM_BAR1_OFFSET (0x0058)
-#define MEI_XMEM_BAR2_OFFSET (0x005C)
-#define MEI_XMEM_BAR3_OFFSET (0x0060)
-#define MEI_XMEM_BAR4_OFFSET (0x0064)
-#define MEI_XMEM_BAR5_OFFSET (0x0068)
-#define MEI_XMEM_BAR6_OFFSET (0x006C))
-#define MEI_XMEM_BAR7_OFFSET (0x0070)
-#define MEI_XMEM_BAR8_OFFSET (0x0074)
-#define MEI_XMEM_BAR9_OFFSET (0x0078)
-#define MEI_XMEM_BAR10_OFFSET (0x007C)
-#define MEI_XMEM_BAR11_OFFSET (0x0080)
-#define MEI_XMEM_BAR12_OFFSET (0x0084)
-#define MEI_XMEM_BAR13_OFFSET (0x0088)
-#define MEI_XMEM_BAR14_OFFSET (0x008C)
-#define MEI_XMEM_BAR15_OFFSET (0x0090)
-#define MEI_XMEM_BAR16_OFFSET (0x0094)
-
-#define WHILE_DELAY 20000
-/*
-** Define where in ME Processor's memory map the Stratify chip lives
-*/
-
-#define MAXSWAPSIZE 8 * 1024 //8k *(32bits)
-
-// Mailboxes
-#define MSG_LENGTH 16 // x16 bits
-#define YES_REPLY 1
-#define NO_REPLY 0
-
-#define CMV_TIMEOUT 1000 //jiffies
-
-// Block size per BAR
-#define SDRAM_SEGMENT_SIZE (64*1024)
-// Number of Bar registers
-#define MAX_BAR_REGISTERS (17)
-
-#define XDATA_REGISTER (15)
-
-#define IFXMIPS_MEI_IOCTL_CMV_WINHOST IFX_ADSL_IOC_CMV_WINHOST
-
-#define IFXMIPS_MEI_IOCTL_CMV_READ IFX_ADSL_IOC_CMV_READ
-#define IFXMIPS_MEI_IOCTL_CMV_WRITE IFX_ADSL_IOC_CMV_WRITE
-
-#define IFXMIPS_MEI_IOCTL_GET_BASE_ADDRESS IFX_ADSL_IOC_GET_BASE_ADDRESS
-
-// ARC register addresss
-#define ARC_STATUS 0x0
-#define ARC_LP_START 0x2
-#define ARC_LP_END 0x3
-#define ARC_DEBUG 0x5
-#define ARC_INT_MASK 0x10A
-
-#define IRAM0_BASE (0x00000)
-#define IRAM1_BASE (0x04000)
-#define BRAM_BASE (0x0A000)
-
-#define ADSL_BASE (0x20000)
-#define CRI_BASE (ADSL_BASE + 0x11F00)
-#define CRI_CCR0 (CRI_BASE + 0x00)
-#define CRI_RST (CRI_BASE + 0x04*4)
-#define ADSL_DILV_BASE (ADSL_BASE+0x20000)
-
-//
-#define IRAM0_ADDR_BIT_MASK 0xFFF
-#define IRAM1_ADDR_BIT_MASK 0xFFF
-#define BRAM_ADDR_BIT_MASK 0xFFF
-#define RX_DILV_ADDR_BIT_MASK 0x1FFF
-
-/*** Bit definitions ***/
-
-#define FALSE 0
-#define TRUE 1
-#define BIT0 1<<0
-#define BIT1 1<<1
-#define BIT2 1<<2
-#define BIT3 1<<3
-#define BIT4 1<<4
-#define BIT5 1<<5
-#define BIT6 1<<6
-#define BIT7 1<<7
-#define BIT8 1<<8
-#define BIT9 1<<9
-#define BIT10 1<<10
-#define BIT11 1<<11
-#define BIT12 1<<12
-#define BIT13 1<<13
-#define BIT14 1<<14
-#define BIT15 1<<15
-#define BIT16 1<<16
-#define BIT17 1<<17
-#define BIT18 1<<18
-#define BIT19 1<<19
-#define BIT20 1<<20
-#define BIT21 1<<21
-#define BIT22 1<<22
-#define BIT23 1<<23
-#define BIT24 1<<24
-#define BIT25 1<<25
-#define BIT26 1<<26
-#define BIT27 1<<27
-#define BIT28 1<<28
-#define BIT29 1<<29
-#define BIT30 1<<30
-#define BIT31 1<<31
-
-// CRI_CCR0 Register definitions
-#define CLK_2M_MODE_ENABLE BIT6
-#define ACL_CLK_MODE_ENABLE BIT4
-#define FDF_CLK_MODE_ENABLE BIT2
-#define STM_CLK_MODE_ENABLE BIT0
-
-// CRI_RST Register definitions
-#define FDF_SRST BIT3
-#define MTE_SRST BIT2
-#define FCI_SRST BIT1
-#define AAI_SRST BIT0
-
-// MEI_TO_ARC_INTERRUPT Register definitions
-#define MEI_TO_ARC_INT1 BIT3
-#define MEI_TO_ARC_INT0 BIT2
-#define MEI_TO_ARC_CS_DONE BIT1 //need to check
-#define MEI_TO_ARC_MSGAV BIT0
-
-// ARC_TO_MEI_INTERRUPT Register definitions
-#define ARC_TO_MEI_INT1 BIT8
-#define ARC_TO_MEI_INT0 BIT7
-#define ARC_TO_MEI_CS_REQ BIT6
-#define ARC_TO_MEI_DBG_DONE BIT5
-#define ARC_TO_MEI_MSGACK BIT4
-#define ARC_TO_MEI_NO_ACCESS BIT3
-#define ARC_TO_MEI_CHECK_AAITX BIT2
-#define ARC_TO_MEI_CHECK_AAIRX BIT1
-#define ARC_TO_MEI_MSGAV BIT0
-
-// ARC_TO_MEI_INTERRUPT_MASK Register definitions
-#define GP_INT1_EN BIT8
-#define GP_INT0_EN BIT7
-#define CS_REQ_EN BIT6
-#define DBG_DONE_EN BIT5
-#define MSGACK_EN BIT4
-#define NO_ACC_EN BIT3
-#define AAITX_EN BIT2
-#define AAIRX_EN BIT1
-#define MSGAV_EN BIT0
-
-#define MEI_SOFT_RESET BIT0
-
-#define HOST_MSTR BIT0
-
-#define JTAG_MASTER_MODE 0x0
-#define MEI_MASTER_MODE HOST_MSTR
-
-// MEI_DEBUG_DECODE Register definitions
-#define MEI_DEBUG_DEC_MASK (0x3)
-#define MEI_DEBUG_DEC_AUX_MASK (0x0)
-#define MEI_DEBUG_DEC_DMP1_MASK (0x1)
-#define MEI_DEBUG_DEC_DMP2_MASK (0x2)
-#define MEI_DEBUG_DEC_CORE_MASK (0x3)
-
-#define AUX_STATUS (0x0)
-// ARC_TO_MEI_MAILBOX[11] is a special location used to indicate
-// page swap requests.
-#define MEI_TO_ARC_MAILBOX (0xDFD0)
-#define MEI_TO_ARC_MAILBOXR (MEI_TO_ARC_MAILBOX + 0x2C)
-
-#define ARC_TO_MEI_MAILBOX (0xDFA0)
-#define ARC_MEI_MAILBOXR (ARC_TO_MEI_MAILBOX + 0x2C)
-
-// Codeswap request messages are indicated by setting BIT31
-#define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK (0x80000000)
-
-// Clear Eoc messages received are indicated by setting BIT17
-#define OMB_CLEAREOC_INTERRUPT_CODE (0x00020000)
-
-/*
-** Swap page header
-*/
-// Page must be loaded at boot time if size field has BIT31 set
-#define BOOT_FLAG (BIT31)
-#define BOOT_FLAG_MASK ~BOOT_FLAG
-
-#define FREE_RELOAD 1
-#define FREE_SHOWTIME 2
-#define FREE_ALL 3
-
-// marcos
-#define IFXMIPS_WRITE_REGISTER_L(data,addr) do{ *((volatile u32*)(addr)) = (u32)(data);} while (0)
-#define IFXMIPS_READ_REGISTER_L(addr) (*((volatile u32*)(addr)))
-#define SET_BIT(reg, mask) reg |= (mask)
-#define CLEAR_BIT(reg, mask) reg &= (~mask)
-#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask)
-#define SET_BITS(reg, mask) SET_BIT(reg, mask)
-#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);}
-
-#define ALIGN_SIZE ( 1L<<10 ) //1K size align
-#define MEM_ALIGN(addr) (((addr) + ALIGN_SIZE - 1) & ~ (ALIGN_SIZE -1) )
-
-// swap marco
-#define MEI_HALF_WORD_SWAP(data) {data = ((data & 0xffff)<<16) + ((data & 0xffff0000)>>16);}
-#define MEI_BYTE_SWAP(data) {data = ((data & 0xff)<<24) + ((data & 0xff00)<<8)+ ((data & 0xff0000)>>8)+ ((data & 0xff000000)>>24);}
-
-// Swap page header describes size in 32-bit words, load location, and image offset
-// for program and/or data segments
-typedef struct _arc_swp_page_hdr {
- u32 p_offset; //Offset bytes of progseg from beginning of image
- u32 p_dest; //Destination addr of progseg on processor
- u32 p_size; //Size in 32-bitwords of program segment
- u32 d_offset; //Offset bytes of dataseg from beginning of image
- u32 d_dest; //Destination addr of dataseg on processor
- u32 d_size; //Size in 32-bitwords of data segment
-} ARC_SWP_PAGE_HDR;
-
-/*
-** Swap image header
-*/
-#define GET_PROG 0 // Flag used for program mem segment
-#define GET_DATA 1 // Flag used for data mem segment
-
-// Image header contains size of image, checksum for image, and count of
-// page headers. Following that are 'count' page headers followed by
-// the code and/or data segments to be loaded
-typedef struct _arc_img_hdr {
- u32 size; // Size of binary image in bytes
- u32 checksum; // Checksum for image
- u32 count; // Count of swp pages in image
- ARC_SWP_PAGE_HDR page[1]; // Should be "count" pages - '1' to make compiler happy
-} ARC_IMG_HDR;
-
-typedef struct smmu_mem_info {
- int type;
- unsigned long nCopy;
- unsigned long size;
- unsigned char *address;
- unsigned char *org_address;
-} smmu_mem_info_t;
-
-typedef struct ifxmips_mei_device_private {
- int modem_ready;
- int arcmsgav;
- int cmv_reply;
- int cmv_waiting;
- // Mei to ARC CMV count, reply count, ARC Indicator count
- int indicator_count;
- int cmv_count;
- int reply_count;
- unsigned long image_size;
- int nBar;
- u16 Recent_indicator[MSG_LENGTH];
-
- u16 CMV_RxMsg[MSG_LENGTH] __attribute__ ((aligned (4)));
-
- smmu_mem_info_t adsl_mem_info[MAX_BAR_REGISTERS];
- ARC_IMG_HDR *img_hdr;
- // to wait for arc cmv reply, sleep on wait_queue_arcmsgav;
- wait_queue_head_t wait_queue_arcmsgav;
- wait_queue_head_t wait_queue_modemready;
- MEI_mutex_t mei_cmv_sema;
-} ifxmips_mei_device_private_t;
-
-#endif //_IFXMIPS_MEI_BSP_H_
+++ /dev/null
-/******************************************************************************
-**
-** FILE NAME : ifxmips_mei_ioctl.h
-** PROJECT : Danube
-** MODULES : MEI
-**
-** DATE : 1 Jan 2006
-** AUTHOR : TC Chen
-** DESCRIPTION : MEI Driver
-** COPYRIGHT : Copyright (c) 2006
-** Infineon Technologies AG
-** Am Campeon 1-12, 85579 Neubiberg, Germany
-**
-** This program is free software; you can redistribute it and/or modify
-** it under the terms of the GNU General Public License as published by
-** the Free Software Foundation; either version 2 of the License, or
-** (at your option) any later version.
-**
-** HISTORY
-** $Version $Date $Author $Comment
-*******************************************************************************/
-#ifndef _IFXMIPS_MEI_IOCTL_H
-#define _IFXMIPS_MEI_IOCTL_H
-
-/////////////////////////////////////////////////////////////////////////////////////////////////////
-#define PCM_BUFF_SIZE 1024 //bytes
-// interrupt numbers
-
-#if !(defined(_IFXMIPS_ADSL_APP) || defined (_AMAZON_ADSL_APP))
-
-// Number of intervals
-#define INTERVAL_NUM 192 //two days
-typedef struct ifxmips_mei_mib {
- struct list_head list;
- struct timeval start_time; //start of current interval
-
- int AtucPerfLof;
- int AtucPerfLos;
- int AtucPerfEs;
- int AtucPerfInit;
-
- int AturPerfLof;
- int AturPerfLos;
- int AturPerfLpr;
- int AturPerfEs;
-
- int AturChanPerfRxBlk;
- int AturChanPerfTxBlk;
- int AturChanPerfCorrBlk;
- int AturChanPerfUncorrBlk;
-
- //RFC-3440
- int AtucPerfStatFastR;
- int AtucPerfStatFailedFastR;
- int AtucPerfStatSesL;
- int AtucPerfStatUasL;
- int AturPerfStatSesL;
- int AturPerfStatUasL;
-} ifxmips_mei_mib;
-
-typedef struct adslChanPrevTxRate {
- u32 adslAtucChanPrevTxRate;
- u32 adslAturChanPrevTxRate;
-} adslChanPrevTxRate;
-
-typedef struct adslPhysCurrStatus {
- u32 adslAtucCurrStatus;
- u32 adslAturCurrStatus;
-} adslPhysCurrStatus;
-
-typedef struct ChanType {
- int interleave;
- int fast;
- int bearchannel0;
- int bearchannel1;
-} ChanType;
-
-typedef struct mib_previous_read {
- u16 ATUC_PERF_ESS;
- u16 ATUR_PERF_ESS;
- u32 ATUR_CHAN_RECV_BLK;
- u16 ATUR_CHAN_CORR_BLK_INTL;
- u16 ATUR_CHAN_CORR_BLK_FAST;
- u16 ATUR_CHAN_UNCORR_BLK_INTL;
- u16 ATUR_CHAN_UNCORR_BLK_FAST;
- u16 ATUC_PERF_STAT_FASTR;
- u16 ATUC_PERF_STAT_FAILED_FASTR;
- u16 ATUC_PERF_STAT_SESL;
- u16 ATUC_PERF_STAT_UASL;
- u16 ATUR_PERF_STAT_SESL;
-} mib_previous_read;
-
-typedef struct mib_flags_pretime {
- struct timeval ATUC_PERF_LOSS_PTIME;
- struct timeval ATUC_PERF_LOFS_PTIME;
- struct timeval ATUR_PERF_LOSS_PTIME;
- struct timeval ATUR_PERF_LOFS_PTIME;
- struct timeval ATUR_PERF_LPR_PTIME;
-} mib_flags_pretime;
-
- // cmv message structures
-#define MP_PAYLOAD_SIZE 12
-typedef struct mpmessage {
- u16 iFunction;
- u16 iGroup;
- u16 iAddress;
- u16 iIndex;
- u16 iPayload[MP_PAYLOAD_SIZE];
-} MPMessage;
-#endif
-
-typedef struct meireg {
- u32 iAddress;
- u32 iData;
-} meireg;
-
-#define MEIDEBUG_BUFFER_SIZES 50
-typedef struct meidebug {
- u32 iAddress;
- u32 iCount;
- u32 buffer[MEIDEBUG_BUFFER_SIZES];
-} meidebug;
-
-//==============================================================================
-// Group definitions
-//==============================================================================
-#define OPTN 5
-#define CNFG 8
-#define CNTL 1
-#define STAT 2
-#define RATE 6
-#define PLAM 7
-#define INFO 3
-#define TEST 4
-//==============================================================================
-// Opcode definitions
-//==============================================================================
-#define H2D_CMV_READ 0x00
-#define H2D_CMV_WRITE 0x04
-#define H2D_CMV_INDICATE_REPLY 0x10
-#define H2D_ERROR_OPCODE_UNKNOWN 0x20
-#define H2D_ERROR_CMV_UNKNOWN 0x30
-
-#define D2H_CMV_READ_REPLY 0x01
-#define D2H_CMV_WRITE_REPLY 0x05
-#define D2H_CMV_INDICATE 0x11
-#define D2H_ERROR_OPCODE_UNKNOWN 0x21
-#define D2H_ERROR_CMV_UNKNOWN 0x31
-#define D2H_ERROR_CMV_READ_NOT_AVAILABLE 0x41
-#define D2H_ERROR_CMV_WRITE_ONLY 0x51
-#define D2H_ERROR_CMV_READ_ONLY 0x61
-
-#define H2D_DEBUG_READ_DM 0x02
-#define H2D_DEBUG_READ_PM 0x06
-#define H2D_DEBUG_WRITE_DM 0x0a
-#define H2D_DEBUG_WRITE_PM 0x0e
-
-#define D2H_DEBUG_READ_DM_REPLY 0x03
-#define D2H_DEBUG_READ_FM_REPLY 0x07
-#define D2H_DEBUG_WRITE_DM_REPLY 0x0b
-#define D2H_DEBUG_WRITE_FM_REPLY 0x0f
-#define D2H_ERROR_ADDR_UNKNOWN 0x33
-
-#define D2H_AUTONOMOUS_MODEM_READY_MSG 0xf1
-//==============================================================================
-// INFO register address field definitions
-//==============================================================================
-
-#define INFO_TxState 0
-#define INFO_RxState 1
-#define INFO_TxNextState 2
-#define INFO_RxNextState 3
-#define INFO_TxStateJumpFrom 4
-#define INFO_RxStateJumpFrom 5
-
-#define INFO_ReverbSnrBuf 8
-#define INFO_ReverbEchoSnrBuf 9
-#define INFO_MedleySnrBuf 10
-#define INFO_RxShowtimeSnrBuf 11
-#define INFO_DECdelay 12
-#define INFO_DECExponent 13
-#define INFO_DECTaps 14
-#define INFO_AECdelay 15
-#define INFO_AECExponent 16
-#define INFO_AECTaps 17
-#define INFO_TDQExponent 18
-#define INFO_TDQTaps 19
-#define INFO_FDQExponent 20
-#define INFO_FDQTaps 21
-#define INFO_USBat 22
-#define INFO_DSBat 23
-#define INFO_USFineGains 24
-#define INFO_DSFineGains 25
-#define INFO_BitloadFirstChannel 26
-#define INFO_BitloadLastChannel 27
-#define INFO_PollEOCData 28 // CO specific
-#define INFO_CSNRMargin 29 // CO specific
-#define INFO_RCMsgs1 30
-#define INFO_RMsgs1 31
-#define INFO_RMsgRA 32
-#define INFO_RCMsgRA 33
-#define INFO_RMsg2 34
-#define INFO_RCMsg2 35
-#define INFO_BitLoadOK 36
-#define INFO_RCRates1 37
-#define INFO_RRates1Tab 38
-#define INFO_RMsgs1Tab 39
-#define INFO_RMsgRATab 40
-#define INFO_RRatesRA 41
-#define INFO_RCRatesRA 42
-#define INFO_RRates2 43
-#define INFO_RCRates2 44
-#define INFO_PackedRMsg2 45
-#define INFO_RxBitSwapFlag 46
-#define INFO_TxBitSwapFlag 47
-#define INFO_ShowtimeSNRUpdateCount 48
-#define INFO_ShowtimeFDQUpdateCount 49
-#define INFO_ShowtimeDECUpdateCount 50
-#define INFO_CopyRxBuffer 51
-#define INFO_RxToneBuf 52
-#define INFO_TxToneBuf 53
-#define INFO_Version 54
-#define INFO_TimeStamp 55
-#define INFO_feVendorID 56
-#define INFO_feSerialNum 57
-#define INFO_feVersionNum 58
-#define INFO_BulkMemory 59 //Points to start of bulk memory
-#define INFO_neVendorID 60
-#define INFO_neVersionNum 61
-#define INFO_neSerialNum 62
-
-//==============================================================================
-// RATE register address field definitions
-//==============================================================================
-
-#define RATE_UsRate 0
-#define RATE_DsRate 1
-
-//==============================================================================
-// PLAM (Physical Layer Management) register address field definitions
-// (See G997.1 for reference)
-//==============================================================================
-
- // ///
- // Failure Flags ///
- // ///
-
-#define PLAM_NearEndFailureFlags 0
-#define PLAM_FarEndFailureFlags 1
-
- // ///
- // Near End Failure Flags Bit Definitions ///
- // ///
-
-// ADSL Failures ///
-#define PLAM_LOS_FailureBit 0x0001
-#define PLAM_LOF_FailureBit 0x0002
-#define PLAM_LPR_FailureBit 0x0004
-#define PLAM_RFI_FailureBit 0x0008
-
-// ATM Failures ///
-#define PLAM_NCD_LP0_FailureBit 0x0010
-#define PLAM_NCD_LP1_FailureBit 0x0020
-#define PLAM_LCD_LP0_FailureBit 0x0040
-#define PLAM_LCD_LP1_FailureBit 0x0080
-
-#define PLAM_NCD_BC0_FailureBit 0x0100
-#define PLAM_NCD_BC1_FailureBit 0x0200
-#define PLAM_LCD_BC0_FailureBit 0x0400
-#define PLAM_LCD_BC1_FailureBit 0x0800
- // ///
- // Performance Counts ///
- // ///
-
-#define PLAM_NearEndCrcCnt 2
-#define PLAM_CorrectedRSErrors 3
-
-#define PLAM_NearEndECSCnt 6
-#define PLAM_NearEndESCnt 7
-#define PLAM_NearEndSESCnt 8
-#define PLAM_NearEndLOSSCnt 9
-#define PLAM_NearEndUASLCnt 10
-
-#define PLAM_NearEndHECErrCnt 11
-
-#define PLAM_NearEndHECTotCnt 16
-#define PLAM_NearEndCellTotCnt 18
-#define PLAM_NearEndSfCntLSW 20
-#define PLAM_NearEndSfCntMSW 21
-
-#define PLAM_FarEndFebeCnt 24
-
-#define PLAM_FarEndFecCnt 28
-
-#define PLAM_FarEndFECSCnt 32
-#define PLAM_FarEndESCnt 33
-#define PLAM_FarEndSESCnt 34
-#define PLAM_FarEndLOSSCnt 35
-#define PLAM_FarEndUASLCnt 36
-
-#define PLAM_FarEndHECErrCnt 37
-
-#define PLAM_FarEndHECTotCnt 41
-
-#define PLAM_FarEndCellTotCnt 43
-
-#define PLAM_SNRMargin_0_1db 45
-
-#define PLAM_SNRMargin 46
-
-//==============================================================================
-// CNTL register address and bit field definitions
-//==============================================================================
-
-#define CNTL_ModemControl 0
-
-#define CNTL_ModemReset 0x0
-#define CNTL_ModemStart 0x2
-
-//==============================================================================
-// STAT register address and bit field definitions
-//==============================================================================
-
-#define STAT_MacroState 0
-#define STAT_Mode 1
-#define STAT_DMTFramingMode 2
-#define STAT_SleepState 3
-#define STAT_Misc 4
-#define STAT_FailureState 5
-
-////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
- // STAT_OLRStatus provides status of OLR
- //16-bit STAT_OLRStatus_DS
- // [1:0] : OLR status 00=IDLE, 01=OLR_IN_PROGRESS, 10=OLR_Completed, 11=OLR_Aborted
- // [3:2]: Reserved
- // [5:4]: OLR_Type (1:bitswap; 2: DRR; 3: SRA)
- // [7:6]: Reserved
- // [10:8]: >0=Request. 0=not. For DS, # of request transmissions/retransmissions (3 bits).
- // [11]: 1=Receive Response, 0=not
- // [15:12]: Reserved
- //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
- ///
-#define STAT_OLRStatus_DS 6
-
-////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
- // STAT_OLRStatus provides status of OLR
- // 16-bit STAT_OLRStatus_US CMV
- // [1:0] : OLR status 00=IDLE, 01=OLR_IN_PROGRESS, 10=OLR_Completed, 11=OLR_Aborted
- // [3:2]: Reserved
- // [5:4]: OLR_Type (1:bitswap; 2: DRR; 3: SRA)
- // [7:6]: Reserved
- // [8]: 1=Request Received. 0=not.
- // [10:9]: Reserved
- // [11]: 1=Response Sent, 0=not
- // [15:12]: Reserved
- //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-///
-#define STAT_OLRStatus_US 7
-
-////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
- // STAT_PMStatus provides status of PM
- // 16-bit STAT_PMStatus CMV
- // [1:0] : PM Status 00=IDLE, 01=PM_IN_PROGRESS, 10=PM_Completed, 11=PM_Aborted
- // [2] : 0=ATU_R initiated PM; 1 = ATU_C initiated PM
- // [3]: Reserved
- // [5:4]: PM_Type (1:Simple Request; 2: L2 request; 3: L2 trim)
- // [7:6]: Reserved
- // [10:8]: >0=Request. 0=not. # of request transmissions/retransmissions (3 bits).
- // [11]: 1=Response, 0=not
- // [15:12]: Reserved
- //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
- ///
-#define STAT_PMStatus 8
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
- // 16-bit STAT_OLRError_DS, STAT_OLRError_US, STAT_PMError
- // [3:0]: OLR/PM response reason code
- // [7:4]: OLR/PM Internal error code
- // [15:8]: OLR/PM Reserved for future
- //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
- ///
-#define STAT_OLRError_DS 9
-#define STAT_OLRError_US 10
-#define STAT_PMError 11
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// STAT_MacroState
-// MacroState reflects the high level state of the modem
-
-#define STAT_InitState 0x0000
-#define STAT_ReadyState 0x0001
-#define STAT_FailState 0x0002
-#define STAT_IdleState 0x0003
-#define STAT_QuietState 0x0004
-#define STAT_GhsState 0x0005
-#define STAT_FullInitState 0x0006
-#define STAT_ShowTimeState 0x0007
-#define STAT_FastRetrainState 0x0008
-#define STAT_LoopDiagMode 0x0009
-#define STAT_ShortInit 0x000A // Bis short initialization ///
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// STAT_Mode
-// ConfigurationMode indicates the mode of the current ADSL Link. In general, a modem may use
-// G.Hs or some other mechanism to negotiate the specific mode of operation.
-// The OPTN_modeControl CMV is used to select a set of desired modes.
-// The STAT_Mode CMV indicates which mode was actually selected.
-
-#define STAT_ConfigMode_T1413 0x0001
-#define STAT_ConfigMode_G992_2_AB 0x0002
-#define STAT_ConfigMode_G992_1_A 0x0004
-#define STAT_ConfigMode_G992_1_B 0x0008
-#define STAT_ConfigMode_G992_1_C 0x0010
-#define STAT_ConfigMode_G992_2_C 0x0020
-
-#define STAT_ConfigMode_G992_3_A 0x0100
-#define STAT_ConfigMode_G992_3_B 0x0200
-#define STAT_ConfigMode_G992_3_I 0x0400
-#define STAT_ConfigMode_G992_3_J 0x0800
-#define STAT_ConfigMode_G992_3_L 0x1000
-
-#define STAT_ConfigMode_G992_4_A 0x2000
-#define STAT_ConfigMode_G992_4_I 0x4000
-
-#define STAT_ConfigMode_G992_5 0x8000
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// STAT_DMTFramingMode
-// FramingMode indicates the DMT framing mde negotiated during initialization. The framing mode
-// status is not applicable in BIS mode and its value is undefined
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-#define STAT_FramingModeMask 0x0003
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// STAT_Misc
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-#define STAT_OverlappedSpectrum 0x0008
-#define STAT_TCM 0x0010
-#define STAT_TDQ_at_1104 0x0020
-#define STAT_T1413_Signal_Detected 0x0040
-#define STAT_AnnexL_US_Mask1_PSD 0x1000 //indicate we actually selected G992.3 AnnexL US PSD mask1
-#define STAT_AnnexL_US_Mask2_PSD 0x2000 //indicate we actually selected G992.3 AnnexL US PSD mask2
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// STAT_FailureState
-// when the MacroSTate indicates the fail state, FailureState provides a failure code
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-#define E_CODE_NO_ERROR 0
-#define E_CODE_BAT_TX 1 // TX BAT table is incorrect */
-#define E_CODE_BAT_RX 2 // RX BAT table is incorrect */
-#define E_CODE_PROFILE 3 // profile is not selected in fast retrain */
-#define E_CODE_TX_AOC_FIFO_OVERFLOW 4
-#define E_CODE_TRUNCATE_FR 5 //Fast Retrain truncated due to no stored profiles*/
-#define E_CODE_BITLOAD 6 // bit loading fails */
-#define E_CODE_ST_ERROR 7 // showtime CRC error */
-#define E_CODE_RESERVED 8 // using parameters reserved by the ITU-T */
-#define E_CODE_C_TONES 9 // detected C_TONES */
-#define E_CODE_CODESWAP_ERR 10 // codeswap not finished in time */
-#define E_CODE_FIFO_OVERFLOW 11 // we have run out of fifo space */
-#define E_CODE_C_BG_DECODE_ERR 12 // error in decoding C-BG message */
-#define E_CODE_C_RATES2_DECODE_ERR 13 // error in decoding C-MSGS2 and C-RATES2 */
-#define E_CODE_RCMedleyRx_C_SEGUE2_Failure 14 // Timeout after RCMedleyRx waiting for C_SEGUE2 */
-#define E_CODE_RReverbRATx_C_SEGUE2_Failure 15 // Timeout after RReverbRATx waiting for C_SEGUE2 */
-#define E_CODE_RReverb3Tx_C_SEGUE1_Failure 16 // Timeout after RReverb3Tx waiting for C_SEGUE1 */
-#define E_CODE_RCCRC2Rx_C_RATES1_DECOD_ERR 17 // Received CRC not equal to computed CRC */
-#define E_CODE_RCCRC1Rx_C_RATES1_DECOD_ERR 18 // Received CRC not equal to computed CRC */
-#define E_CODE_RReverb5Tx_C_SEGUE2_Failure 19 // Timeout after RReverb5Tx waiting for C_SEGUE2 */
-#define E_CODE_RReverb6Tx_C_SEGUE3_Failure 20 // Timeout after RReverb6Tx waiting for C_SEGUE3 */
-#define E_CODE_RSegue5Tx_C_SEGUE3_Failure 21 // Timeout after RSegue5Tx waiting for C_SEGUE3 */
-#define E_CODE_RCReverb5Rx_C_SEGUE_Failure 22 // Timeout after RCReverb5Rx waiting for C_SEGUE */
-#define E_CODE_RCReverbRARx_C_SEGUE2_Failure 23 // Timeout after RCReverbRARx waiting for C_SEGUE2 */
-#define E_CODE_RCCRC4Rx_CMSGS2_DECOD_ERR 24 // Received CRC not equal to computed CRC */
-#define E_CODE_RCCRC5Rx_C_BG_DECOD_ERR 25 // Received CRC not equal to computed CRC */
-#define E_CODE_RCCRC3Rx_DECOD_ERR 26 // Received CRC not equal to computed CRC */
-#define E_CODE_RCPilot3_DEC_PATH_DEL_TIMEOUT 27 // DEC Path Delay timeout */
-#define E_CODE_RCPilot3_DEC_TRAINING_TIMEOUT 28 // DEC Training timeout */
-#define E_CODE_RCReverb3Rx_C_SEGUE1_Failure 29 // Timeout after RCReverb3Rx waiting for C_SEGUE1 */
-#define E_CODE_RCReverb2Rx_SignalEnd_Failure 30 // Timeout waiting for the end of RCReverb2Rx signal */
-#define E_CODE_RQuiet2_SignalEnd_Failure 31 // Timeout waiting for the end of RQuiet2 signal */
-#define E_CODE_RCReverbFR1Rx_Failure 32 // Timeout waiting for the end of RCReverbFR1Rx signal */
-#define E_CODE_RCPilotFR1Rx_SignalEnd_Failure 33 // Timeout waiting for the end of RCPilotFR1Rx signal */
-#define E_CODE_RCReverbFR2Rx_C_Segue_Failure 34 // Timeout after RCReverbFR2Rx waiting for C_SEGUE */
-#define E_CODE_RCReverbFR5Rx_SignalEnd_TIMEOUT 35 // Timeout waiting for the end of RCReverbFR5Rx signal */
-#define E_CODE_RCReverbFR6Rx_C_SEGUE_Failure 36 // Timeout after RCReverbFR6Rx waiting for C_SEGUE */
-#define E_CODE_RCReverbFR8Rx_C_SEGUE_FR4_Failure 37 // Timeout after RCReverbFR8Rx waiting for C_SEGUE_FR4 */
-#define E_CODE_RCReverbFR8Rx_No_PROFILE 38 // Timeout since no profile was selected */
-#define E_CODE_RCReverbFR8Rx_SignalEnd_TIMEOUT 39 // Timeout waiting for the end of RCReverbFR8Rx signal */
-#define E_CODE_RCCRCFR1_DECOD_ERR 40 // Received CRC not equal to computed CRC */
-#define E_CODE_RCRecovRx_SingnalEnd_TIMEOUT 41 // Timeout waiting for the end of RCRecovRx signal */
-#define E_CODE_RSegueFR5Tx_TX_Not_Ready_TIMEOUT 42 // Timeout after RSegueFR5Tx waiting for C_SEGUE2 */
-#define E_CODE_RRecovTx_SignalEnd_TIMEOUT 43 // Timeout waiting for the end of RRecovTx signal */
-#define E_CODE_RCMedleyFRRx_C_SEGUE2_Failure 44 // Timeout after RCMedleyFRRx waiting for C_SEGUE2 */
-#define E_CODE_CONFIGURATION_PARAMETERS_ERROR 45 // one of the configuration parameters do not meet the standard */
-#define E_CODE_BAD_MEM_ACCESS 46
-#define E_CODE_BAD_INSTRUCTION_ACCESS 47
-#define E_CODE_TX_EOC_FIFO_OVERFLOW 48
-#define E_CODE_RX_EOC_FIFO_OVERFLOW 49
-#define E_CODE_GHS_CD_FLAG_TIME_OUT 50 // Timeout when transmitting Flag in handshake cleardown */
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-//STAT_OLRStatus:
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-#define STAT_OLRPM_IDLE 0x0000
-#define STAT_OLRPM_IN_PROGRESS 0x0001
-#define STAT_OLRPM_COMPLETE 0x0002
-#define STAT_OLRPM_ABORTED 0x0003
-#define STAT_OLRPM_RESPONSE 0x0800
-
-#define STAT_OLR_BITSWAP 0x0010
-#define STAT_OLR_DRR 0x0020
-#define STAT_OLR_SRA 0x0030
-
-//STAT_PMStatus_US:
-#define STAT_PM_CO_REQ 0x0004
-#define STAT_PM_SIMPLE_REQ 0x0010
-#define STAT_PM_L2_REQ 0x0020
-#define STAT_PM_L2_TRIM_REQ 0x0030
-
-// STAT_OLRError_DS, STAT_OLRError_US
-//4 bit response reason code:
-#define RESP_BUSY 0x01
-#define RESP_INVALID_PARAMETERS 0x02
-#define RESP_NOT_ENABLED 0x03
-#define RESP_NOT_SUPPORTED 0x04
-
-//4 bit internal error code (common for OLR and PM)
-#define REQ_INVALID_BiGi 0x10
-#define REQ_INVALID_Lp 0x20
-#define REQ_INVALID_Bpn 0x30
-#define REQ_INVALID_FRAMING_CONSTRAINT 0x40
-#define REQ_NOT_IN_L0_STATE 0x50
-#define REQ_NOT_IN_L2_STATE 0x60
-#define REQ_INVALID_PCB 0x70
-#define REQ_VIOLATES_MARGIN 0x80
-
-//STAT_PMError
-//4 bit response reason code:
-#define RESP_STATE_NOT_DESIRED 0x03
-#define RESP_INFEASIBLE_PARAMETERS 0x04
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// OPTN register address and bit field definitions
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-#define OPTN_ModeControl 0
-#define OPTN_DMTLnkCtl 1
-// Reserved 2
-#define OPTN_GhsControl 3
-// Reserved 4
-#define OPTN_PwrManControl 5
-#define OPTN_AnnexControl 6
-#define OPTN_ModeControl1 7
-// Reserved 8
-#define OPTN_StateMachineCtrl 9
-// Reserved 10
-// Reserved 11
-#define OPTN_BisLinkControl 12
-#define OPTN_ATMAddrConfig 13
-#define OPTN_ATMNumCellConfig 14
-
-// Mode control defines the allowable operating modes of an ADSL link. In general, a modem may ///
-// use G.Hs or some other mechanism to negotiate the specific mode of operation. ///
-// The OPTN_ModeControl CMV is used to select a set of desired modes ///
-// The STAT_ModeControl CMV indicates which mode was actually selected ///
-
-// OPTN_ModeControl
-#define OPTN_ConfigMode_T1413 0x0001
-#define OPTN_ConfigMode_G992_2_AB 0x0002
-#define OPTN_ConfigMode_G992_1_A 0x0004
-#define OPTN_ConfigMode_G992_1_B 0x0008
-#define OPTN_ConfigMode_G992_1_C 0x0010
-#define OPTN_ConfigMode_G992_2_C 0x0020
-
-#define OPTN_ConfigMode_G992_3_A 0x0100
-#define OPTN_ConfigMode_G992_3_B 0x0200
-#define OPTN_ConfigMode_G992_3_I 0x0400
-#define OPTN_ConfigMode_G992_3_J 0x0800
-#define OPTN_ConfigMode_G992_3_L 0x1000
-
-#define OPTN_ConfigMode_G992_4_A 0x2000
-#define OPTN_ConfigMode_G992_4_I 0x4000
-
-#define OPTN_ConfigMode_G992_5 0x8000
-
-// OPTN_PwrManControl
-#define OPTN_PwrManWakeUpGhs 0x1
-#define OPTN_PwrManWakeUpFR 0x2
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// OPTN_DMT Link Control
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-#define OPTN_DMT_DualLatency_Dis 0x200
-#define OPTN_DMT_S_Dis 0x100
-#define OPTN_DMT_FRAMINGMODE 0x1
-#define OPTN_DMT_FRAMINGMODE_MASK 0x7
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// OPTN_BIS Link Control
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-#define OPTN_BisLinkContrl_LineProbeDis 0x1
-#define OPTN_BisLinkContrl_DSBlackBitsEn 0x2
-#define OPTN_BisLinkContrl_DiagnosticModeEn 0x4
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// OPTN_GhsControl
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-//
-// for OPTN_GhsControl, we will assign 16bit word as follows
-// bit 0~3: set the control over which start(initial) message CPE will send:
-//
-// BIT: 2 1 0
-// 0 0 1 CLR
-// 0 1 0 MR
-// 0 1 1 MS
-// 1 0 0 MP
-//
-// // bit 4~6: set the control over which message will be sent when we get at lease one CL/CLR exchange
-// BIT: 5 4
-// 0 1 MS
-// 1 0 MR
-// 1 1 MP
-//
-// // bit 15: RT initiated G.hs sample sessions one through eight. Session one is default.
-// BIT: 15
-// 1 means session one
-//
-///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-#define OPTN_GHS_ST_GHS 0x8000
-#define OPTN_GHS_INIT_MASK 0x000F
-#define OPTN_GHS_RESP_MASK 0x00F0
-
-#define OPTN_RTInitTxMsg_CLR 0x0001
-#define OPTN_RTInitTxMsg_MR 0x0002
-#define OPTN_RTInitTxMsg_MS 0x0003
-#define OPTN_RTInitTxMsg_MP 0x0004
-
-#define OPTN_RTRespTxMsg_MS 0x0010
-#define OPTN_RTRespTxMsg_MR 0x0020
-#define OPTN_RTRespTxMsg_MP 0x0030
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// OPTN_AnnexControl
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-// G.992.3 Annex A/L1/L2 US PSD Mask preferred
-
-#define OPTN_G992_3_AnnexA_PreferredModeMask 0x3000
-#define OPTN_G992_3_AnnexA_PreferredModeA 0x0000 // default AnnexA PSD mask ///
-#define OPTN_G992_3_AnnexA_PreferredModeL1 0x1000 // AnnexL wide spectrum upstream PSD mask ///
-#define OPTN_G992_3_AnnexA_PreferredModeL2 0x2000 // AnnexL narrow spectrum upstream PSD mask ///
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-//OPTN_ATMAddrConfig
-// Bits 4:0 are Utopia address for BC1
-// Bits 9:5 are Utopia address for BC0
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-#define OPTN_UTPADDR_BC1 0x001F
-#define OPTN_UTPADDR_BC0 0x03E0
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-//OPTN_ATMNumCellConfig
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-#define OPTN_BC1_NUM_CELL_PAGES 0x000F // Bits 0:3 ///
-#define OPTN_BC0_NUM_CELL_PAGES 0x00F0 // Bits 4:7 ///
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// CNFG register address field ///
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-///////////////////////////////////////////
-// these cmvs are used by bis handshake ///
-///////////////////////////////////////////
-
-// Each of the CNFG_TPS entries points to a structure of type (TPS_TC_BearerChannel_t)
-#define CNFG_TPS_TC_DS0 0
-#define CNFG_TPS_TC_DS1 1
-#define CNFG_TPS_TC_US0 2
-#define CNFG_TPS_TC_US1 3
-
-#define CNFG_HDLC_Overhead_Requirements 4
-
-// Each of the CNFG_PMS entries points to a structure of type (PMS_TC_LatencyPath_t)
-#define CNFG_PMS_TC_DS0 5
-#define CNFG_PMS_TC_DS1 6
-#define CNFG_PMS_TC_US0 7
-#define CNFG_PMS_TC_US1 8
-
-// CNFG_PMD_PARAMETERS points to a structure of type (PMD_params_t)
-#define CNFG_PMD_PARAMETERS 9
-
-////////////////////////////////////////////////////////////
-// these cmvs are used by bis training and showtime code ///
-////////////////////////////////////////////////////////////
-
-////////////////
-// Tx Config ///
-////////////////
-#define CNFG_tx_Cnfg_Nbc 10
-#define CNFG_tx_Cnfg_Nlp 11
-#define CNFG_tx_Cnfg_Rp 12
-#define CNFG_tx_Cnfg_Mp 13
-#define CNFG_tx_Cnfg_Lp 14
-#define CNFG_tx_Cnfg_Tp 15
-#define CNFG_tx_Cnfg_Dp 16
-#define CNFG_tx_Cnfg_Bpn 17
-#define CNFG_tx_Cnfg_FramingMode 18
-#define CNFG_tx_Cnfg_MSGLp 19
-#define CNFG_tx_Cnfg_MSGc 20
-
-////////////////
-// Rx Config ///
-////////////////
-#define CNFG_rx_Cnfg_Nbc 21
-#define CNFG_rx_Cnfg_Nlp 22
-#define CNFG_rx_Cnfg_Rp 23
-#define CNFG_rx_Cnfg_Mp 24
-#define CNFG_rx_Cnfg_Lp 25
-#define CNFG_rx_Cnfg_Tp 26
-#define CNFG_rx_Cnfg_Dp 27
-#define CNFG_rx_Cnfg_Bpn 28
-#define CNFG_rx_Cnfg_FramingMode 29
-#define CNFG_rx_Cnfg_MSGLp 30
-#define CNFG_rx_Cnfg_MSGc 31
-
-#define CNFG_tx_Cnfg_BCnToLPp 32
-#define CNFG_rx_Cnfg_BCnToLPp 33
-
-#endif
+++ /dev/null
-/******************************************************************************
-**
-** FILE NAME : ifxmips_mei_linux.h
-** PROJECT : Danube
-** MODULES : MEI
-**
-** DATE : 1 Jan 2006
-** AUTHOR : TC Chen
-** DESCRIPTION : MEI Driver
-** COPYRIGHT : Copyright (c) 2006
-** Infineon Technologies AG
-** Am Campeon 1-12, 85579 Neubiberg, Germany
-**
-** This program is free software; you can redistribute it and/or modify
-** it under the terms of the GNU General Public License as published by
-** the Free Software Foundation; either version 2 of the License, or
-** (at your option) any later version.
-**
-** HISTORY
-** $Version $Date $Author $Comment
-*******************************************************************************/
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/version.h>
-#include <linux/types.h>
-#include <linux/fs.h>
-#include <linux/mm.h>
-#include <linux/errno.h>
-#include <linux/interrupt.h>
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <asm/semaphore.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <asm/uaccess.h>
-
-#undef CONFIG_DEVFS_FS //165204:henryhsu devfs will make mei open file fail.
-
-#ifdef CONFIG_DEVFS_FS
-#include <linux/devfs_fs_kernel.h>
-#endif
-#ifdef CONFIG_PROC_FS
-#include <linux/proc_fs.h>
-#endif
-
-#include <linux/list.h>
-#include <linux/delay.h>
-#define __LINUX__
-
-#ifdef CONFIG_PROC_FS
-#define PROC_ITEMS 8
-#define MEI_DIRNAME "mei"
-#endif
-
-#include <asm/ifxmips/ifxmips.h>
-#include <asm/ifxmips/ifxmips_irq.h>
-#include <asm/ifxmips/ifxmips_mei.h>
-#include <asm/ifxmips/ifxmips_mei_app.h>
-#include <asm/ifxmips/ifxmips_mei_ioctl.h>
-#include <asm/ifxmips/ifxmips_mei_app_ioctl.h>
-#include <asm/ifxmips/ifxmips_gpio.h>
-#include <asm/ifxmips/ifxmips_led.h>
-#include <asm/ifxmips/ifxmips_irq.h>
-
-#ifdef CONFIG_DEVFS_FS
-#define IFXMIPS_DEVNAME "ifxmips"
-#endif //ifdef CONFIG_DEVFS_FS
-
-#define MEI_LOCKINT(var) \
- local_save_flags(var);\
- local_irq_disable()
-#define MEI_UNLOCKINT(var) \
- local_irq_restore(var)
-
-#define MEI_MUTEX_INIT(id,flag) \
- sema_init(&id,flag)
-#define MEI_MUTEX_LOCK(id) \
- down_interruptible(&id)
-#define MEI_MUTEX_UNLOCK(id) \
- up(&id)
-
-#define MEI_MASK_AND_ACK_IRQ \
- ifxmips_mask_and_ack_irq
-
-#define MEI_DISABLE_IRQ \
- disable_irq
-#define MEI_ENABLE_IRQ \
- enable_irq
-
-#define MEI_WAIT(ms) \
- {\
- set_current_state(TASK_INTERRUPTIBLE);\
- schedule_timeout(ms);\
- }
-
-#define MEI_INIT_WAKELIST(name,queue) \
- init_waitqueue_head(&queue)
-
-#define MEI_WAIT_EVENT_TIMEOUT(ev,timeout)\
- interruptible_sleep_on_timeout(&ev,timeout)
-
-#define MEI_WAIT_EVENT(ev)\
- interruptible_sleep_on(&ev)
-#define MEI_WAKEUP_EVENT(ev)\
- wake_up_interruptible(&ev)
-
-typedef unsigned long MEI_intstat_t;
-typedef struct semaphore MEI_mutex_t;
-typedef struct file MEI_file_t;
-typedef struct inode MEI_inode_t;
-
-extern void mask_and_ack_ifxmips_irq (unsigned int irq_nr);
pci_probe_only = 0;
printk("PCI: Probing PCI hardware on host bus 0.\n");
ifxmips_pci_startup ();
- // IFXMIPS_PCI_REG32(PCI_CR_CLK_CTRL_REG) &= (~8);
ifxmips_pci_mapped_cfg = (u32)ioremap_nocache(0x17000000, 0x800 * 16);
printk("IFXMips PCI mapped to 0x%08lX\n", (unsigned long)ifxmips_pci_mapped_cfg);
ifxmips_pci_controller.io_map_base = (unsigned long)ioremap(IFXMIPS_PCI_IO_BASE, IFXMIPS_PCI_IO_SIZE - 1);
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * This driver was originally based on the INCA-IP driver, but due to
- * fundamental conceptual drawbacks there has been changed a lot.
- *
- * Based on INCA-IP driver Copyright(c) 2003 Gary Jennejohn <gj@denx.de>
- * Based on the VxWorks drivers Copyright(c) 2002, Infineon Technologies.
- *
- * Copyright(C) 2006 infineon
- * Copyright(C) 2007 John Crispin <blogic@openwrt.org>
- *
- */
-
-#define IFAP_EEPROM_DRV_VERSION "0.0.1"
-
-#include <linux/module.h>
-#include <linux/errno.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/timer.h>
-#include <linux/interrupt.h>
-#include <linux/major.h>
-#include <linux/string.h>
-#include <linux/fs.h>
-#include <linux/fcntl.h>
-#include <linux/ptrace.h>
-#include <linux/mm.h>
-#include <linux/ioport.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/spinlock.h>
-#include <linux/slab.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/uaccess.h>
-#include <linux/bitops.h>
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/version.h>
-
-#include <asm/system.h>
-#include <asm/ifxmips/ifxmips.h>
-#include <asm/ifxmips/ifxmips_irq.h>
-#include <asm/ifxmips/ifx_ssc_defines.h>
-#include <asm/ifxmips/ifx_ssc.h>
-
-/* allow the user to set the major device number */
-static int ifxmips_eeprom_maj;
-
-extern int ifx_ssc_init(void);
-extern int ifx_ssc_open(struct inode *inode, struct file *filp);
-extern int ifx_ssc_close(struct inode *inode, struct file *filp);
-extern void ifx_ssc_cleanup_module(void);
-extern int ifx_ssc_ioctl(struct inode *inode, struct file *filp,
- unsigned int cmd, unsigned long data);
-extern ssize_t ifx_ssc_kwrite(int port, const char *kbuf, size_t len);
-extern ssize_t ifx_ssc_kread(int port, char *kbuf, size_t len);
-
-extern int ifx_ssc_cs_low(unsigned int pin);
-extern int ifx_ssc_cs_high(unsigned int pin);
-extern int ifx_ssc_txrx(char *tx_buf, unsigned int tx_len, char *rx_buf, unsigned int rx_len);
-extern int ifx_ssc_tx(char *tx_buf, unsigned int tx_len);
-extern int ifx_ssc_rx(char *rx_buf, unsigned int rx_len);
-
-#define EEPROM_CS IFX_SSC_WHBGPOSTAT_OUT0_POS
-
-/* commands for EEPROM, x25160, x25140 */
-#define EEPROM_WREN ((unsigned char)0x06)
-#define EEPROM_WRDI ((unsigned char)0x04)
-#define EEPROM_RDSR ((unsigned char)0x05)
-#define EEPROM_WRSR ((unsigned char)0x01)
-#define EEPROM_READ ((unsigned char)0x03)
-#define EEPROM_WRITE ((unsigned char)0x02)
-#define EEPROM_PAGE_SIZE 4
-#define EEPROM_SIZE 512
-
-static int eeprom_rdsr(void)
-{
- int ret = 0;
- unsigned char cmd = EEPROM_RDSR;
- unsigned long flag;
- char status;
-
- local_irq_save(flag);
-
- if ((ret = ifx_ssc_cs_low(EEPROM_CS)) == 0)
- if ((ret = ifx_ssc_txrx(&cmd, 1, &status, 1)) >= 0)
- ret = status & 1;
-
- ifx_ssc_cs_high(EEPROM_CS);
- local_irq_restore(flag);
-
- return ret;
-}
-
-void eeprom_wip_over(void)
-{
- while (eeprom_rdsr())
- printk(KERN_INFO "waiting for eeprom\n");
-}
-
-static int eeprom_wren(void)
-{
- unsigned char cmd = EEPROM_WREN;
- int ret = 0;
- unsigned long flag;
-
- local_irq_save(flag);
- if ((ret = ifx_ssc_cs_low(EEPROM_CS)) == 0)
- if ((ret = ifx_ssc_tx(&cmd, 1)) >= 0)
- ret = 0;
-
- ifx_ssc_cs_high(EEPROM_CS);
- local_irq_restore(flag);
-
- if (!ret)
- eeprom_wip_over();
-
- return ret;
-}
-
-static int eeprom_wrsr(void)
-{
- int ret = 0;
- unsigned char cmd[2];
- unsigned long flag;
-
- cmd[0] = EEPROM_WRSR;
- cmd[1] = 0;
-
- if ((ret = eeprom_wren())) {
- printk(KERN_ERR "eeprom_wren fails\n");
- goto out1;
- }
-
- local_irq_save(flag);
-
- if ((ret = ifx_ssc_cs_low(EEPROM_CS)))
- goto out;
-
- if ((ret = ifx_ssc_tx(cmd, 2)) < 0) {
- ifx_ssc_cs_high(EEPROM_CS);
- goto out;
- }
-
- if ((ret = ifx_ssc_cs_low(EEPROM_CS)))
- goto out;
-
- local_irq_restore(flag);
- eeprom_wip_over();
-
- return ret;
-
-out:
- local_irq_restore(flag);
- eeprom_wip_over();
-
-out1:
- return ret;
-}
-
-static int eeprom_read(unsigned int addr, unsigned char *buf, unsigned int len)
-{
- int ret = 0;
- unsigned char write_buf[2];
- unsigned int eff = 0;
- unsigned long flag;
-
- while (1) {
- eeprom_wip_over();
- eff = EEPROM_PAGE_SIZE - (addr % EEPROM_PAGE_SIZE);
- eff = (eff < len) ? eff : len;
- local_irq_save(flag);
-
- if ((ret = ifx_ssc_cs_low(EEPROM_CS)) < 0)
- goto out;
-
- write_buf[0] = EEPROM_READ | ((unsigned char)((addr & 0x100) >> 5));
- write_buf[1] = (addr & 0xff);
-
- ret = ifx_ssc_txrx(write_buf, 2, buf, eff);
- if (ret != eff) {
- printk(KERN_ERR "ssc_txrx fails %d\n", ret);
- ifx_ssc_cs_high(EEPROM_CS);
- goto out;
- }
-
- buf += ret;
- len -= ret;
- addr += ret;
-
- ret = ifx_ssc_cs_high(EEPROM_CS);
- if (ret)
- goto out;
-
- local_irq_restore(flag);
-
- if (len <= 0)
- goto out2;
- }
-
-out:
- local_irq_restore(flag);
-out2:
- return ret;
-}
-
-static int eeprom_write(unsigned int addr, unsigned char *buf, unsigned int len)
-{
- int ret = 0;
- unsigned int eff = 0;
- unsigned char write_buf[2];
- int i;
- unsigned char rx_buf[EEPROM_PAGE_SIZE];
-
- while (1) {
- eeprom_wip_over();
-
- if ((ret = eeprom_wren())) {
- printk(KERN_ERR "eeprom_wren fails\n");
- goto out;
- }
-
- write_buf[0] = EEPROM_WRITE | ((unsigned char)((addr & 0x100) >> 5));
- write_buf[1] = (addr & 0xff);
-
- eff = EEPROM_PAGE_SIZE - (addr % EEPROM_PAGE_SIZE);
- eff = (eff < len) ? eff : len;
-
- printk(KERN_INFO "EEPROM Write:\n");
- for (i = 0; i < eff; i++) {
- printk("%2x ", buf[i]);
- if ((i % 16) == 15)
- printk("\n");
- }
- printk("\n");
-
- if ((ret = ifx_ssc_cs_low(EEPROM_CS)))
- goto out;
-
- if ((ret = ifx_ssc_tx(write_buf, 2)) < 0) {
- printk(KERN_ERR "ssc_tx fails %d\n", ret);
- ifx_ssc_cs_high(EEPROM_CS);
- goto out;
- }
-
- if ((ret = ifx_ssc_tx(buf, eff)) != eff) {
- printk(KERN_ERR "ssc_tx fails %d\n", ret);
- ifx_ssc_cs_high(EEPROM_CS);
- goto out;
- }
-
- buf += ret;
- len -= ret;
- addr += ret;
-
- if ((ret = ifx_ssc_cs_high(EEPROM_CS)))
- goto out;
-
- printk(KERN_INFO "<==");
- eeprom_read((addr - eff), rx_buf, eff);
- for (i = 0; i < eff; i++)
- printk("[%x]", rx_buf[i]);
- printk("\n");
-
- if (len <= 0)
- break;
- }
-
-out:
- return ret;
-}
-
-int ifxmips_eeprom_open(struct inode *inode, struct file *filp)
-{
- filp->f_pos = 0;
- return 0;
-}
-
-int ifxmips_eeprom_close(struct inode *inode, struct file *filp)
-{
- return 0;
-}
-
-int ifxmips_eeprom_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long data)
-{
- return 0;
-}
-
-ssize_t ifxmips_eeprom_read(char *buf, size_t len, unsigned int addr)
-{
- int ret = 0;
- unsigned int data;
-
- printk(KERN_INFO "addr:=%d\n", addr);
- printk(KERN_INFO "len:=%d\n", len);
-
- if ((addr + len) > EEPROM_SIZE) {
- printk(KERN_ERR "invalid len\n");
- addr = 0;
- len = EEPROM_SIZE / 2;
- }
-
- if ((ret = ifx_ssc_open((struct inode *)0, NULL))) {
- printk(KERN_ERR "ifxmips_ssc_open fails\n");
- goto out;
- }
-
- data = (unsigned int)IFX_SSC_MODE_RXTX;
-
- if ((ret = ifx_ssc_ioctl((struct inode *)0, NULL, IFX_SSC_RXTX_MODE_SET, (unsigned long) &data))) {
- printk(KERN_ERR "set RXTX mode fails\n");
- goto out;
- }
-
- if ((ret = eeprom_wrsr())) {
- printk(KERN_ERR "EEPROM reset fails\n");
- goto out;
- }
-
- if ((ret = eeprom_read(addr, buf, len))) {
- printk(KERN_ERR "eeprom read fails\n");
- goto out;
- }
-
-out:
- if (ifx_ssc_close((struct inode *)0, NULL))
- printk(KERN_ERR "ifxmips_ssc_close fails\n");
-
- return len;
-}
-EXPORT_SYMBOL(ifxmips_eeprom_read);
-
-static ssize_t ifxmips_eeprom_fops_read(struct file *filp, char *ubuf, size_t len, loff_t *off)
-{
- int ret = 0;
- unsigned char ssc_rx_buf[EEPROM_SIZE];
- unsigned long flag;
-
- if (*off >= EEPROM_SIZE)
- return 0;
-
- if (*off + len > EEPROM_SIZE)
- len = EEPROM_SIZE - *off;
-
- if (len == 0)
- return 0;
-
- local_irq_save(flag);
-
- if ((ret = ifxmips_eeprom_read(ssc_rx_buf, len, *off)) < 0) {
- printk(KERN_ERR "read fails, err=%x\n", ret);
- local_irq_restore(flag);
- return ret;
- }
-
- if (copy_to_user((void *)ubuf, ssc_rx_buf, ret) != 0) {
- local_irq_restore(flag);
- ret = -EFAULT;
- }
-
- local_irq_restore(flag);
- *off += len;
-
- return len;
-}
-
-ssize_t ifxmips_eeprom_write(char *buf, size_t len, unsigned int addr)
-{
- int ret = 0;
- unsigned int data;
-
- if ((ret = ifx_ssc_open((struct inode *)0, NULL))) {
- printk(KERN_ERR "ifxmips_ssc_open fails\n");
- goto out;
- }
-
- data = (unsigned int) IFX_SSC_MODE_RXTX;
-
- if ((ret = ifx_ssc_ioctl((struct inode *)0, NULL, IFX_SSC_RXTX_MODE_SET, (unsigned long) &data))) {
- printk(KERN_ERR "set RXTX mode fails\n");
- goto out;
- }
-
- if ((ret = eeprom_wrsr())) {
- printk(KERN_ERR "EEPROM reset fails\n");
- goto out;
- }
-
- if ((ret = eeprom_write(addr, buf, len))) {
- printk(KERN_ERR "eeprom write fails\n");
- goto out;
- }
-
-out:
- if (ifx_ssc_close((struct inode *)0, NULL))
- printk(KERN_ERR "ifxmips_ssc_close fails\n");
-
- return ret;
-}
-EXPORT_SYMBOL(ifxmips_eeprom_write);
-
-static ssize_t ifxmips_eeprom_fops_write(struct file *filp, const char *ubuf, size_t len, loff_t *off)
-{
- int ret = 0;
- unsigned char ssc_tx_buf[EEPROM_SIZE];
-
- if (*off >= EEPROM_SIZE)
- return 0;
-
- if (len + *off > EEPROM_SIZE)
- len = EEPROM_SIZE - *off;
-
- if ((ret = copy_from_user(ssc_tx_buf, ubuf, len)))
- return EFAULT;
-
- ret = ifxmips_eeprom_write(ssc_tx_buf, len, *off);
-
- if (ret > 0)
- *off = ret;
-
- return ret;
-}
-
-loff_t ifxmips_eeprom_llseek(struct file *filp, loff_t off, int whence)
-{
- loff_t newpos;
- switch (whence) {
- case SEEK_SET:
- newpos = off;
- break;
-
- case SEEK_CUR:
- newpos = filp->f_pos + off;
- break;
-
- default:
- return -EINVAL;
- }
-
- if (newpos < 0)
- return -EINVAL;
-
- filp->f_pos = newpos;
-
- return newpos;
-}
-
-static struct file_operations ifxmips_eeprom_fops = {
- .owner = THIS_MODULE,
- .llseek = ifxmips_eeprom_llseek,
- .read = ifxmips_eeprom_fops_read,
- .write = ifxmips_eeprom_fops_write,
- .ioctl = ifxmips_eeprom_ioctl,
- .open = ifxmips_eeprom_open,
- .release = ifxmips_eeprom_close,
-};
-
-int __init ifxmips_eeprom_init(void)
-{
- int ret = 0;
-
- ifxmips_eeprom_maj = register_chrdev(0, "eeprom", &ifxmips_eeprom_fops);
-
- if (ifxmips_eeprom_maj < 0) {
- printk(KERN_ERR "failed to register eeprom device\n");
- ret = -EINVAL;
-
- goto out;
- }
-
- printk(KERN_INFO "ifxmips_eeprom : /dev/eeprom mayor %d\n", ifxmips_eeprom_maj);
-
-out:
- return ret;
-}
-
-void __exit ifxmips_eeprom_cleanup_module(void)
-{
- /*if (unregister_chrdev(ifxmips_eeprom_maj, "eeprom")) {
- printk(KERN_ERR "Unable to unregister major %d for the EEPROM\n",
- maj);
- }*/
-}
-
-module_exit(ifxmips_eeprom_cleanup_module);
-module_init(ifxmips_eeprom_init);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Peng Liu");
-MODULE_DESCRIPTION("IFAP EEPROM driver");
-MODULE_SUPPORTED_DEVICE("ifxmips_eeprom");
-
+++ /dev/null
-/******************************************************************************
-**
-** FILE NAME : ifxmips_mei_core.c
-** PROJECT : Danube
-** MODULES : MEI
-**
-** DATE : 1 Jan 2006
-** AUTHOR : TC Chen
-** DESCRIPTION : MEI Driver
-** COPYRIGHT : Copyright (c) 2006
-** Infineon Technologies AG
-** Am Campeon 1-12, 85579 Neubiberg, Germany
-**
-** This program is free software; you can redistribute it and/or modify
-** it under the terms of the GNU General Public License as published by
-** the Free Software Foundation; either version 2 of the License, or
-** (at your option) any later version.
-**
-** HISTORY
-** $Version $Date $Author $Comment
- 1.00.01 TC Chen Fixed cell rate calculation issue
- Fixed pvovider_id of adsl mib swapping issue
- 1.00.02 TC Chen Added L3 Low Poewr Mode support.
- 1.00.03 TC Chen Fixed Clear Eoc transmit issue.
- 1.00.04 31/08/2006 TC Chen Add ADSL Link/Data Led
- Add Dual Latency Path
- Add AUTOBOOT_ENABLE_SET ioctl for autoboot
- mode enable/disable
- Fix fast path cell rate calculation
- 1.00.05 25/09/2006 TC Chen Fix ATM QoS fail on interface 0(fast path).
- 1.00.06 02/10/2006 TC Chen Change ifxmips_ppe_set_cell_rate to
- ifx_atm_set_cell_rate
- Add ATM Led callback function
- 1.00.07 13/11/2006 TC Chen Invert ADSL Link LED Signal
- 1.00.08 08/12/2006 TC Chen Fix loop diagnostic warning message issue
- 1.00.09 20/12/2006 TC Chen Workaround for USB OC interrupt which is trigegred once DSL reset
-******************************************************************************/
-
-/*
- * ===========================================================================
- * INCLUDE FILES
- * ===========================================================================
- */
-
-#include <asm/ifxmips/ifxmips_mei_linux.h>
-
-char IFXMIPS_MEI_VERSION[] = "1.00.09";
-
-#define IFXMIPS_MEI_CMV_EXTRA //WINHOST debug
-#define IFX_ADSL_L3_MODE_SUPPORT //L3 Low Power Mode Support
-#define IFX_ADSL_DUAL_LATENCY_SUPPORT
-#undef IFXMIPS_CLEAR_EOC //clear eoc support
-
-// for ARC memory access
-#define WHILE_DELAY 20000
-#if defined(IFXMIPS_PORT_RTEMS)
-#undef IFXMIPS_DMA_DEBUG_MUTEX
-#else
-#define IFXMIPS_DMA_DEBUG_MUTEX
-#endif
-
-#define IMAGE_SWAP
-#define BOOT_SWAP
-#define HEADER_SWAP
-
-//TODO
-#undef DFE_LOOPBACK // testing code //undefined by Henry , start to real link test.
- //165203:henryhsu
-
-#ifdef DFE_LOOPBACK
-//#define DFE_MEM_TEST
-//#define DFE_PING_TEST
-#define DFE_ATM_LOOPBACK
-#endif
-
-#undef DATA_LED_ON_MODE
-#define DATA_LED_SUPPORT // support adsl data led
-//#define DATA_LED_ADSL_FW_HANDLE // adsl data led handle by firmware
-#define CONFIG_IFXMIPS_MEI_LED // adsl led support
-
-// Block size per BAR
-#define SDRAM_SEGMENT_SIZE (64*1024)
-// Number of Bar registers
-#define MAX_BAR_REGISTERS (17)
-
-#define XDATA_REGISTER (15)
-
-#define IFXMIPS_MEI_DEVNAME "mei"
-
-#ifdef DFE_LOOPBACK
-#ifndef UINT32
-#define UINT32 unsigned long
-#endif
-#ifdef DFE_PING_TEST
-#include "dsp_xmem_arb_rand_em.h"
-#endif
-#ifdef DFE_MEM_TEST
-#include "aai_mem_test.h"
-#endif
-#ifdef DFE_ATM_LOOPBACK
-#include "aai_lpbk_dyn_rate.h"
-#endif
-#endif
-
-/************************************************************************
- * Function declaration
- ************************************************************************/
-static MEI_ERROR meiDMAWrite (u32 destaddr, u32 * databuff, u32 databuffsize);
-static MEI_ERROR meiDMARead (u32 srcaddr, u32 * databuff, u32 databuffsize);
-static void meiControlModeSwitch (int mode);
-static void meiPollForDbgDone (void);
-static MEI_ERROR _meiDebugLongWordRead (u32 DEC_mode, u32 address,
- u32 * data);
-static MEI_ERROR _meiDebugLongWordWrite (u32 DEC_mode, u32 address, u32 data);
-MEI_ERROR meiDebugWrite (u32 destaddr, u32 * databuff, u32 databuffsize);
-static MEI_ERROR meiDebugRead (u32 srcaddr, u32 * databuff, u32 databuffsize);
-static MEI_ERROR meiMailboxWrite (u16 * msgsrcbuffer, u16 msgsize);
-static MEI_ERROR meiDownloadBootCode (void);
-static MEI_ERROR meiHaltArc (void);
-static MEI_ERROR meiRunArc (void);
-static MEI_ERROR meiRunAdslModem (void);
-static int meiGetPage (u32 Page, u32 data, u32 MaxSize, u32 * Buffer,
- u32 * Dest);
-void makeCMV (u8 opcode, u8 group, u16 address, u16 index, int size,
- u16 * data, u16 * CMVMSG);
-MEI_ERROR meiCMV (u16 * request, int reply, u16 * response);
-static void meiMailboxInterruptsDisable (void);
-static void meiMailboxInterruptsEnable (void);
-static int update_bar_register (int nTotalBar);
-static int free_image_buffer (int type);
-static int alloc_processor_memory (unsigned long size,
- smmu_mem_info_t * adsl_mem_info);
-ssize_t mei_write (MEI_file_t * filp, char *buf, size_t size, loff_t * loff);
-int mei_ioctl (MEI_inode_t * ino, MEI_file_t * fil, unsigned int command,
- unsigned long lon);
-
-#ifdef CONFIG_PROC_FS
-static int proc_read (struct file *file, char *buf, size_t nbytes,
- loff_t * ppos);
-static ssize_t proc_write (struct file *file, const char *buffer,
- size_t count, loff_t * ppos);
-#endif
-
-#ifdef CONFIG_IFXMIPS_MEI_MIB
-int mei_mib_ioctl (MEI_inode_t * ino, MEI_file_t * fil, unsigned int command,
- unsigned long lon);
-int mei_mib_adsl_link_up (void);
-int mei_mib_adsl_link_down (void);
-int ifxmips_mei_mib_init (void);
-int ifxmips_mei_mib_cleanup (void);
-#endif
-#if defined(CONFIG_IFXMIPS_MEI_LED) && defined(DATA_LED_SUPPORT)
-static int ifxmips_mei_led_init (void);
-static int ifxmips_mei_led_cleanup (void);
-static int adsl_led_flash_task (void);
-#endif
-// for clearEoC
-#ifdef IFXMIPS_CLEAR_EOC
-extern void ifx_push_eoc (struct sk_buff *pkt);
-#endif
-
-/************************************************************************
- * variable declaration
- ************************************************************************/
-static smmu_mem_info_t adsl_mem_info[MAX_BAR_REGISTERS];
-static unsigned long image_size = 0;
-static struct timeval time_disconnect, time_showtime;
-static u16 unavailable_seconds = 0;
-#ifdef IFXMIPS_CLEAR_EOC
-static wait_queue_head_t wait_queue_hdlc_poll; ///clear eoc
-#endif
-
-static int showtime_lock_flag = 0;
-static int quiet_mode_flag = 0;
-
-int showtime = 0;
-static int major = IFXMIPS_MEI_MAJOR;
-MEI_mutex_t mei_sema;
-
-// Mei to ARC CMV count, reply count, ARC Indicator count
-static int indicator_count = 0;
-static int cmv_count = 0;
-static int reply_count = 0;
-static u16 Recent_indicator[MSG_LENGTH];
-static int reset_arc_flag = 0;
-
-// Used in interrupt handler as flags
-static int arcmsgav = 0;
-static int cmv_reply = 0;
-static int cmv_waiting = 0;
-static int modem_ready = 0;
-// to wait for arc cmv reply, sleep on wait_queue_arcmsgav;
-static wait_queue_head_t wait_queue_arcmsgav;
-
-// CMV mailbox messages
-// ARC to MEI message
-static u16 CMV_RxMsg[MSG_LENGTH] __attribute__ ((aligned (4)));
-// MEI to ARC message
-static u16 CMV_TxMsg[MSG_LENGTH] __attribute__ ((aligned (4)));
-
-static u32 *mei_arc_swap_buff = NULL; // holding swap pages
-static ARC_IMG_HDR *img_hdr;
-static int arc_halt_flag = 0;
-static int nBar = 0; // total bars to be used.
-
-static u32 loop_diagnostics_mode = 0;
-wait_queue_head_t wait_queue_loop_diagnostic;
-int loop_diagnostics_completed = 0;
-u32 adsl_mode, adsl_mode_extend; // adsl mode : adsl/ 2/ 2+
-static int autoboot_enable_flag = 0;
-
-#ifdef IFX_ADSL_DUAL_LATENCY_SUPPORT
-static u8 bDualLatency = 0;
-#endif
-
-#ifdef IFXMIPS_CLEAR_EOC
-static u16 ceoc_read_idx = 0;
-#endif
-
-#ifdef IFX_ADSL_L3_MODE_SUPPORT
-static wait_queue_head_t wait_queue_l3; // l3 power mode
-static int l3_shutdown = 0;
-int get_l3_power_status (void);
-#endif
-
-#if defined(CONFIG_IFXMIPS_MEI_LED) && defined(DATA_LED_SUPPORT)
-int led_status_on = 0, led_need_to_flash = 0;
-static int stop_led_module = 0; //wakeup and clean led module
-static wait_queue_head_t wait_queue_led_polling; // adsl led
-#endif
-
-static struct file_operations mei_operations = {
- write : mei_write,
- ioctl : mei_ioctl,
-};
-
-#ifdef CONFIG_PROC_FS
-static struct proc_dir_entry *meidir;
-static struct file_operations proc_operations = {
- read:proc_read,
- write:proc_write,
-};
-static reg_entry_t regs[PROC_ITEMS]; //total items to be monitored by /proc/mei
-#define NUM_OF_REG_ENTRY (sizeof(regs)/sizeof(reg_entry_t))
-#endif //#ifdef CONFIG_PROC_FS
-
-#ifdef DFE_LOOPBACK
-unsigned char got_int = 0;
-#endif
-
-///////////////// mei access Rd/Wr methods ///////////////
-/**
- * Write a value to register
- * This function writes a value to ifxmips register
- *
- * \param ul_address The address to write
- * \param ul_data The value to write
- * \ingroup Internal
- */
-static void
-meiLongwordWrite (u32* ul_address, u32 ul_data)
-{
- ifxmips_w32(ul_data, ul_address);
- wmb();
- return;
-} // end of "meiLongwordWrite(..."
-
-/**
- * Read the ifxmips register
- * This function read the value from ifxmips register
- *
- * \param ul_address The address to write
- * \param pul_data Pointer to the data
- * \ingroup Internal
- */
-static void
-meiLongwordRead (u32* ul_address, u32 * pul_data)
-{
- //*pul_data = *((volatile u32 *)ul_address);
- *pul_data = ifxmips_r32(ul_address);
- wmb();
- return;
-} // end of "meiLongwordRead(..."
-
-/**
- * Write several DWORD datas to ARC memory via ARC DMA interface
- * This function writes several DWORD datas to ARC memory via DMA interface.
- *
- * \param destaddr The address to write
- * \param databuff Pointer to the data buffer
- * \param databuffsize Number of DWORDs to write
- * \return MEI_SUCCESS or MEI_FAILURE
- * \ingroup Internal
- */
-static MEI_ERROR
-meiDMAWrite (u32 destaddr, u32 * databuff, u32 databuffsize)
-{
- u32 *p = databuff;
- u32 temp;
- MEI_intstat_t flags;
-
- if (destaddr & 3)
- return MEI_FAILURE;
-
-#ifdef IFXMIPS_DMA_DEBUG_MUTEX
- MEI_LOCKINT (flags);
-#endif
-
- //printk("destaddr=%X,size=%d\n",destaddr,databuffsize);
- // Set the write transfer address
- meiLongwordWrite (MEI_XFR_ADDR, destaddr);
-
- // Write the data pushed across DMA
- while (databuffsize--) {
- temp = *p;
- if (databuff == (u32 *) CMV_TxMsg)
- MEI_HALF_WORD_SWAP (temp);
- meiLongwordWrite (MEI_DATA_XFR, temp);
- p++;
- } // end of "while(..."
-
-#ifdef IFXMIPS_DMA_DEBUG_MUTEX
- MEI_UNLOCKINT (flags);
-#endif
-
- return MEI_SUCCESS;
-
-} // end of "meiDMAWrite(..."
-
-/**
- * Read several DWORD datas from ARC memory via ARC DMA interface
- * This function reads several DWORD datas from ARC memory via DMA interface.
- *
- * \param srcaddr The address to read
- * \param databuff Pointer to the data buffer
- * \param databuffsize Number of DWORDs to read
- * \return MEI_SUCCESS or MEI_FAILURE
- * \ingroup Internal
- */
-static MEI_ERROR
-meiDMARead (u32 srcaddr, u32 * databuff, u32 databuffsize)
-{
- u32 *p = databuff;
- u32 temp;
-#ifdef IFXMIPS_DMA_DEBUG_MUTEX
- MEI_intstat_t flags;
-#endif
- //printk("destaddr=%X,size=%X\n",srcaddr,databuffsize);
- if (srcaddr & 3)
- return MEI_FAILURE;
-
-#ifdef IFXMIPS_DMA_DEBUG_MUTEX
- MEI_LOCKINT (flags);
-#endif
-
- // Set the read transfer address
- meiLongwordWrite (MEI_XFR_ADDR, srcaddr);
-
- // Read the data popped across DMA
- while (databuffsize--) {
- meiLongwordRead (MEI_DATA_XFR, &temp);
- if (databuff == (u32 *) CMV_RxMsg) // swap half word
- MEI_HALF_WORD_SWAP (temp);
- *p = temp;
- p++;
- } // end of "while(..."
-
-#ifdef IFXMIPS_DMA_DEBUG_MUTEX
- MEI_UNLOCKINT (flags);
-#endif
-
- return MEI_SUCCESS;
-
-} // end of "meiDMARead(..."
-
-/**
- * Switch the ARC control mode
- * This function switchs the ARC control mode to JTAG mode or MEI mode
- *
- * \param mode The mode want to switch: JTAG_MASTER_MODE or MEI_MASTER_MODE.
- * \ingroup Internal
- */
-static void
-meiControlModeSwitch (int mode)
-{
- u32 temp = 0x0;
- meiLongwordRead ( MEI_DBG_MASTER, &temp);
- switch (mode) {
- case JTAG_MASTER_MODE:
- temp &= ~(HOST_MSTR);
- break;
- case MEI_MASTER_MODE:
- temp |= (HOST_MSTR);
- break;
- default:
- printk ("meiControlModeSwitch: unkonwn mode [%d]\n",
- mode);
- return;
- }
- meiLongwordWrite (MEI_DBG_MASTER, temp);
-}
-
-/**
- * Poll for transaction complete signal
- * This function polls and waits for transaction complete signal.
- *
- * \ingroup Internal
- */
-static void
-meiPollForDbgDone (void)
-{
- u32 query = 0;
- int i = 0;
- while (i < WHILE_DELAY) {
- meiLongwordRead (ARC_TO_MEI_INT, &query);
- query &= (ARC_TO_MEI_DBG_DONE);
- if (query)
- break;
- i++;
- if (i == WHILE_DELAY) {
- printk ("\n\n PollforDbg fail");
- }
- }
- meiLongwordWrite ( ARC_TO_MEI_INT, ARC_TO_MEI_DBG_DONE); // to clear this interrupt
-} // end of "meiPollForDbgDone(..."
-
-/**
- * ARC Debug Memory Access for a single DWORD reading.
- * This function used for direct, address-based access to ARC memory.
- *
- * \param DEC_mode ARC memory space to used
- * \param address Address to read
- * \param data Pointer to data
- * \return MEI_SUCCESS or MEI_FAILURE
- * \ingroup Internal
- */
-static MEI_ERROR
-_meiDebugLongWordRead (u32 DEC_mode, u32 address, u32 * data)
-{
- meiLongwordWrite ( MEI_DEBUG_DEC, DEC_mode);
- meiLongwordWrite ( MEI_DEBUG_RAD, address);
- meiPollForDbgDone ();
- meiLongwordRead (MEI_DEBUG_DATA, data);
- return MEI_SUCCESS;
-}
-
-/**
- * ARC Debug Memory Access for a single DWORD writing.
- * This function used for direct, address-based access to ARC memory.
- *
- * \param DEC_mode ARC memory space to used
- * \param address The address to write
- * \param data The data to write
- * \return MEI_SUCCESS or MEI_FAILURE
- * \ingroup Internal
- */
-static MEI_ERROR
-_meiDebugLongWordWrite (u32 DEC_mode, u32 address, u32 data)
-{
- meiLongwordWrite (MEI_DEBUG_DEC, DEC_mode);
- meiLongwordWrite (MEI_DEBUG_WAD, address);
- meiLongwordWrite (MEI_DEBUG_DATA, data);
- meiPollForDbgDone ();
- return MEI_SUCCESS;
-}
-
-/**
- * ARC Debug Memory Access for writing.
- * This function used for direct, address-based access to ARC memory.
- *
- * \param destaddr The address to ead
- * \param databuffer Pointer to data
- * \param databuffsize The number of DWORDs to read
- * \return MEI_SUCCESS or MEI_FAILURE
- * \ingroup Internal
- */
-
-MEI_ERROR
-meiDebugWrite (u32 destaddr, u32 * databuff, u32 databuffsize)
-{
- u32 i;
- u32 temp = 0x0;
- u32 address = 0x0;
- u32 *buffer = 0x0;
-#ifdef IFXMIPS_DMA_DEBUG_MUTEX
- MEI_intstat_t flags;
-#endif
-
-#ifdef IFXMIPS_DMA_DEBUG_MUTEX
- MEI_LOCKINT (flags);
-#endif
-
- // Open the debug port before DMP memory write
- meiControlModeSwitch (MEI_MASTER_MODE);
-
- meiLongwordWrite (MEI_DEBUG_DEC, MEI_DEBUG_DEC_DMP1_MASK);
-
- // For the requested length, write the address and write the data
- address = destaddr;
- buffer = databuff;
- for (i = 0; i < databuffsize; i++) {
- temp = *buffer;
- _meiDebugLongWordWrite (MEI_DEBUG_DEC_DMP1_MASK, address,
- temp);
- address += 4;
- buffer++;
- } // end of "for(..."
-
- // Close the debug port after DMP memory write
- meiControlModeSwitch (JTAG_MASTER_MODE);
-
-#ifdef IFXMIPS_DMA_DEBUG_MUTEX
- MEI_UNLOCKINT (flags);
-#endif
-
- // Return
- return MEI_SUCCESS;
-
-} // end of "meiDebugWrite(..."
-
-/**
- * ARC Debug Memory Access for reading.
- * This function used for direct, address-based access to ARC memory.
- *
- * \param srcaddr The address to read
- * \param databuffer Pointer to data
- * \param databuffsize The number of DWORDs to read
- * \return MEI_SUCCESS or MEI_FAILURE
- * \ingroup Internal
- */
-static MEI_ERROR
-meiDebugRead (u32 srcaddr, u32 * databuff, u32 databuffsize)
-{
- u32 i;
- u32 temp = 0x0;
- u32 address = 0x0;
- u32 *buffer = 0x0;
-#ifdef IFXMIPS_DMA_DEBUG_MUTEX
- MEI_intstat_t flags;
-#endif
-
-#ifdef IFXMIPS_DMA_DEBUG_MUTEX
- MEI_LOCKINT (flags);
-#endif
-
- // Open the debug port before DMP memory read
- meiControlModeSwitch (MEI_MASTER_MODE);
-
- meiLongwordWrite (MEI_DEBUG_DEC, MEI_DEBUG_DEC_DMP1_MASK);
-
- // For the requested length, write the address and read the data
- address = srcaddr;
- buffer = databuff;
- for (i = 0; i < databuffsize; i++) {
- _meiDebugLongWordRead (MEI_DEBUG_DEC_DMP1_MASK, address,
- &temp);
- *buffer = temp;
- address += 4;
- buffer++;
- } // end of "for(..."
-
- // Close the debug port after DMP memory read
- meiControlModeSwitch (JTAG_MASTER_MODE);
-
-#ifdef IFXMIPS_DMA_DEBUG_MUTEX
- MEI_UNLOCKINT (flags);
-#endif
-
- // Return
- return MEI_SUCCESS;
-
-} // end of "meiDebugRead(..."
-
-/**
- * Send a message to ARC MailBox.
- * This function sends a message to ARC Mailbox via ARC DMA interface.
- *
- * \param msgsrcbuffer Pointer to message.
- * \param msgsize The number of words to write.
- * \return MEI_SUCCESS or MEI_FAILURE
- * \ingroup Internal
- */
-static MEI_ERROR
-meiMailboxWrite (u16 * msgsrcbuffer, u16 msgsize)
-{
- int i;
- u32 arc_mailbox_status = 0x0;
- u32 temp = 0;
- MEI_ERROR meiMailboxError = MEI_SUCCESS;
-
- // Write to mailbox
- meiMailboxError =
- meiDMAWrite (MEI_TO_ARC_MAILBOX, (u32 *) msgsrcbuffer,
- msgsize / 2);
- meiMailboxError =
- meiDMAWrite (MEI_TO_ARC_MAILBOXR, (u32 *) (&temp), 1);
-
- // Notify arc that mailbox write completed
- cmv_waiting = 1;
- meiLongwordWrite (MEI_TO_ARC_INT, MEI_TO_ARC_MSGAV);
-
- i = 0;
- while (i < WHILE_DELAY) { // wait for ARC to clear the bit
- meiLongwordRead ( MEI_TO_ARC_INT, &arc_mailbox_status);
- if ((arc_mailbox_status & MEI_TO_ARC_MSGAV) !=
- MEI_TO_ARC_MSGAV)
- break;
- i++;
- if (i == WHILE_DELAY) {
- printk
- ("\n\n MEI_TO_ARC_MSGAV not cleared by ARC");
- meiMailboxError = MEI_FAILURE;
- }
- }
-
- // Return
- return meiMailboxError;
-
-} // end of "meiMailboxWrite(..."
-
-/**
- * Read a message from ARC MailBox.
- * This function reads a message from ARC Mailbox via ARC DMA interface.
- *
- * \param msgsrcbuffer Pointer to message.
- * \param msgsize The number of words to read
- * \return MEI_SUCCESS or MEI_FAILURE
- * \ingroup Internal
- */
-static MEI_ERROR
-meiMailboxRead (u16 * msgdestbuffer, u16 msgsize)
-{
- MEI_ERROR meiMailboxError = MEI_SUCCESS;
- // Read from mailbox
- meiMailboxError =
- meiDMARead (ARC_TO_MEI_MAILBOX, (u32 *) msgdestbuffer,
- msgsize / 2);
-
- // Notify arc that mailbox read completed
- meiLongwordWrite (ARC_TO_MEI_INT, ARC_TO_MEI_MSGAV);
-
- // Return
- return meiMailboxError;
-
-} // end of "meiMailboxRead(..."
-
-/**
- * Download boot pages to ARC.
- * This function downloads boot pages to ARC.
- *
- * \return MEI_SUCCESS or MEI_FAILURE
- * \ingroup Internal
- */
-static MEI_ERROR
-meiDownloadBootPages (void)
-{
- int boot_loop;
- int page_size;
- u32 dest_addr;
-
- /*
- ** DMA the boot code page(s)
- */
-#ifndef HEADER_SWAP
- for (boot_loop = 1; boot_loop < le32_to_cpu (img_hdr->count);
- boot_loop++)
-#else
- for (boot_loop = 1; boot_loop < (img_hdr->count); boot_loop++)
-#endif
- {
-#ifndef HEADER_SWAP
- if (le32_to_cpu (img_hdr->page[boot_loop].p_size) & BOOT_FLAG)
-#else
- if ((img_hdr->page[boot_loop].p_size) & BOOT_FLAG)
-#endif
- {
- page_size =
- meiGetPage (boot_loop, GET_PROG, MAXSWAPSIZE,
- mei_arc_swap_buff, &dest_addr);
- if (page_size > 0) {
- meiDMAWrite (dest_addr, mei_arc_swap_buff,
- page_size);
- }
- }
-#ifndef HEADER_SWAP
- if (le32_to_cpu (img_hdr->page[boot_loop].d_size) & BOOT_FLAG)
-#else
- if ((img_hdr->page[boot_loop].d_size) & BOOT_FLAG)
-#endif
- {
- page_size =
- meiGetPage (boot_loop, GET_DATA, MAXSWAPSIZE,
- mei_arc_swap_buff, &dest_addr);
- if (page_size > 0) {
- meiDMAWrite (dest_addr, mei_arc_swap_buff,
- page_size);
- }
- }
- }
- return MEI_SUCCESS;
-}
-
-/**
- * Initial efuse rar.
- **/
-static void
-mei_fuse_rar_init (void)
-{
- u32 data = 0;
- meiDMAWrite (IRAM0_BASE, &data, 1);
- meiDMAWrite (IRAM0_BASE + 4, &data, 1);
- meiDMAWrite (IRAM1_BASE, &data, 1);
- meiDMAWrite (IRAM1_BASE + 4, &data, 1);
- meiDMAWrite (BRAM_BASE, &data, 1);
- meiDMAWrite (BRAM_BASE + 4, &data, 1);
- meiDMAWrite (ADSL_DILV_BASE, &data, 1);
- meiDMAWrite (ADSL_DILV_BASE + 4, &data, 1);
-}
-
-/**
- * efuse rar program
- **/
-static void
-mei_fuse_prg (void)
-{
- u32 reg_data, fuse_value;
- int i = 0;
- meiLongwordRead ( IFXMIPS_RCU_RST, ®_data);
- while ((reg_data & 0x10000000) == 0) {
- meiLongwordRead ( IFXMIPS_RCU_RST, ®_data);
- //add a watchdog
- i++;
- /* 0x4000 translate to about 16 ms@111M, so should be enough */
- if (i == 0x4000)
- return;
- }
- // STEP a: Prepare memory for external accesses
- // Write fuse_en bit24
- meiLongwordRead (IFXMIPS_RCU_RST, ®_data);
- meiLongwordWrite (IFXMIPS_RCU_RST, reg_data | (1 << 24));
-
- mei_fuse_rar_init ();
- for (i = 0; i < 4; i++) {
- meiLongwordRead((u32*)(IFXMIPS_FUSE_BASE_ADDR + (i * 4)), &fuse_value);
- switch (fuse_value & 0xF0000) {
- case 0x80000:
- reg_data =
- ((fuse_value & RX_DILV_ADDR_BIT_MASK) |
- (RX_DILV_ADDR_BIT_MASK + 0x1));
- meiDMAWrite (ADSL_DILV_BASE, ®_data, 1);
- break;
- case 0x90000:
- reg_data =
- ((fuse_value & RX_DILV_ADDR_BIT_MASK) |
- (RX_DILV_ADDR_BIT_MASK + 0x1));
- meiDMAWrite (ADSL_DILV_BASE + 4, ®_data, 1);
- break;
- case 0xA0000:
- reg_data =
- ((fuse_value & IRAM0_ADDR_BIT_MASK) |
- (IRAM0_ADDR_BIT_MASK + 0x1));
- meiDMAWrite (IRAM0_BASE, ®_data, 1);
- break;
- case 0xB0000:
- reg_data =
- ((fuse_value & IRAM0_ADDR_BIT_MASK) |
- (IRAM0_ADDR_BIT_MASK + 0x1));
- meiDMAWrite (IRAM0_BASE + 4, ®_data, 1);
- break;
- case 0xC0000:
- reg_data =
- ((fuse_value & IRAM1_ADDR_BIT_MASK) |
- (IRAM1_ADDR_BIT_MASK + 0x1));
- meiDMAWrite (IRAM1_BASE, ®_data, 1);
- break;
- case 0xD0000:
- reg_data =
- ((fuse_value & IRAM1_ADDR_BIT_MASK) |
- (IRAM1_ADDR_BIT_MASK + 0x1));
- meiDMAWrite (IRAM1_BASE + 4, ®_data, 1);
- break;
- case 0xE0000:
- reg_data =
- ((fuse_value & BRAM_ADDR_BIT_MASK) |
- (BRAM_ADDR_BIT_MASK + 0x1));
- meiDMAWrite (BRAM_BASE, ®_data, 1);
- break;
- case 0xF0000:
- reg_data =
- ((fuse_value & BRAM_ADDR_BIT_MASK) |
- (BRAM_ADDR_BIT_MASK + 0x1));
- meiDMAWrite (BRAM_BASE + 4, ®_data, 1);
- break;
- default: // PPE efuse
- break;
- }
- }
- meiLongwordRead (IFXMIPS_RCU_RST, ®_data);
- meiLongwordWrite (IFXMIPS_RCU_RST, reg_data & 0xF7FFFFFF);
-}
-
-/**
- * Download boot code to ARC.
- * This function downloads boot code to ARC.
- *
- * \return MEI_SUCCESS or MEI_FAILURE
- * \ingroup Internal
- */
-static MEI_ERROR
-meiDownloadBootCode (void)
-{
- u32 arc_debug_data = ACL_CLK_MODE_ENABLE; //0x10
-
- meiMailboxInterruptsDisable ();
-
- // Switch arc control from JTAG mode to MEI mode
- meiControlModeSwitch (MEI_MASTER_MODE);
- //enable ac_clk signal
- _meiDebugLongWordRead (MEI_DEBUG_DEC_DMP1_MASK, CRI_CCR0,
- &arc_debug_data);
- arc_debug_data |= ACL_CLK_MODE_ENABLE;
- _meiDebugLongWordWrite (MEI_DEBUG_DEC_DMP1_MASK, CRI_CCR0,
- arc_debug_data);
- //Switch arc control from MEI mode to JTAG mode
- meiControlModeSwitch (JTAG_MASTER_MODE);
-
- mei_fuse_prg (); //program fuse rar
-
- meiDownloadBootPages ();
-
- return MEI_SUCCESS;
-
-} // end of "meiDownloadBootCode(..."
-
-//#endif
-
-/**
- * Halt the ARC.
- * This function halts the ARC.
- *
- * \return MEI_SUCCESS or MEI_FAILURE
- * \ingroup Internal
- */
-static MEI_ERROR
-meiHaltArc (void)
-{
- u32 arc_debug_data = 0x0;
-
- // Switch arc control from JTAG mode to MEI mode
- meiControlModeSwitch (MEI_MASTER_MODE);
- _meiDebugLongWordRead (MEI_DEBUG_DEC_AUX_MASK, ARC_DEBUG,
- &arc_debug_data);
- arc_debug_data |= (BIT1);
- _meiDebugLongWordWrite (MEI_DEBUG_DEC_AUX_MASK, ARC_DEBUG,
- arc_debug_data);
- // Switch arc control from MEI mode to JTAG mode
- meiControlModeSwitch (JTAG_MASTER_MODE);
- arc_halt_flag = 1;
-
- MEI_WAIT (10);
- // Return
- return MEI_SUCCESS;
-
-} // end of "meiHalt(..."
-
-/**
- * Run the ARC.
- * This function runs the ARC.
- *
- * \return MEI_SUCCESS or MEI_FAILURE
- * \ingroup Internal
- */
-static MEI_ERROR
-meiRunArc (void)
-{
- u32 arc_debug_data = 0x0;
-
- // Switch arc control from JTAG mode to MEI mode- write '1' to bit0
- meiControlModeSwitch (MEI_MASTER_MODE);
- _meiDebugLongWordRead (MEI_DEBUG_DEC_AUX_MASK, AUX_STATUS,
- &arc_debug_data);
-
- // Write debug data reg with content ANDd with 0xFDFFFFFF (halt bit cleared)
- arc_debug_data &= ~(BIT25);
- _meiDebugLongWordWrite (MEI_DEBUG_DEC_AUX_MASK, AUX_STATUS,
- arc_debug_data);
-
- // Switch arc control from MEI mode to JTAG mode- write '0' to bit0
- meiControlModeSwitch (JTAG_MASTER_MODE);
- // Enable mask for arc codeswap interrupts
- meiMailboxInterruptsEnable ();
- arc_halt_flag = 0;
-
- // Return
- return MEI_SUCCESS;
-
-} // end of "meiActivate(..."
-
-/**
- * Reset the ARC.
- * This function resets the ARC.
- *
- * \return MEI_SUCCESS or MEI_FAILURE
- * \ingroup Internal
- */
-static MEI_ERROR
-meiResetARC (void)
-{
-
- u32 arc_debug_data = 0;
- showtime = 0;
-
- meiHaltArc ();
-
- meiLongwordRead (IFXMIPS_RCU_RST, &arc_debug_data);
- meiLongwordWrite (IFXMIPS_RCU_RST,
- arc_debug_data | IFXMIPS_RCU_RST_REQ_DFE |
- IFXMIPS_RCU_RST_REQ_AFE);
- meiLongwordWrite (IFXMIPS_RCU_RST, arc_debug_data);
- // reset ARC
- meiLongwordWrite(MEI_RST_CONTROL, MEI_SOFT_RESET);
- meiLongwordWrite(MEI_RST_CONTROL, 0);
-
- meiMailboxInterruptsDisable ();
- MEI_MUTEX_INIT (mei_sema, 1);
- reset_arc_flag = 1;
- modem_ready = 0;
- return MEI_SUCCESS;
-}
-
-/**
- * Reset the ARC, download boot codes, and run the ARC.
- * This function resets the ARC, downloads boot codes to ARC, and runs the ARC.
- *
- * \return MEI_SUCCESS or MEI_FAILURE
- * \ingroup Internal
- */
-static MEI_ERROR
-meiRunAdslModem (void)
-{
- int nSize = 0, idx = 0;
-
- img_hdr = (ARC_IMG_HDR *) adsl_mem_info[0].address;
-#if defined(HEADER_SWAP)
- if ((img_hdr->count) * sizeof (ARC_SWP_PAGE_HDR) > SDRAM_SEGMENT_SIZE)
-#else //define(HEADER_SWAP)
- if (le32_to_cpu (img_hdr->count) * sizeof (ARC_SWP_PAGE_HDR) >
- SDRAM_SEGMENT_SIZE)
-#endif //define(HEADER_SWAP)
- {
- printk
- ("segment_size is smaller than firmware header size\n");
- return -1;
- }
- // check image size
- for (idx = 0; idx < MAX_BAR_REGISTERS; idx++) {
- nSize += adsl_mem_info[idx].nCopy;
- }
- if (nSize != image_size) {
- printk
- ("Firmware download is not completed. \nPlease download firmware again!\n");
- return -1;
- }
- // TODO: check crc
- ///
- if (reset_arc_flag == 0) {
- u32 arc_debug_data;
-
- meiResetARC ();
- meiControlModeSwitch (MEI_MASTER_MODE);
- //enable ac_clk signal
- _meiDebugLongWordRead (MEI_DEBUG_DEC_DMP1_MASK, CRI_CCR0,
- &arc_debug_data);
- arc_debug_data |= ACL_CLK_MODE_ENABLE;
- _meiDebugLongWordWrite (MEI_DEBUG_DEC_DMP1_MASK, CRI_CCR0,
- arc_debug_data);
- meiControlModeSwitch (JTAG_MASTER_MODE);
- meiHaltArc ();
- update_bar_register (nBar);
- }
- reset_arc_flag = 0;
- if (arc_halt_flag == 0) {
- meiHaltArc ();
- }
- printk ("Starting to meiDownloadBootCode\n");
-
- meiDownloadBootCode();
-
- // 1.00.09 20/12/2006 TC Chen
- // disable USB OC interrupt, reset DSL chip will triger OC interrupt
- disable_irq(IFXMIPS_USB_OC_INT);
-
- meiRunArc ();
-
- MEI_WAIT (100); //wait 100ms
-
- //1.00.09 20/12/2006 TC Chen
- // restore USB OC interrupt
- MEI_MASK_AND_ACK_IRQ(IFXMIPS_USB_OC_INT);
- enable_irq(IFXMIPS_USB_OC_INT);
-
- if (modem_ready != 1) {
- printk ("Running ADSL modem firmware fail!\n");
- return MEI_FAILURE;
- }
-
-
- return MEI_SUCCESS;
-}
-
-/**
- * Get the page's data pointer
- * This function caculats the data address from the firmware header.
- *
- * \param Page The page number.
- * \param data Data page or program page.
- * \param MaxSize The maximum size to read.
- * \param Buffer Pointer to data.
- * \param Dest Pointer to the destination address.
- * \return The number of bytes to read.
- * \ingroup Internal
- */
-static int
-meiGetPage (u32 Page, u32 data, u32 MaxSize, u32 * Buffer, u32 * Dest)
-{
- u32 size;
- u32 i;
- u32 *p;
- u32 idx, offset, nBar = 0;
-
- if (Page > img_hdr->count)
- return -2;
- /*
- ** Get program or data size, depending on "data" flag
- */
-#ifndef HEADER_SWAP
- size = (data ==
- GET_DATA) ? le32_to_cpu (img_hdr->page[Page].
- d_size) : le32_to_cpu (img_hdr->
- page[Page].
- p_size);
-#else
- size = (data ==
- GET_DATA) ? (img_hdr->page[Page].d_size) : (img_hdr->
- page[Page].
- p_size);
-#endif
- size &= BOOT_FLAG_MASK; // Clear boot bit!
- if (size > MaxSize)
- return -1;
-
- if (size == 0)
- return 0;
- /*
- ** Get program or data offset, depending on "data" flag
- */
-#ifndef HEADER_SWAP
- i = data ? le32_to_cpu (img_hdr->page[Page].
- d_offset) : le32_to_cpu (img_hdr->page[Page].
- p_offset);
-#else
- i = data ? (img_hdr->page[Page].d_offset) : (img_hdr->page[Page].
- p_offset);
-#endif
-
- /*
- ** Copy data/program to buffer
- */
-
- idx = i / SDRAM_SEGMENT_SIZE;
- offset = i % SDRAM_SEGMENT_SIZE;
- p = (u32 *) ((u8 *) adsl_mem_info[idx].address + offset);
-
- for (i = 0; i < size; i++) {
- if (offset + i * 4 - (nBar * SDRAM_SEGMENT_SIZE) >=
- SDRAM_SEGMENT_SIZE) {
- idx++;
- nBar++;
- p = (u32 *) ((u8 *)
- KSEG1ADDR ((u32) adsl_mem_info[idx].
- address));
- }
- Buffer[i] = *p++;
-#ifdef BOOT_SWAP
-#ifndef IMAGE_SWAP
- Buffer[i] = le32_to_cpu (Buffer[i]);
-#endif
-#endif
- }
-
- /*
- ** Pass back data/program destination address
- */
-#ifndef HEADER_SWAP
- *Dest = data ? le32_to_cpu (img_hdr->page[Page].
- d_dest) : le32_to_cpu (img_hdr->
- page[Page].p_dest);
-#else
- *Dest = data ? (img_hdr->page[Page].d_dest) : (img_hdr->page[Page].
- p_dest);
-#endif
-
- return size;
-}
-
-////////////////makeCMV(Opcode, Group, Address, Index, Size, Data), CMV in u16 TxMessage[MSG_LENGTH]///////////////////////////
-
-/**
- * Compose a message.
- * This function compose a message from opcode, group, address, index, size, and data
- *
- * \param opcode The message opcode
- * \param group The message group number
- * \param address The message address.
- * \param index The message index.
- * \param size The number of words to read/write.
- * \param data The pointer to data.
- * \param CMVMSG The pointer to message buffer.
- * \ingroup Internal
- */
-void
-makeCMV (u8 opcode, u8 group, u16 address, u16 index, int size, u16 * data,
- u16 * CMVMSG)
-{
- memset (CMVMSG, 0, MSG_LENGTH * 2);
- CMVMSG[0] = (opcode << 4) + (size & 0xf);
- CMVMSG[1] = (((index == 0) ? 0 : 1) << 7) + (group & 0x7f);
- CMVMSG[2] = address;
- CMVMSG[3] = index;
- if (opcode == H2D_CMV_WRITE)
- memcpy (CMVMSG + 4, data, size * 2);
- return;
-}
-
-/**
- * Send a message to ARC and read the response
- * This function sends a message to arc, waits the response, and reads the responses.
- *
- * \param request Pointer to the request
- * \param reply Wait reply or not.
- * \param response Pointer to the response
- * \return MEI_SUCCESS or MEI_FAILURE
- * \ingroup Internal
- */
-MEI_ERROR
-meiCMV (u16 * request, int reply, u16 * response) // write cmv to arc, if reply needed, wait for reply
-{
- MEI_ERROR meierror;
-#if defined(IFXMIPS_PORT_RTEMS)
- int delay_counter = 0;
-#endif
-
- cmv_reply = reply;
- memcpy (CMV_TxMsg, request, MSG_LENGTH * 2);
- arcmsgav = 0;
-
- meierror = meiMailboxWrite (CMV_TxMsg, MSG_LENGTH);
-
- if (meierror != MEI_SUCCESS) {
- cmv_waiting = 0;
- arcmsgav = 0;
- printk ("\n\n MailboxWrite Fail.");
- return meierror;
- }
- else {
- cmv_count++;
- }
-
- if (cmv_reply == NO_REPLY)
- return MEI_SUCCESS;
-
-#if !defined(IFXMIPS_PORT_RTEMS)
- if (arcmsgav == 0)
- MEI_WAIT_EVENT_TIMEOUT (wait_queue_arcmsgav, CMV_TIMEOUT);
-#else
- while (arcmsgav == 0 && delay_counter < CMV_TIMEOUT / 5) {
- MEI_WAIT (5);
- delay_counter++;
- }
-#endif
-
- cmv_waiting = 0;
- if (arcmsgav == 0) { //CMV_timeout
- arcmsgav = 0;
- printk ("\nmeiCMV: MEI_MAILBOX_TIMEOUT\n");
- return MEI_MAILBOX_TIMEOUT;
- }
- else {
- arcmsgav = 0;
- reply_count++;
- memcpy (response, CMV_RxMsg, MSG_LENGTH * 2);
- return MEI_SUCCESS;
- }
- return MEI_SUCCESS;
-}
-
-///////////////////// Interrupt handler /////////////////////////
-/**
- * Disable ARC to MEI interrupt
- *
- * \ingroup Internal
- */
-static void
-meiMailboxInterruptsDisable (void)
-{
- meiLongwordWrite (ARC_TO_MEI_INT_MASK, 0x0);
-} // end of "meiMailboxInterruptsDisable(..."
-
-/**
- * Eable ARC to MEI interrupt
- *
- * \ingroup Internal
- */
-static void
-meiMailboxInterruptsEnable (void)
-{
- meiLongwordWrite (ARC_TO_MEI_INT_MASK, MSGAV_EN);
-} // end of "meiMailboxInterruptsEnable(..."
-
-/**
- * MEI interrupt handler
- *
- * \param int1
- * \param void0
- * \param regs Pointer to the structure of ifxmips mips registers
- * \ingroup Internal
- */
-irqreturn_t
-mei_interrupt_arcmsgav (int int1, void *void0)
-{
- u32 scratch;
-
-#if defined(DFE_LOOPBACK) && defined(DFE_PING_TEST)
- dfe_loopback_irq_handler ();
- goto out;
-#endif //DFE_LOOPBACK
-
- meiDebugRead (ARC_MEI_MAILBOXR, &scratch, 1);
- if (scratch & OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK) {
- printk("\n\n Receive Code Swap Request interrupt!!!");
- goto out;
- }
- else if (scratch & OMB_CLEAREOC_INTERRUPT_CODE) // clear eoc message interrupt
- {
- meiLongwordWrite (ARC_TO_MEI_INT, ARC_TO_MEI_MSGAV);
-#if defined (IFXMIPS_CLEAR_EOC)
- MEI_WAKEUP_EVENT (wait_queue_hdlc_poll);
-#endif
- MEI_MASK_AND_ACK_IRQ (IFXMIPS_MEI_INT);
- goto out;
- }
- else { // normal message
- meiMailboxRead (CMV_RxMsg, MSG_LENGTH);
-#if 0
- {
- int msg_idx = 0;
- printk ("got interrupt\n");
- for (msg_idx = 0; msg_idx < MSG_LENGTH; msg_idx++) {
- printk ("%04X ", CMV_RxMsg[msg_idx]);
- if (msg_idx % 8 == 7)
- printk ("\n");
- }
- printk ("\n");
- }
-#endif
- if (cmv_waiting == 1) {
- arcmsgav = 1;
- cmv_waiting = 0;
-#if !defined(IFXMIPS_PORT_RTEMS)
- MEI_WAKEUP_EVENT (wait_queue_arcmsgav);
-#endif
- }
- else {
- indicator_count++;
- memcpy ((char *) Recent_indicator, (char *) CMV_RxMsg,
- MSG_LENGTH * 2);
- if (((CMV_RxMsg[0] & 0xff0) >> 4) == D2H_AUTONOMOUS_MODEM_READY_MSG) // arc ready
- { //check ARC ready message
- printk ("Got MODEM_READY_MSG\n");
- modem_ready = 1;
- MEI_MUTEX_UNLOCK (mei_sema); // allow cmv access
- }
- }
- }
-
- MEI_MASK_AND_ACK_IRQ (IFXMIPS_MEI_INT);
-out:
- return IRQ_HANDLED;;
-}
-
-////////////////////////hdlc ////////////////
-
-/**
- * Get the hdlc status
- *
- * \return HDLC status
- * \ingroup Internal
- */
-static unsigned int
-ifx_me_hdlc_status (void)
-{
- u16 CMVMSG[MSG_LENGTH];
- int ret;
-
- if (showtime != 1)
- return -ENETRESET;
-
- makeCMV (H2D_CMV_READ, STAT, 14, 0, 1, NULL, CMVMSG); //Get HDLC status
- ret = mei_ioctl ((struct inode *) 0, NULL, IFXMIPS_MEI_CMV_WINHOST,
- (unsigned long) CMVMSG);
- if (ret != 0) {
- return -EIO;
- }
- return CMVMSG[4] & 0x0F;
-}
-
-/**
- * Check if the me is reslved.
- *
- * \param status the me status
- * \return ME_HDLC_UNRESOLVED or ME_HDLC_RESOLVED
- * \ingroup Internal
- */
-int
-ifx_me_is_resloved (int status)
-{
- u16 CMVMSG[MSG_LENGTH];
- int ret;
- if (adsl_mode <= 8 && adsl_mode_extend == 0) // adsl mode
- {
- makeCMV (H2D_CMV_READ, CNTL, 2, 0, 1, NULL, CMVMSG); //Get ME-HDLC Control
- ret = mei_ioctl ((struct inode *) 0, NULL,
- IFXMIPS_MEI_CMV_WINHOST,
- (unsigned long) CMVMSG);
- if (ret != 0) {
- return ME_HDLC_UNRESOLVED;
- }
- if (CMVMSG[4] & (1 << 0)) {
- return ME_HDLC_UNRESOLVED;
- }
- }
- else {
- if (status == ME_HDLC_MSG_QUEUED
- || status == ME_HDLC_MSG_SENT)
- return ME_HDLC_UNRESOLVED;
- if (status == ME_HDLC_IDLE) {
- makeCMV (H2D_CMV_READ, CNTL, 2, 0, 1, NULL, CMVMSG); //Get ME-HDLC Control
- ret = mei_ioctl ((struct inode *) 0, NULL,
- IFXMIPS_MEI_CMV_WINHOST,
- (unsigned long) CMVMSG);
- if (ret != 0) {
- return IFX_POP_EOC_FAIL;
- }
- if (CMVMSG[4] & (1 << 0)) {
- return ME_HDLC_UNRESOLVED;
- }
- }
- }
- return ME_HDLC_RESOLVED;
-}
-
-int
-_ifx_me_hdlc_send (unsigned char *hdlc_pkt, int pkt_len, int max_length)
-{
- int ret;
- u16 CMVMSG[MSG_LENGTH];
- u16 data = 0;
- u16 len = 0;
- int rx_length = 0;
- int write_size = 0;
-
- if (pkt_len > max_length) {
- makeCMV (H2D_CMV_READ, INFO, 85, 2, 1, NULL, CMVMSG); //Get ME-HDLC Control
- ret = mei_ioctl ((struct inode *) 0, NULL,
- IFXMIPS_MEI_CMV_WINHOST,
- (unsigned long) CMVMSG);
- if (ret != 0) {
- return -EIO;
- }
- rx_length = CMVMSG[4];
- if (rx_length + max_length < pkt_len) {
- printk ("Exceed maximum eoc rx(%d)+tx(%d) message length\n", rx_length, max_length);
- return -EMSGSIZE;
- }
- data = 1;
- makeCMV (H2D_CMV_WRITE, INFO, 85, 6, 1, &data, CMVMSG); //disable RX Eoc
- ret = mei_ioctl ((struct inode *) 0, NULL,
- IFXMIPS_MEI_CMV_WINHOST,
- (unsigned long) CMVMSG);
- if (ret != 0) {
- return -EIO;
- }
- }
- while (len < pkt_len) {
- write_size = pkt_len - len;
- if (write_size > 24)
- write_size = 24;
- //printk("len=%d,write_size=%d,pkt_len=%d\n",len,write_size,pkt_len);
- memset (CMVMSG, 0, sizeof (CMVMSG));
- makeCMV (H2D_CMV_WRITE, INFO, 81, len / 2, (write_size + 1) / 2, (u16 *) (hdlc_pkt + len), CMVMSG); //Write clear eoc message to ARC
- ret = mei_ioctl ((struct inode *) 0, NULL,
- IFXMIPS_MEI_CMV_WINHOST,
- (unsigned long) CMVMSG);
- if (ret != 0) {
- return -EIO;
- }
- len += write_size;
- }
- makeCMV (H2D_CMV_WRITE, INFO, 83, 2, 1, &len, CMVMSG); //Update tx message length
- ret = mei_ioctl ((struct inode *) 0, NULL, IFXMIPS_MEI_CMV_WINHOST,
- (unsigned long) CMVMSG);
- if (ret != 0) {
- return -EIO;
- }
-
- data = (1 << 0);
- makeCMV (H2D_CMV_WRITE, CNTL, 2, 0, 1, &data, CMVMSG); //Start to send
- ret = mei_ioctl ((struct inode *) 0, NULL, IFXMIPS_MEI_CMV_WINHOST,
- (unsigned long) CMVMSG);
- if (ret != 0) {
- return -EIO;
- }
- return 0;
-}
-
-/**
- * Send hdlc packets
- *
- * \param hdlc_pkt Pointer to hdlc packet
- * \param hdlc_pkt_len The number of bytes to send
- * \return success or failure.
- * \ingroup Internal
- */
-int
-ifx_me_hdlc_send (unsigned char *hdlc_pkt, int hdlc_pkt_len)
-{
- int hdlc_status = 0;
- u16 CMVMSG[MSG_LENGTH];
- int max_hdlc_tx_length = 0, ret = 0, retry = 0;
- int power_mode = 0;
- int send_busy_counter = 0;
- int send_retry = 0;
-
- HDLC_SEND:
- // retry 1000 times (10 seconds)
- while (retry < 1000) {
- /* In L2 power mode, do not read the OHC related parameters,
- instead give the indication to the calling IOCTL,
- that the readout fails (just return -EBUSY). */
- power_mode = get_l3_power_status();
- if (power_mode == L2_POWER_MODE) {
- return -EBUSY;
- }
-
- hdlc_status = ifx_me_hdlc_status ();
- if (ifx_me_is_resloved (hdlc_status) == ME_HDLC_RESOLVED) // arc ready to send HDLC message
- {
- makeCMV (H2D_CMV_READ, INFO, 83, 0, 1, NULL, CMVMSG); //Get Maximum Allowed HDLC Tx Message Length
- ret = mei_ioctl ((struct inode *) 0, NULL,
- IFXMIPS_MEI_CMV_WINHOST,
- (unsigned long) CMVMSG);
- if (ret != 0) {
- printk
- ("ifx_me_hdlc_send failed. Return -EIO");
- return -EIO;
- }
- max_hdlc_tx_length = CMVMSG[4];
- ret = _ifx_me_hdlc_send (hdlc_pkt, hdlc_pkt_len,
- max_hdlc_tx_length);
- return ret;
- }
- else {
- if (hdlc_status == ME_HDLC_MSG_SENT)
- send_busy_counter++;
- }
- retry++;
- MEI_WAIT (1);
- }
- // wait 10 seconds and FW still report busy -> reset FW HDLC status
- if (send_busy_counter > 950 && send_retry == 0) {
- u16 data = 0;
- send_retry = 1;
- retry = 0;
- printk ("Reset FW HDLC status!!\n");
- send_busy_counter = 0;
- data = (1 << 1);
- makeCMV (H2D_CMV_WRITE, CNTL, 2, 0, 1, NULL, CMVMSG); //Force reset to idle
- ret = mei_ioctl ((struct inode *) 0, NULL,
- IFXMIPS_MEI_CMV_WINHOST,
- (unsigned long) CMVMSG);
- if (ret != 0) {
- return -EIO;
- }
- goto HDLC_SEND;
- }
- printk ("ifx_me_hdlc_send failed. Return -EBUSY");
- return -EBUSY;
-}
-
-/**
- * Read the hdlc packets
- *
- * \param hdlc_pkt Pointer to hdlc packet
- * \param hdlc_pkt_len The maximum number of bytes to read
- * \return The number of bytes which reads.
- * \ingroup Internal
- */
-int
-ifx_mei_hdlc_read (char *hdlc_pkt, int max_hdlc_pkt_len)
-{
- u16 CMVMSG[MSG_LENGTH];
- int msg_read_len, ret = 0, pkt_len = 0, retry = 0;
-
- while (retry < 10) {
- ret = ifx_me_hdlc_status ();
- if (ret == ME_HDLC_RESP_RCVD) {
- int current_size = 0;
- makeCMV (H2D_CMV_READ, INFO, 83, 3, 1, NULL, CMVMSG); //Get EoC packet length
- ret = mei_ioctl ((MEI_inode_t *) 0, NULL,
- IFXMIPS_MEI_CMV_WINHOST,
- (unsigned long) CMVMSG);
- if (ret != 0) {
- return -EIO;
- }
-
- pkt_len = CMVMSG[4];
- if (pkt_len > max_hdlc_pkt_len) {
- ret = -ENOMEM;
- goto error;
- }
- while (current_size < pkt_len) {
- if (pkt_len - current_size >
- (MSG_LENGTH * 2 - 8))
- msg_read_len = (MSG_LENGTH * 2 - 8);
- else
- msg_read_len =
- pkt_len - (current_size);
- makeCMV (H2D_CMV_READ, INFO, 82, 0 + (current_size / 2), (msg_read_len + 1) / 2, NULL, CMVMSG); //Get hdlc packet
- ret = mei_ioctl ((MEI_inode_t *) 0, NULL,
- IFXMIPS_MEI_CMV_WINHOST,
- (unsigned long) CMVMSG);
- if (ret != 0) {
- goto error;
- }
- memcpy (hdlc_pkt + current_size, &CMVMSG[4],
- msg_read_len);
- current_size += msg_read_len;
- }
- ret = current_size;
- break;
- }
- else {
- ret = -ENODATA;
- }
-
- retry++;
-
- MEI_WAIT (10);
- }
- error:
- return ret;
-}
-
-#if defined(IFXMIPS_CLEAR_EOC)
-int
-ifx_me_ceoc_send (struct sk_buff *eoc_pkt)
-{
- int ret, pkt_len = 0;
- unsigned char *pkt_data_ptr;
- int offset = 0;
- int swap_idx = 0;
-
- if (adsl_mode <= 8 && adsl_mode_extend == 0) // adsl mode
- {
- pkt_len = eoc_pkt->len;
-
- pkt_data_ptr = kmalloc (pkt_len + 3, GFP_KERNEL);
-
- offset = 2;
- pkt_data_ptr[0] = 0x4c;
- pkt_data_ptr[1] = 0x81;
- pkt_len += 2;
- } else {
- pkt_len = eoc_pkt->len + 4;
- pkt_data_ptr = kmalloc (pkt_len + 1 + 2, GFP_KERNEL);
- memset (pkt_data_ptr, 0, pkt_len + 1 + 2);
- //fill clear eoc header
- pkt_data_ptr[0] = 0x1;
- pkt_data_ptr[1] = 0x8;
- pkt_data_ptr[2] = 0x4c;
- pkt_data_ptr[3] = 0x81;
- offset = 4;
- }
- for (swap_idx = 0; swap_idx < (eoc_pkt->len / 2) * 2; swap_idx += 2)
- {
- //printk("%02X %02X ",eoc_pkt->data[swap_idx],eoc_pkt->data[swap_idx+1]);
- pkt_data_ptr[swap_idx + offset] = eoc_pkt->data[swap_idx + 1];
- pkt_data_ptr[swap_idx + 1 + offset] = eoc_pkt->data[swap_idx];
- }
- if (eoc_pkt->len % 2)
- {
- //printk("%02X ",eoc_pkt->data[eoc_pkt->len-1]);
- pkt_data_ptr[eoc_pkt->len - 1 + offset] =
- eoc_pkt->data[eoc_pkt->len - 1];
- pkt_data_ptr[eoc_pkt->len + offset] =
- eoc_pkt->data[eoc_pkt->len - 1];
- }
- ret = ifx_me_hdlc_send (pkt_data_ptr, pkt_len);
-
- if (pkt_data_ptr != eoc_pkt->data)
- {
- kfree (pkt_data_ptr);
- }
- dev_kfree_skb (eoc_pkt);
- return ret;
-}
-
-int
-get_me_ceoc_data (int pkt_len, int rx_buffer_addr, int rx_buffer_len,
- u8 * data_ptr1)
-{
- int ret;
- MEI_ERROR dma_ret;
- u16 CMVMSG[MSG_LENGTH];
- int read_size, aread_size;
- int offset = 0;
- u8 *data = NULL, *data_ptr = NULL;
- int i, j;
- int over_read = 0;
-
- i = j = 0;
-
- read_size = (pkt_len / 4) + 4;
- offset = ceoc_read_idx % 4;
- over_read = read_size * 4 - pkt_len - offset;
-
- ceoc_read_idx = (ceoc_read_idx & 0xFFFFFFFC);
-
- data = kmalloc (read_size * 4, GFP_KERNEL);
- if (data == NULL)
- goto error;
- data_ptr = kmalloc (read_size * 4, GFP_KERNEL);
- if (data_ptr == NULL)
- goto error;
- if (ceoc_read_idx + read_size * 4 >= rx_buffer_len) {
- aread_size = (rx_buffer_len - ceoc_read_idx) / 4;
- }
- else {
- aread_size = read_size;
- }
-
- //printk("aread_size = %d,ceoc_read_idx=%d,read_size=%d,offset=%d\n",aread_size,ceoc_read_idx,read_size,offset);
- dma_ret =
- meiDebugRead (rx_buffer_addr + ceoc_read_idx, (u32 *) (data),
- aread_size);
- ceoc_read_idx += aread_size * 4;
- if (aread_size != read_size) {
- dma_ret =
- meiDebugRead (rx_buffer_addr,
- (u32 *) (data) + aread_size,
- read_size - aread_size);
- ceoc_read_idx = (read_size - aread_size) * 4;
- }
- if (ceoc_read_idx < over_read)
- ceoc_read_idx = rx_buffer_len + ceoc_read_idx - over_read;
- else
- ceoc_read_idx -= over_read;
-
- if (offset == 0 || offset == 2) {
- for (i = 0; i < read_size; i++) {
- // 3412 --> 1234
-
- for (j = 0; j < 4; j++) {
- if (i * 4 + j - offset >= 0)
- data_ptr[i * 4 + j - offset] =
- data[i * 4 + (3 - j)];
- }
- }
-
- }
- else if (offset == 1) {
- for (i = 0; i < pkt_len; i = i + 4) {
-
- data_ptr[i + 1] = data[i + 1];
- data_ptr[i] = data[i + 2];
- data_ptr[i + 3] = data[i + 7];
- data_ptr[i + 2] = data[i];
- }
- }
- else if (offset == 3) {
- for (i = 0; i < pkt_len; i = i + 4) {
- data_ptr[i + 1] = data[i + 7];
- data_ptr[i + 0] = data[i];
- data_ptr[i + 3] = data[i + 5];
- data_ptr[i + 2] = data[i + 6];
- }
- }
- if (pkt_len % 2 == 1)
- data_ptr[pkt_len - 1] = data_ptr[pkt_len];
-
- kfree (data);
- memcpy (data_ptr1, data_ptr, pkt_len);
- kfree (data_ptr);
-
- makeCMV (H2D_CMV_WRITE, INFO, 85, 3, 1, &ceoc_read_idx, CMVMSG);
- ret = mei_ioctl ((struct inode *) 0, NULL, IFXMIPS_MEI_CMV_WINHOST,
- (unsigned long) CMVMSG);
- if (ret != 0) {
- goto error;
- }
-
- return dma_ret;
- error:
- kfree (data);
- kfree (data_ptr);
- return -1;
-}
-
-int
-ifx_me_ceoc_receive (int ceoc_write_idx, int rx_buffer_len,
- struct sk_buff **eoc_pkt)
-{
- u16 CMVMSG[MSG_LENGTH];
- int pkt_len, ret;
- u16 lsw_addr, msw_addr;
- u32 rx_buffer_addr = 0;
- MEI_ERROR dma_ret;
-
- //printk("rx_buffer_len=%d,ceoc_read_idx=%d,ceoc_write_idx=%d\n",rx_buffer_len,ceoc_read_idx,ceoc_write_idx);
- if (ceoc_write_idx > ceoc_read_idx) {
- pkt_len = ceoc_write_idx - ceoc_read_idx;
- }
- else {
- pkt_len = rx_buffer_len - ceoc_read_idx + ceoc_write_idx;
- }
- *eoc_pkt = dev_alloc_skb (pkt_len);
- if (*eoc_pkt == NULL) {
- printk ("Out of memory!\n");
- ret = -ENOMEM;
- goto error;
- }
-
- makeCMV (H2D_CMV_READ, INFO, 85, 0, 1, NULL, CMVMSG); //Get HDLC packet
- ret = mei_ioctl ((struct inode *) 0, NULL, IFXMIPS_MEI_CMV_WINHOST,
- (unsigned long) CMVMSG);
- if (ret != 0) {
- goto error;
- }
- lsw_addr = CMVMSG[4];
-
- makeCMV (H2D_CMV_READ, INFO, 85, 1, 1, NULL, CMVMSG); //Get HDLC packet
- ret = mei_ioctl ((struct inode *) 0, NULL, IFXMIPS_MEI_CMV_WINHOST,
- (unsigned long) CMVMSG);
- if (ret != 0) {
- goto error;
- }
- msw_addr = CMVMSG[4];
- rx_buffer_addr = msw_addr << 16 | lsw_addr;
- dma_ret =
- get_me_ceoc_data (pkt_len, rx_buffer_addr, rx_buffer_len,
- (u16 *) skb_put (*eoc_pkt, pkt_len));
- if (dma_ret != MEI_SUCCESS) {
- ret = -EIO;
- goto error;
- }
-
- return 0;
- error:
- if (*eoc_pkt != NULL)
- dev_kfree_skb (*eoc_pkt);
- return ret;
-}
-
-int
-ifx_mei_ceoc_rx (void)
-{
- u16 CMVMSG[MSG_LENGTH];
- int rx_buffer_len, ret, pkt_len = 0;
- struct sk_buff *eoc_pkt;
- u16 ceoc_write_idx = 0;
-
- makeCMV (H2D_CMV_READ, INFO, 85, 2, 1, NULL, CMVMSG); //Get EoC packet length
- ret = mei_ioctl ((struct inode *) 0, NULL, IFXMIPS_MEI_CMV_WINHOST,
- (unsigned long) CMVMSG);
- if (ret != 0) {
- printk ("ioctl fail!!\n");
- }
- rx_buffer_len = CMVMSG[4];
-
- makeCMV (H2D_CMV_READ, INFO, 85, 4, 1, NULL, CMVMSG); //Get write index
- ret = mei_ioctl ((struct inode *) 0, NULL, IFXMIPS_MEI_CMV_WINHOST,
- (unsigned long) CMVMSG);
- if (ret != 0) {
- return -EIO;
- }
-
- ceoc_write_idx = CMVMSG[4];
- ret = ifx_me_ceoc_receive (ceoc_write_idx, rx_buffer_len, &eoc_pkt);
-#if defined (CONFIG_ATM_IFXMIPS)
- if (ret == 0) {
- skb_pull (eoc_pkt, 2); // skip 4c 81 header
- ifx_push_ceoc (eoc_pkt); //pass data to higher layer
- }
-
- return ret;
-#endif
-}
-
-static int
-adsl_clear_eoc_poll (void *unused)
-{
- struct task_struct *tsk = current;
-
- daemonize("mei_eoc_poll");
- strcpy(tsk->comm, "mei_ceoc_poll");
- sigfillset(&tsk->blocked);
-
- while (1)
- {
- MEI_WAIT_EVENT (wait_queue_hdlc_poll);
- if (showtime)
- ifx_mei_ceoc_rx();
- }
- return 0;
-}
-#endif //#if defined(IFXMIPS_CLEAR_EOC)
-
-#ifdef IFXMIPS_CLEAR_EOC
-static int
-ifxmips_mei_ceoc_init (void)
-{
- kernel_thread (adsl_clear_eoc_poll, NULL,
- CLONE_FS | CLONE_FILES | CLONE_SIGNAL);
- return 0;
-}
-#endif
-
-////////////////////// Driver Structure ///////////////////////
-
-/**
- * Free the memory for ARC firmware
- *
- * \param type Free all memory or free the unused memory after showtime
- * \ingroup Internal
- */
-static int
-free_image_buffer (int type)
-{
- int idx = 0;
- for (idx = 0; idx < MAX_BAR_REGISTERS; idx++) {
- printk ("meminfo[%d].type=%d,size=%ld,addr=%X\n", idx,
- adsl_mem_info[idx].type, adsl_mem_info[idx].size,
- (unsigned int)adsl_mem_info[idx].address);
- if (type == FREE_ALL || adsl_mem_info[idx].type == type) {
- if (adsl_mem_info[idx].size > 0) {
- kfree (adsl_mem_info[idx].org_address);
- adsl_mem_info[idx].address = 0;
- adsl_mem_info[idx].size = 0;
- adsl_mem_info[idx].type = 0;
- adsl_mem_info[idx].nCopy = 0;
- }
- }
- }
- return 0;
-}
-
-/**
- * Allocate memory for ARC firmware
- *
- * \param size The number of bytes to allocate.
- * \param adsl_mem_info Pointer to firmware information.
- * \ingroup Internal
- */
-static int
-alloc_processor_memory (unsigned long size, smmu_mem_info_t * adsl_mem_info)
-{
- char *mem_ptr = NULL;
- char *org_mem_ptr = NULL;
- int idx = 0;
- long total_size = 0;
- long img_size = size;
- int err = 0;
-
- // Alloc Swap Pages
- while (img_size > 0 && idx < MAX_BAR_REGISTERS) {
- // skip bar15 for XDATA usage.
-#ifndef DFE_LOOPBACK
- if (idx == XDATA_REGISTER)
- idx++;
-#endif
- if (idx == MAX_BAR_REGISTERS - 1)
- {
- //allocate 1MB memory for bar16
- org_mem_ptr = kmalloc (1024 * 1024, GFP_ATOMIC);
- mem_ptr = (char*)((unsigned long) (org_mem_ptr + 1023) & 0xFFFFFC00);
- adsl_mem_info[idx].size = 1024 * 1024;
- } else {
- org_mem_ptr = kmalloc (SDRAM_SEGMENT_SIZE, GFP_ATOMIC);
- mem_ptr = (char*)((unsigned long) (org_mem_ptr + 1023) & 0xFFFFFC00);
- adsl_mem_info[idx].size = SDRAM_SEGMENT_SIZE;
- }
- if (org_mem_ptr == NULL)
- {
- printk ("kmalloc memory fail!\n");
- err = -ENOMEM;
- goto allocate_error;
- }
- adsl_mem_info[idx].address = mem_ptr;
- adsl_mem_info[idx].org_address = org_mem_ptr;
-
- img_size -= SDRAM_SEGMENT_SIZE;
- total_size += SDRAM_SEGMENT_SIZE;
- printk("alloc memory idx=%d,img_size=%ld,addr=%X\n",
- idx, img_size, (unsigned int)adsl_mem_info[idx].address);
- idx++;
- }
- if (img_size > 0)
- {
- printk ("Image size is too large!\n");
- err = -EFBIG;
- goto allocate_error;
- }
- err = idx;
- return err;
-
- allocate_error:
- free_image_buffer (FREE_ALL);
- return err;
-}
-
-/**
- * Program the BAR registers
- *
- * \param nTotalBar The number of bar to program.
- * \ingroup Internal
- */
-static int
-update_bar_register (int nTotalBar)
-{
- int idx = 0;
-
- for (idx = 0; idx < nTotalBar; idx++) {
- //skip XDATA register
- if (idx == XDATA_REGISTER)
- idx++;
- meiLongwordWrite ( MEI_XMEM_BAR_BASE + idx * 4,
- (((uint32_t) adsl_mem_info[idx].
- address) & 0x0FFFFFFF));
- printk ("BAR%d=%08X, addr=%08X\n", idx,
- (((uint32_t) adsl_mem_info[idx].
- address) & 0x0FFFFFFF),
- (((uint32_t) adsl_mem_info[idx].address)));
- }
- for (idx = nTotalBar; idx < MAX_BAR_REGISTERS; idx++) {
- if (idx == XDATA_REGISTER)
- idx++;
- meiLongwordWrite ( MEI_XMEM_BAR_BASE + idx * 4,
- (((uint32_t) adsl_mem_info[nTotalBar - 1].
- address) & 0x0FFFFFFF));
- }
-
- meiLongwordWrite (MEI_XMEM_BAR_BASE + XDATA_REGISTER * 4,
- (((uint32_t) adsl_mem_info[XDATA_REGISTER].
- address) & 0x0FFFFFFF));
- // update MEI_XDATA_BASE_SH
- printk ("update bar15 register with %08lX\n",
- ((unsigned long) adsl_mem_info[XDATA_REGISTER].
- address) & 0x0FFFFFFF);
- meiLongwordWrite (MEI_XDATA_BASE_SH,
- ((unsigned long) adsl_mem_info[XDATA_REGISTER].
- address) & 0x0FFFFFFF);
- return MEI_SUCCESS;
-}
-
-/**
- * Copy the firmware to BARs memory.
- *
- * \param filp Pointer to the file structure.
- * \param buf Pointer to the data.
- * \param size The number of bytes to copy.
- * \param loff The file offset.
- * \return The current file position.
- * \ingroup Internal
- */
-ssize_t
-mei_write (MEI_file_t * filp, char *buf, size_t size, loff_t * loff)
-{
- ARC_IMG_HDR img_hdr_tmp, *img_hdr;
-
- size_t nRead = 0, nCopy = 0;
- char *mem_ptr;
- ssize_t retval = -ENOMEM;
- int idx = 0;
-
- if (*loff == 0) {
- if (size < sizeof (img_hdr)) {
- printk ("Firmware size is too small!\n");
- return retval;
- }
- copy_from_user ((char *) &img_hdr_tmp, buf,
- sizeof (img_hdr_tmp));
- image_size = le32_to_cpu (img_hdr_tmp.size) + 8; // header of image_size and crc are not included.
- if (image_size > 1024 * 1024) {
- printk ("Firmware size is too large!\n");
- return retval;
- }
- // check if arc is halt
- if (arc_halt_flag != 1) {
- meiResetARC ();
- meiHaltArc ();
- }
-
- // reset part of PPE
- *(unsigned long *) (IFXMIPS_PPE32_SRST) = 0xC30;
- *(unsigned long *) (IFXMIPS_PPE32_SRST) = 0xFFF;
-
- free_image_buffer (FREE_ALL); //free all
-
- retval = alloc_processor_memory (image_size, adsl_mem_info);
- if (retval < 0) {
- printk ("Error: No memory space left.\n");
- goto error;
- }
-
- for (idx = 0; idx < retval; idx++) {
- //skip XDATA register
- if (idx == XDATA_REGISTER)
- idx++;
- if (idx * SDRAM_SEGMENT_SIZE <
- le32_to_cpu (img_hdr_tmp.page[0].p_offset)) {
- adsl_mem_info[idx].type = FREE_RELOAD;
- }
- else {
- adsl_mem_info[idx].type = FREE_SHOWTIME;
- }
-
- }
- nBar = retval;
-
- img_hdr = (ARC_IMG_HDR *) adsl_mem_info[0].address;
-
-#if !defined(__LINUX__)
- adsl_mem_info[XDATA_REGISTER].org_address =
- kmalloc (SDRAM_SEGMENT_SIZE + 1023, GFP_ATOMIC);
-#else
- adsl_mem_info[XDATA_REGISTER].org_address =
- kmalloc (SDRAM_SEGMENT_SIZE, GFP_ATOMIC);
-#endif
- adsl_mem_info[XDATA_REGISTER].address =
- (char
- *) ((unsigned long) (adsl_mem_info[XDATA_REGISTER].
- org_address +
- 1023) & 0xFFFFFC00);
- adsl_mem_info[XDATA_REGISTER].size = SDRAM_SEGMENT_SIZE;
- if (adsl_mem_info[XDATA_REGISTER].address == NULL) {
- printk ("kmalloc memory fail!\n");
- retval = -ENOMEM;
- goto error;
- }
- adsl_mem_info[XDATA_REGISTER].type = FREE_RELOAD;
- update_bar_register (nBar);
-
- }
- else if (image_size == 0) {
- printk ("Error: Firmware size=0! \n");
- goto error;
- }
- else {
- if (arc_halt_flag == 0) {
- printk
- ("Please download the firmware from the beginning of the firmware!\n");
- goto error;
- }
- }
-
- nRead = 0;
- while (nRead < size) {
- long offset = ((long) (*loff) + nRead) % SDRAM_SEGMENT_SIZE;
- idx = (((long) (*loff)) + nRead) / SDRAM_SEGMENT_SIZE;
- mem_ptr = (char *)
- KSEG1ADDR ((unsigned long) (adsl_mem_info[idx].
- address) + offset);
- if ((size - nRead + offset) > SDRAM_SEGMENT_SIZE)
- nCopy = SDRAM_SEGMENT_SIZE - offset;
- else
- nCopy = size - nRead;
- copy_from_user (mem_ptr, buf + nRead, nCopy);
-#ifdef IMAGE_SWAP
- for (offset = 0; offset < (nCopy / 4); offset++) {
- ((unsigned long *) mem_ptr)[offset] =
- le32_to_cpu (((unsigned long *)
- mem_ptr)[offset]);
- }
-#endif //IMAGE_SWAP
- nRead += nCopy;
- adsl_mem_info[idx].nCopy += nCopy;
- }
-
-#if ( defined(HEADER_SWAP) && !defined(IMAGE_SWAP)) || (defined(IMAGE_SWAP) && !defined(HEADER_SWAP))
- if (*loff == 0) {
-
- for (idx = 0;
- idx <
- (sizeof (ARC_IMG_HDR) +
- (le32_to_cpu (img_hdr_tmp.count) -
- 1) * sizeof (ARC_SWP_PAGE_HDR)) / 4; idx++) {
- ((unsigned long *) img_hdr)[idx] =
- le32_to_cpu (((unsigned long *)
- img_hdr)[idx]);
- }
- }
-#endif //( defined(HEADER_SWAP) && !defined(IMAGE_SWAP)) || (defined(IMAGE_SWAP) && !defined(HEADER_SWAP))
- printk ("size=%X,loff=%08X\n", size, (unsigned int) *loff);
-
- *loff += size;
- return size;
- error:
- free_image_buffer (FREE_ALL);
-
- return retval;
-}
-
-/********************************************************
- * L3 Power Mode *
- ********************************************************/
-/**
- * Send a CMV message.
- * This function sends a CMV message to ARC
- *
- * \param opcode The message opcode
- * \param group The message group number
- * \param address The message address.
- * \param index The message index.
- * \param size The number of words to read/write.
- * \param data The pointer to data.
- * \param CMVMSG The pointer to message buffer.
- * \return 0: success
- * \ingroup Internal
- */
-int
-send_cmv (u8 opcode, u8 group, u16 address, u16 index, int size, u16 * data, u16 * CMVMSG)
-{
- int ret;
-
- makeCMV(opcode, group, address, index, size, data, CMVMSG);
- ret = mei_ioctl((struct inode *) 0, NULL, IFXMIPS_MEI_CMV_WINHOST, (unsigned long)CMVMSG);
- return ret;
-}
-
-#ifdef IFX_ADSL_L3_MODE_SUPPORT
-
-/**
- * Check the L3 request from CO
- * This function Check if CPE received the L3 request from CO
- * \return 1: got L3 request.
- * \ingroup Internal
- */
-int
-check_co_l3_shutdown_request (void)
-{
- u16 CMVMSG[MSG_LENGTH];
- if (modem_ready == 1) {
- if (send_cmv (H2D_CMV_READ, STAT, 4, 0, 1, NULL, CMVMSG) != 0) {
- return -EBUSY;
- }
- if (CMVMSG[4] & BIT14) {
- return 1;
- }
- }
- return 0;
-}
-
-/**
- * Check the L3 status
- * This function get the CPE Power Management Mode status
- * \return 0: L0 Mode
- * 2: L2 Mode
- * 3: L3 Mode
- * \ingroup Internal
- */
-int
-get_l3_power_status (void)
-{
- u16 CMVMSG[MSG_LENGTH];
- if (modem_ready == 0) {
- return L3_POWER_MODE;
- }
- else {
- if (send_cmv (H2D_CMV_READ, STAT, 18, 0, 1, NULL, CMVMSG) !=
- 0) {
- return -EBUSY;
- }
- return ((int) CMVMSG[4]);
-
- }
- return 0;
-}
-
-/**
- * Send a L3 request to CO
- * This function send a L3 request to CO and check the CO response.
- * \return 0: Success. Others: Fail.
- * \ingroup Internal
- */
-int
-send_l3_shutdown_cmd (void)
-{
- u16 cmd = 0x1;
- int nRetry = 0;
- u16 CMVMSG[MSG_LENGTH];
-
- if (modem_ready == 0) {
- return -EBUSY;
- }
- // send l3 request to CO
- if (send_cmv (H2D_CMV_WRITE, CNTL, 3, 0, 1, &cmd, CMVMSG) != 0) {
- return -EBUSY;
- }
- retry:
- MEI_WAIT (10);
-
- // check CO response
- if (send_cmv (H2D_CMV_READ, STAT, 20, 0, 1, NULL, CMVMSG) != 0) {
- return -EBUSY;
- }
- if (CMVMSG[4] == 0) {
- nRetry++;
- if (nRetry < 10) {
- goto retry;
- }
- else {
- return -EBUSY;
- }
-
- }
- else if (CMVMSG[4] == 1) // reject
- {
- return -EPERM;
- }
- else if (CMVMSG[4] == 2) // ok
- {
- return 0;
- }
- else if (CMVMSG[4] == 3) // failure
- {
- return -EAGAIN;
- }
- return 0;
-}
-
-/**
- * Enable L3 Power Mode
- * This function send a L3 request to CO and check the CO response. Then reboot the CPE to enter L3 Mode.
- * \return 0: Success. Others: Fail.
- * \ingroup Internal
- */
-int
-set_l3_shutdown (void)
-{
- int ret = 0;
- if (l3_shutdown == 0) {
- // send l3 request to CO
- ret = send_l3_shutdown_cmd ();
- if (ret == 0) //got CO ACK
- {
- //reboot adsl and block autoboot daemon
- ret = mei_ioctl ((struct inode *) 0, NULL, IFXMIPS_MEI_REBOOT, (unsigned long)NULL);
- l3_shutdown = 1;
- }
- }
- return ret;
-}
-
-/**
- * Disable L3 Power Mode
- * This function disable L3 Mode and wake up the autoboot daemon.
- * \return 0: Success.
- * \ingroup Internal
- */
-//l3 power mode disable
-int
-set_l3_power_on (void)
-{
- if (l3_shutdown == 1) {
- l3_shutdown = 0;
- // wakeup autoboot daemon
- MEI_WAKEUP_EVENT (wait_queue_l3);
-
- }
- return 0;
-}
-
-/********************************************************
- * End of L3 Power Mode *
- ********************************************************/
-#endif //IFX_ADSL_L3_MODE_SUPPORT
-
-#ifdef CONFIG_IFXMIPS_MEI_LED
-/*
- * LED Initialization function
- */
-int
-meiADSLLedInit (void)
-{
- u16 data = 0x0600;
- u16 CMVMSG[MSG_LENGTH];
-
- data = 0x0400;
-#if defined(DATA_LED_SUPPORT) && defined (DATA_LED_ADSL_FW_HANDLE)
- data |= 0x200;
-#endif
- // Setup ADSL Link/Data LED
- if (send_cmv (H2D_CMV_WRITE, INFO, 91, 0, 1, &data, CMVMSG) != 0) {
- return -EBUSY;
- }
-
- if (send_cmv (H2D_CMV_WRITE, INFO, 91, 2, 1, &data, CMVMSG) != 0) {
- return -EBUSY;
- }
-
- // Let FW to handle ADSL Link LED
- data = 0x0a03; //invert the LED signal as per input from Stefan on 13/11/2006
- if (send_cmv (H2D_CMV_WRITE, INFO, 91, 4, 1, &data, CMVMSG) != 0) {
- return -EBUSY;
- }
-
-#ifdef DATA_LED_SUPPORT
-#ifdef DATA_LED_ADSL_FW_HANDLE
-
- // Turn ADSL Data LED on
- data = 0x0900;
- if (send_cmv (H2D_CMV_WRITE, INFO, 91, 5, 1, &data, CMVMSG) != 0) {
- return -EBUSY;
- }
-#else
- ifxmips_led_set(0x1);
-#endif
-#endif
- return 0;
-}
-#endif
-
-#ifdef IFX_ADSL_DUAL_LATENCY_SUPPORT
-/*
- * Dual Latency Path Initialization function
- */
-int
-meiDualLatencyInit (void)
-{
- u16 nDual = 0;
- u16 CMVMSG[MSG_LENGTH];
-
- // setup up stream path
- if (bDualLatency & DUAL_LATENCY_US_ENABLE) {
- nDual = 2;
- }
- else {
- nDual = 1;
- }
-
- if (send_cmv (H2D_CMV_WRITE, CNFG, 10, 0, 1, &nDual, CMVMSG) != 0) {
- return -EBUSY;
- }
-
- if (send_cmv (H2D_CMV_WRITE, CNFG, 11, 0, 1, &nDual, CMVMSG) != 0) {
- return -EBUSY;
- }
-
- // setup down stream path
- if (bDualLatency & DUAL_LATENCY_DS_ENABLE) {
- nDual = 2;
- }
- else {
- nDual = 1;
- }
-
- if (send_cmv (H2D_CMV_WRITE, CNFG, 21, 0, 1, &nDual, CMVMSG) != 0) {
- return -EBUSY;
- }
- if (send_cmv (H2D_CMV_WRITE, CNFG, 22, 0, 1, &nDual, CMVMSG) != 0) {
- return -EBUSY;
- }
- return 0;
-}
-
-int
-mei_is_dual_latency_enabled (void)
-{
- return bDualLatency;
-}
-#endif
-
-int
-meiAdslStartupInit (void)
-{
-#ifdef CONFIG_IFXMIPS_MEI_LED
- meiADSLLedInit ();
-#endif
-#ifdef IFX_ADSL_DUAL_LATENCY_SUPPORT
- meiDualLatencyInit ();
-#endif
- return 0;
-}
-
-/**
- * MEI IO controls for user space accessing
- *
- * \param ino Pointer to the stucture of inode.
- * \param fil Pointer to the stucture of file.
- * \param command The ioctl command.
- * \param lon The address of data.
- * \return Success or failure.
- * \ingroup Internal
- */
-int
-mei_ioctl (MEI_inode_t * ino, MEI_file_t * fil, unsigned int command,
- unsigned long lon)
-{
- int i;
-
- int meierr = MEI_SUCCESS;
- meireg regrdwr;
- meidebug debugrdwr;
- u32 arc_debug_data, reg_data;
-#ifdef IFXMIPS_CLEAR_EOC
- u16 data;
- struct sk_buff *eoc_skb;
-#endif //IFXMIPS_CLEAR_EOC
- u16 RxMessage[MSG_LENGTH] __attribute__ ((aligned (4)));
- u16 TxMessage[MSG_LENGTH] __attribute__ ((aligned (4)));
-
- int from_kernel = 0; //joelin
- if (ino == (MEI_inode_t *) 0)
- from_kernel = 1; //joelin
- if (command < IFXMIPS_MEI_START) {
-#ifdef CONFIG_IFXMIPS_MEI_MIB
- return mei_mib_ioctl (ino, fil, command, lon);
-#endif //CONFIG_IFXMIPS_MEI_MIB
-
- if (command == IFXMIPS_MIB_LO_ATUR
- || command == IFXMIPS_MIB_LO_ATUC)
- return MEI_SUCCESS;
- printk
- ("No such ioctl command (0x%X)! MEI ADSL MIB is not supported!\n",
- command);
- return -ENOIOCTLCMD;
- }
- else {
- switch (command) {
- case IFXMIPS_MEI_START:
-
- showtime = 0;
- loop_diagnostics_completed = 0;
- if (time_disconnect.tv_sec == 0)
- do_gettimeofday (&time_disconnect);
-
- if (MEI_MUTEX_LOCK (mei_sema)) //disable CMV access until ARC ready
- {
- printk ("-ERESTARTSYS\n");
- return -ERESTARTSYS;
- }
-
- meiMailboxInterruptsDisable (); //disable all MEI interrupts
- if (mei_arc_swap_buff == NULL) {
- mei_arc_swap_buff =
- (u32 *) kmalloc (MAXSWAPSIZE * 4,
- GFP_KERNEL);
- if (mei_arc_swap_buff == NULL) {
- printk
- ("\n\n malloc fail for codeswap buff");
- meierr = MEI_FAILURE;
- }
- }
- if (meiRunAdslModem () != MEI_SUCCESS) {
- printk
- ("meiRunAdslModem() error...");
- meierr = MEI_FAILURE;
- }
-#ifdef IFX_ADSL_L3_MODE_SUPPORT
- /* L3 Power Mode Start */
- if (l3_shutdown == 1) {
- // block autoboot daemon until l3 power mode disable
- MEI_WAIT_EVENT (wait_queue_l3);
- }
- /* L3 Power Mode End */
-#endif //IFX_ADSL_L3_MODE_SUPPORT
- if (autoboot_enable_flag)
- meiAdslStartupInit ();
- break;
-
- case IFXMIPS_MEI_SHOWTIME:
- if (MEI_MUTEX_LOCK (mei_sema))
- return -ERESTARTSYS;
-
- do_gettimeofday (&time_showtime);
- unavailable_seconds +=
- time_showtime.tv_sec - time_disconnect.tv_sec;
- time_disconnect.tv_sec = 0;
- makeCMV (H2D_CMV_READ, RATE, 0, 0, 4, NULL, TxMessage); //maximum allowed tx message length, in bytes
- if (meiCMV (TxMessage, YES_REPLY, RxMessage) !=
- MEI_SUCCESS) {
- printk
- ("\n\nCMV fail, Group RAGE Address 0 Index 0");
- }
- else {
- u32 rate_fast;
- u32 rate_intl;
- rate_intl = RxMessage[4] | RxMessage[5] << 16;
- rate_fast = RxMessage[6] | RxMessage[7] << 16;
- // 609251:tc.chen Fix ATM QoS issue start
- if (rate_intl && rate_fast) // apply cell rate to each path
- {
-#ifdef CONFIG_ATM_IFXMIPS
- ifx_atm_set_cell_rate (1,
- rate_intl /
- (53 * 8));
- ifx_atm_set_cell_rate (0,
- rate_fast /
- (53 * 8));
-#endif
- }
- else if (rate_fast) // apply fast path cell rate to atm interface 0
- {
-#ifdef CONFIG_ATM_IFXMIPS
- ifx_atm_set_cell_rate (0,
- rate_fast /
- (53 * 8));
-#endif
- }
- else if (rate_intl) // apply interleave path cell rate to atm interface 0
- {
-#ifdef CONFIG_ATM_IFXMIPS
- ifx_atm_set_cell_rate (0,
- rate_intl /
- (53 * 8));
-#endif
- }
- else {
- printk ("Got rate fail.\n");
- }
- // 609251:tc.chen end
- }
-
-#ifdef IFXMIPS_CLEAR_EOC
- data = 1;
- makeCMV (H2D_CMV_WRITE, OPTN, 24, 0, 1, &data,
- TxMessage);
- if (meiCMV (TxMessage, YES_REPLY, RxMessage) !=
- MEI_SUCCESS) {
- printk ("Enable clear eoc fail!\n");
- }
-#endif
- // read adsl mode
- makeCMV (H2D_CMV_READ, STAT, 1, 0, 1, NULL,
- TxMessage);
- if (meiCMV (TxMessage, YES_REPLY, RxMessage) !=
- MEI_SUCCESS) {
-#ifdef IFXMIPS_MEI_DEBUG_ON
- printk ("\n\nCMV fail, Group STAT Address 1 Index 0");
-#endif
- }
- adsl_mode = RxMessage[4];
- makeCMV (H2D_CMV_READ, STAT, 17, 0, 1, NULL,
- TxMessage);
- if (meiCMV (TxMessage, YES_REPLY, RxMessage) !=
- MEI_SUCCESS) {
-#ifdef IFXMIPS_MEI_DEBUG_ON
- printk ("\n\nCMV fail, Group STAT Address 1 Index 0");
-#endif
- }
- adsl_mode_extend = RxMessage[4];
-#ifdef CONFIG_IFXMIPS_MEI_MIB
- mei_mib_adsl_link_up ();
-#endif
-
-//joelin 04/16/2005-start
- makeCMV (H2D_CMV_WRITE, PLAM, 10, 0, 1,
- &unavailable_seconds, TxMessage);
- if (meiCMV (TxMessage, YES_REPLY, RxMessage) !=
- MEI_SUCCESS) {
- printk
- ("\n\nCMV fail, Group 7 Address 10 Index 0");
- }
-
-//joelin 04/16/2005-end
- showtime = 1;
- free_image_buffer (FREE_SHOWTIME);
- MEI_MUTEX_UNLOCK (mei_sema);
- break;
-
- case IFXMIPS_MEI_HALT:
- if (arc_halt_flag == 0) {
- meiResetARC ();
- meiHaltArc ();
- }
- break;
- case IFXMIPS_MEI_RUN:
- if (arc_halt_flag == 1) {
- meiRunArc ();
- }
- break;
- case IFXMIPS_MEI_CMV_WINHOST:
- if (MEI_MUTEX_LOCK (mei_sema))
- return -ERESTARTSYS;
-
- if (!from_kernel)
- copy_from_user ((char *) TxMessage, (char *) lon, MSG_LENGTH * 2); //joelin
- else
- memcpy (TxMessage, (char *) lon,
- MSG_LENGTH * 2);
-
- if (meiCMV (TxMessage, YES_REPLY, RxMessage) !=
- MEI_SUCCESS) {
- printk
- ("\n\nWINHOST CMV fail :TxMessage:%X %X %X %X, RxMessage:%X %X %X %X %X\n",
- TxMessage[0], TxMessage[1],
- TxMessage[2], TxMessage[3],
- RxMessage[0], RxMessage[1],
- RxMessage[2], RxMessage[3],
- RxMessage[4]);
- meierr = MEI_FAILURE;
- }
- else {
- if (!from_kernel) //joelin
- copy_to_user ((char *) lon,
- (char *) RxMessage,
- MSG_LENGTH * 2);
- else
- memcpy ((char *) lon,
- (char *) RxMessage,
- MSG_LENGTH * 2);
- }
-
- MEI_MUTEX_UNLOCK (mei_sema);
- break;
-#ifdef IFXMIPS_MEI_CMV_EXTRA
- case IFXMIPS_MEI_CMV_READ:
- copy_from_user ((char *) (®rdwr), (char *) lon,
- sizeof (meireg));
- meiLongwordRead ((u32*)regrdwr.iAddress, &(regrdwr.iData));
-
- copy_to_user((char *) lon, (char *) (®rdwr), sizeof (meireg));
- break;
-
- case IFXMIPS_MEI_CMV_WRITE:
- copy_from_user ((char *) (®rdwr), (char *) lon, sizeof (meireg));
- meiLongwordWrite ((u32*)regrdwr.iAddress, regrdwr.iData);
- break;
-
- case IFXMIPS_MEI_REMOTE:
- copy_from_user ((char *) (&i), (char *) lon,
- sizeof (int));
- if (i == 0) {
- meiMailboxInterruptsEnable ();
-
- MEI_MUTEX_UNLOCK (mei_sema);
- }
- else if (i == 1) {
- meiMailboxInterruptsDisable ();
- if (MEI_MUTEX_LOCK (mei_sema))
- return -ERESTARTSYS;
- }
- else {
- printk
- ("\n\n IFXMIPS_MEI_REMOTE argument error");
- meierr = MEI_FAILURE;
- }
- break;
-
- case IFXMIPS_MEI_READDEBUG:
- case IFXMIPS_MEI_WRITEDEBUG:
-#if 0 //tc.chen:It is no necessary to acquire lock to read debug memory!!
- if (MEI_MUTEX_LOCK (mei_sema))
- return -ERESTARTSYS;
-#endif
- if (!from_kernel)
- copy_from_user ((char *) (&debugrdwr),
- (char *) lon,
- sizeof (debugrdwr));
- else
- memcpy ((char *) (&debugrdwr), (char *) lon,
- sizeof (debugrdwr));
-
- if (command == IFXMIPS_MEI_READDEBUG)
- meiDebugRead (debugrdwr.iAddress,
- debugrdwr.buffer,
- debugrdwr.iCount);
- else
- meiDebugWrite (debugrdwr.iAddress,
- debugrdwr.buffer,
- debugrdwr.iCount);
-
- if (!from_kernel)
- copy_to_user ((char *) lon, (char *) (&debugrdwr), sizeof (debugrdwr)); //dying gasp
-#if 0 //tc.chen:It is no necessary to acquire lock to read debug memory!!
- MEI_MUTEX_UNLOCK (mei_sema);
-#endif
- break;
- case IFXMIPS_MEI_RESET:
- case IFXMIPS_MEI_REBOOT:
-
-#ifdef CONFIG_IFXMIPS_MEI_MIB
- mei_mib_adsl_link_down ();
-#endif
-
-#ifdef IFX_ADSL_L3_MODE_SUPPORT
- /* L3 Power Mode start */
- if (check_co_l3_shutdown_request () == 1) //co request
- {
- // cpe received co L3 request
- l3_shutdown = 1;
- }
- /* L3 Power Mode end */
-#endif //IFX_ADSL_L3_MODE_SUPPORT
-
- meiResetARC ();
- meiControlModeSwitch (MEI_MASTER_MODE);
- //enable ac_clk signal
- _meiDebugLongWordRead (MEI_DEBUG_DEC_DMP1_MASK,
- CRI_CCR0, &arc_debug_data);
- arc_debug_data |= ACL_CLK_MODE_ENABLE;
- _meiDebugLongWordWrite (MEI_DEBUG_DEC_DMP1_MASK,
- CRI_CCR0, arc_debug_data);
- meiControlModeSwitch (JTAG_MASTER_MODE);
- meiHaltArc ();
- update_bar_register (nBar);
- break;
- case IFXMIPS_MEI_DOWNLOAD:
- // DMA the boot code page(s)
- printk ("Start download pages");
- meiDownloadBootPages ();
- break;
-#endif //IFXMIPS_MEI_CMV_EXTRA
- //for clearEoC
-#ifdef IFXMIPS_CLEAR_EOC
- case IFXMIPS_MEI_EOC_SEND:
- if (!showtime) {
- return -EIO;
- }
- if (!from_kernel) {
- copy_from_user ((char *) (&debugrdwr),
- (char *) lon,
- sizeof (debugrdwr));
- eoc_skb =
- dev_alloc_skb (debugrdwr.iCount * 4);
- if (eoc_skb == NULL) {
- printk
- ("\n\nskb alloc fail");
- break;
- }
-
- eoc_skb->len = debugrdwr.iCount * 4;
- memcpy (skb_put
- (eoc_skb, debugrdwr.iCount * 4),
- (char *) debugrdwr.buffer,
- debugrdwr.iCount * 4);
- }
- else {
- eoc_skb = (struct sk_buff *) lon;
- }
- ifx_me_ceoc_send (eoc_skb); //pass data to higher layer
- break;
-#endif // IFXMIPS_CLEAR_EOC
- case IFXMIPS_MEI_JTAG_ENABLE:
- printk ("ARC JTAG Enable.\n");
- *(IFXMIPS_GPIO_P0_DIR) = (*IFXMIPS_GPIO_P0_DIR) & (~0x800); // set gpio11 to input
- *(IFXMIPS_GPIO_P0_ALTSEL0) = ((*IFXMIPS_GPIO_P0_ALTSEL0) & (~0x800));
- *(IFXMIPS_GPIO_P0_ALTSEL1) = ((*IFXMIPS_GPIO_P0_ALTSEL1) & (~0x800));
- *IFXMIPS_GPIO_P0_OD = (*IFXMIPS_GPIO_P0_OD) | 0x800;
-
- //enable ARC JTAG
- meiLongwordRead(IFXMIPS_RCU_RST, ®_data);
- meiLongwordWrite(IFXMIPS_RCU_RST, reg_data | IFXMIPS_RCU_RST_REQ_ARC_JTAG);
- break;
-
- case GET_ADSL_LOOP_DIAGNOSTICS_MODE:
- copy_to_user ((char *) lon, (char *) &loop_diagnostics_mode, sizeof(int));
- break;
- case LOOP_DIAGNOSTIC_MODE_COMPLETE:
- loop_diagnostics_completed = 1;
-#ifdef CONFIG_IFXMIPS_MEI_MIB
- // read adsl mode
- makeCMV (H2D_CMV_READ, STAT, 1, 0, 1, NULL, TxMessage);
- if (meiCMV (TxMessage, YES_REPLY, RxMessage) != MEI_SUCCESS) {
-#ifdef IFXMIPS_MEI_DEBUG_ON
- printk ("\n\nCMV fail, Group STAT Address 1 Index 0");
-#endif
- }
- adsl_mode = RxMessage[4];
-
- makeCMV (H2D_CMV_READ, STAT, 17, 0, 1, NULL, TxMessage);
- if (meiCMV (TxMessage, YES_REPLY, RxMessage) != MEI_SUCCESS) {
-#ifdef IFXMIPS_MEI_DEBUG_ON
- printk ("\n\nCMV fail, Group STAT Address 1 Index 0");
-#endif
- }
- adsl_mode_extend = RxMessage[4];
-#endif
- MEI_WAKEUP_EVENT (wait_queue_loop_diagnostic);
- break;
- case SET_ADSL_LOOP_DIAGNOSTICS_MODE:
- if (lon != loop_diagnostics_mode) {
- loop_diagnostics_completed = 0;
- loop_diagnostics_mode = lon;
-#if 0 //08/12/2006 tc.chen : autoboot daemon should reset dsl
- mei_ioctl ((MEI_inode_t *) 0, NULL,
- IFXMIPS_MEI_REBOOT,
- (unsigned long) NULL);
-#endif
- }
- break;
- case IS_ADSL_LOOP_DIAGNOSTICS_MODE_COMPLETE:
- copy_to_user ((char *) lon,
- (char *) &loop_diagnostics_completed,
- sizeof (int));
- break;
-#ifdef IFX_ADSL_L3_MODE_SUPPORT
- /* L3 Power Mode Start */
- case GET_POWER_MANAGEMENT_MODE:
- i = get_l3_power_status ();
- copy_to_user ((char *) lon, (char *) &i,
- sizeof (int));
- break;
- case SET_L3_POWER_MODE:
- i = 1;
- copy_from_user ((char *) &i, (char *) lon,
- sizeof (int));
- if (i == 0) {
- return set_l3_shutdown ();
- }
- else {
- return set_l3_power_on ();
- }
- break;
- /* L3 Power Mode End */
-#endif //IFX_ADSL_L3_MODE_SUPPORT
-#ifdef IFX_ADSL_DUAL_LATENCY_SUPPORT
- case GET_ADSL_DUAL_LATENCY:
- i = mei_is_dual_latency_enabled ();
- if (i < 0)
- return i;
- copy_to_user ((char *) lon, (char *) &i,
- sizeof (int));
- break;
- case SET_ADSL_DUAL_LATENCY:
- i = 0;
- copy_from_user ((char *) &i, (char *) lon,
- sizeof (int));
- if (i > DUAL_LATENCY_US_DS_ENABLE) {
- return -EINVAL;
- }
- if (i != bDualLatency) {
- bDualLatency = i;
- i = 1; // DualLatency update,need to reboot arc
- }
- else {
- i = 0; // DualLatency is the same
- }
- if (modem_ready && i) // modem is already start, reboot arc to apply Dual Latency changed
- {
- mei_ioctl ((MEI_inode_t *) 0, NULL,
- IFXMIPS_MEI_REBOOT,
- (unsigned long) NULL);
- }
- break;
-
-#endif
- case QUIET_MODE_GET:
- copy_to_user ((char *) lon, (char *) &quiet_mode_flag,
- sizeof (int));
- break;
- case QUIET_MODE_SET:
- copy_from_user ((char *) &i, (char *) lon,
- sizeof (int));
- if (i > 1 || i < 0)
- return -EINVAL;
- if (i == 1) {
- u16 CMVMSG[MSG_LENGTH];
- u16 data = 0;
- makeCMV (H2D_CMV_WRITE, INFO, 94, 0, 1, &data, CMVMSG); // set tx power to 0
- meierr = mei_ioctl ((struct inode *) 0, NULL,
- IFXMIPS_MEI_CMV_WINHOST,
- (unsigned long) CMVMSG);
- }
- quiet_mode_flag = i;
- break;
- case SHOWTIME_LOCK_GET:
- copy_to_user ((char *) lon,
- (char *) &showtime_lock_flag,
- sizeof (int));
- break;
- case SHOWTIME_LOCK_SET:
- copy_from_user ((char *) &i, (char *) lon,
- sizeof (int));
- if (i > 1 || i < 0)
- return -EINVAL;
- showtime_lock_flag = i;
- break;
- case AUTOBOOT_ENABLE_SET:
- copy_from_user ((char *) &i, (char *) lon,
- sizeof (int));
- if (i > 1 || i < 0)
- return -EINVAL;
- autoboot_enable_flag = i;
- break;
- default:
- printk
- ("The ioctl command(0x%X is not supported!\n",
- command);
- meierr = -ENOIOCTLCMD;
- }
- }
- return meierr;
-} //mei_ioctl
-
-//////////////////// procfs debug ///////////////////////////
-
-#ifdef CONFIG_PROC_FS
-static int
-proc_read (struct file *file, char *buf, size_t nbytes, loff_t * ppos)
-{
- int i_ino = (file->f_dentry->d_inode)->i_ino;
- char outputbuf[64];
- int count = 0;
- int i;
- u32 version = 0;
- reg_entry_t *current_reg = NULL;
- u16 RxMessage[MSG_LENGTH] __attribute__ ((aligned (4)));
- u16 TxMessage[MSG_LENGTH] __attribute__ ((aligned (4)));
-
- for (i = 0; i < NUM_OF_REG_ENTRY; i++) {
- if (regs[i].low_ino == i_ino) {
- current_reg = ®s[i];
- break;
- }
- }
- if (current_reg == NULL)
- return -EINVAL;
-
- if (current_reg->flag == (int *) 8) {
- ///proc/mei/version
- //format:
- //Firmware version: major.minor.sub_version.int_version.rel_state.spl_appl
- ///Firmware Date Time Code: date/month min:hour
- if (*ppos > 0) /* Assume reading completed in previous read */
- return 0; // indicates end of file
- if (MEI_MUTEX_LOCK (mei_sema))
- return -ERESTARTSYS;
-
- if (indicator_count < 1) {
- MEI_MUTEX_UNLOCK (mei_sema);
- return -EAGAIN;
- }
- //major:bits 0-7
- //minor:bits 8-15
- makeCMV (H2D_CMV_READ, INFO, 54, 0, 1, NULL, TxMessage);
- if (meiCMV (TxMessage, YES_REPLY, RxMessage) != MEI_SUCCESS) {
- MEI_MUTEX_UNLOCK (mei_sema);
- return -EIO;
- }
- version = RxMessage[4];
- count = sprintf (outputbuf, "%d.%d.", (version) & 0xff,
- (version >> 8) & 0xff);
-
- //sub_version:bits 4-7
- //int_version:bits 0-3
- //spl_appl:bits 8-13
- //rel_state:bits 14-15
- makeCMV (H2D_CMV_READ, INFO, 54, 1, 1, NULL, TxMessage);
- if (meiCMV (TxMessage, YES_REPLY, RxMessage) != MEI_SUCCESS) {
- MEI_MUTEX_UNLOCK (mei_sema);
- return -EFAULT;
- }
- version = RxMessage[4];
- count += sprintf (outputbuf + count, "%d.%d.%d.%d",
- (version >> 4) & 0xf,
- version & 0xf,
- (version >> 14) & 0x3,
- (version >> 8) & 0x3f);
- //Date:bits 0-7
- //Month:bits 8-15
- makeCMV (H2D_CMV_READ, INFO, 55, 0, 1, NULL, TxMessage);
- if (meiCMV (TxMessage, YES_REPLY, RxMessage) != MEI_SUCCESS) {
- MEI_MUTEX_UNLOCK (mei_sema);
- return -EIO;
- }
- version = RxMessage[4];
-
- //Hour:bits 0-7
- //Minute:bits 8-15
- makeCMV (H2D_CMV_READ, INFO, 55, 1, 1, NULL, TxMessage);
- if (meiCMV (TxMessage, YES_REPLY, RxMessage) != MEI_SUCCESS) {
- MEI_MUTEX_UNLOCK (mei_sema);
- return -EFAULT;
- }
- version += (RxMessage[4] << 16);
- count += sprintf (outputbuf + count, " %d/%d %d:%d\n",
- version & 0xff, (version >> 8) & 0xff,
- (version >> 25) & 0xff,
- (version >> 16) & 0xff);
- MEI_MUTEX_UNLOCK (mei_sema);
-
- *ppos += count;
- }
- else if (current_reg->flag != (int *) Recent_indicator) {
- if (*ppos > 0) /* Assume reading completed in previous read */
- return 0; // indicates end of file
- count = sprintf (outputbuf, "0x%08X\n\n",
- *(current_reg->flag));
- *ppos += count;
- if (count > nbytes) /* Assume output can be read at one time */
- return -EINVAL;
- }
- else {
- if ((int) (*ppos) / ((int) 7) == 16)
- return 0; // indicate end of the message
- count = sprintf (outputbuf, "0x%04X\n\n",
- *(((u16 *) (current_reg->flag)) +
- (int) (*ppos) / ((int) 7)));
- *ppos += count;
- }
- if (copy_to_user (buf, outputbuf, count))
- return -EFAULT;
- return count;
-}
-
-static ssize_t
-proc_write (struct file *file, const char *buffer, size_t count,
- loff_t * ppos)
-{
- int i_ino = (file->f_dentry->d_inode)->i_ino;
- reg_entry_t *current_reg = NULL;
- int i;
- unsigned long newRegValue;
- char *endp;
-
- for (i = 0; i < NUM_OF_REG_ENTRY; i++) {
- if (regs[i].low_ino == i_ino) {
- current_reg = ®s[i];
- break;
- }
- }
- if ((current_reg == NULL)
- || (current_reg->flag == (int *) Recent_indicator))
- return -EINVAL;
-
- newRegValue = simple_strtoul (buffer, &endp, 0);
- *(current_reg->flag) = (int) newRegValue;
- return (count + endp - buffer);
-}
-#endif //CONFIG_PROC_FS
-
-//TODO, for loopback test
-#ifdef DFE_LOOPBACK
-#define mte_reg_base (0x4800*4+0x20000)
-
-/* Iridia Registers Address Constants */
-#define MTE_Reg(r) (int)(mte_reg_base + (r*4))
-
-#define IT_AMODE MTE_Reg(0x0004)
-
-#define OMBOX_BASE 0xDF80
-#define OMBOX1 (OMBOX_BASE+0x4)
-#define IMBOX_BASE 0xDFC0
-
-#define TIMER_DELAY (1024)
-#define BC0_BYTES (32)
-#define BC1_BYTES (30)
-#define NUM_MB (12)
-#define TIMEOUT_VALUE 2000
-
-static void
-BFMWait (u32 cycle)
-{
- u32 i;
- for (i = 0; i < cycle; i++);
-}
-
-static void
-WriteRegLong (u32 addr, u32 data)
-{
- //*((volatile u32 *)(addr)) = data;
- IFXMIPS_WRITE_REGISTER_L (data, addr);
-}
-
-static u32
-ReadRegLong (u32 addr)
-{
- // u32 rd_val;
- //rd_val = *((volatile u32 *)(addr));
- // return rd_val;
- return IFXMIPS_READ_REGISTER_L (addr);
-}
-
-/* This routine writes the mailbox with the data in an input array */
-static void
-WriteMbox (u32 * mboxarray, u32 size)
-{
- meiDebugWrite (IMBOX_BASE, mboxarray, size);
- printk ("write to %X\n", IMBOX_BASE);
- meiLongwordWrite ( MEI_TO_ARC_INT, MEI_TO_ARC_MSGAV);
-}
-
-/* This routine reads the output mailbox and places the results into an array */
-static void
-ReadMbox (u32 * mboxarray, u32 size)
-{
- meiDebugRead (OMBOX_BASE, mboxarray, size);
- printk ("read from %X\n", OMBOX_BASE);
-}
-
-static void
-MEIWriteARCValue (u32 address, u32 value)
-{
- u32 i, check = 0;
-
- /* Write address register */
- IFXMIPS_WRITE_REGISTER_L (address, MEI_DEBUG_WAD);
-
- /* Write data register */
- IFXMIPS_WRITE_REGISTER_L (value, MEI_DEBUG_DATA);
-
- /* wait until complete - timeout at 40 */
- for (i = 0; i < 40; i++) {
- check = IFXMIPS_READ_REGISTER_L (ARC_TO_MEI_INT);
-
- if ((check & ARC_TO_MEI_DBG_DONE))
- break;
- }
- /* clear the flag */
- IFXMIPS_WRITE_REGISTER_L (ARC_TO_MEI_DBG_DONE, ARC_TO_MEI_INT);
-}
-
-void
-arc_code_page_download (uint32_t arc_code_length, uint32_t * start_address)
-{
- int count;
- printk ("try to download pages,size=%d\n", arc_code_length);
- meiControlModeSwitch (MEI_MASTER_MODE);
- if (arc_halt_flag == 0) {
- meiHaltArc ();
- }
- meiLongwordWrite ( MEI_XFR_ADDR, 0);
- for (count = 0; count < arc_code_length; count++) {
- meiLongwordWrite ( MEI_DATA_XFR,
- *(start_address + count));
- }
- meiControlModeSwitch (JTAG_MASTER_MODE);
-}
-static int
-load_jump_table (unsigned long addr)
-{
- int i;
- uint32_t addr_le, addr_be;
- uint32_t jump_table[32];
- for (i = 0; i < 16; i++) {
- addr_le = i * 8 + addr;
- addr_be = ((addr_le >> 16) & 0xffff);
- addr_be |= ((addr_le & 0xffff) << 16);
- jump_table[i * 2 + 0] = 0x0f802020;
- jump_table[i * 2 + 1] = addr_be;
- //printk("jt %X %08X %08X\n",i,jump_table[i*2+0],jump_table[i*2+1]);
- }
- arc_code_page_download (32, &jump_table[0]);
- return 0;
-}
-
-void
-dfe_loopback_irq_handler (void)
-{
- uint32_t rd_mbox[10];
-
- memset (&rd_mbox[0], 0, 10 * 4);
- ReadMbox (&rd_mbox[0], 6);
- if (rd_mbox[0] == 0x0) {
- printk ("Get ARC_ACK\n");
- got_int = 1;
- }
- else if (rd_mbox[0] == 0x5) {
- printk ("Get ARC_BUSY\n");
- got_int = 2;
- }
- else if (rd_mbox[0] == 0x3) {
- printk ("Get ARC_EDONE\n");
- if (rd_mbox[1] == 0x0) {
- got_int = 3;
- printk ("Get E_MEMTEST\n");
- if (rd_mbox[2] != 0x1) {
- got_int = 4;
- printk ("Get Result %X\n",
- rd_mbox[2]);
- }
- }
- }
- meiLongwordWrite ( ARC_TO_MEI_INT, ARC_TO_MEI_DBG_DONE);
- MEI_MASK_AND_ACK_IRQ (IFXMIPS_MEI_INT);
- disable_irq (IFXMIPS_MEI_INT);
- //got_int = 1;
- return;
-}
-
-static void
-wait_mem_test_result (void)
-{
- uint32_t mbox[5];
- mbox[0] = 0;
- printk ("Waiting Starting\n");
- while (mbox[0] == 0) {
- ReadMbox (&mbox[0], 5);
- }
- printk ("Try to get mem test result.\n");
- ReadMbox (&mbox[0], 5);
- if (mbox[0] == 0xA) {
- printk ("Success.\n");
- }
- else if (mbox[0] == 0xA) {
- printk
- ("Fail,address %X,except data %X,receive data %X\n",
- mbox[1], mbox[2], mbox[3]);
- }
- else {
- printk ("Fail\n");
- }
-}
-
-static int
-arc_ping_testing (void)
-{
-#define MEI_PING 0x00000001
- uint32_t wr_mbox[10], rd_mbox[10];
- int i;
- for (i = 0; i < 10; i++) {
- wr_mbox[i] = 0;
- rd_mbox[i] = 0;
- }
-
- printk ("send ping msg\n");
- wr_mbox[0] = MEI_PING;
- WriteMbox (&wr_mbox[0], 10);
-
- while (got_int == 0) {
- MEI_WAIT (100);
- }
-
- printk ("send start event\n");
- got_int = 0;
-
- wr_mbox[0] = 0x4;
- wr_mbox[1] = 0;
- wr_mbox[2] = 0;
- wr_mbox[3] = (uint32_t) 0xf5acc307e;
- wr_mbox[4] = 5;
- wr_mbox[5] = 2;
- wr_mbox[6] = 0x1c000;
- wr_mbox[7] = 64;
- wr_mbox[8] = 0;
- wr_mbox[9] = 0;
- WriteMbox (&wr_mbox[0], 10);
- enable_irq (IFXMIPS_MEI_INT);
- //printk("meiMailboxWrite ret=%d\n",i);
- meiLongwordWrite ( MEI_TO_ARC_INT, MEI_TO_ARC_MSGAV);
- printk ("sleeping\n");
- while (1) {
- if (got_int > 0) {
-
- if (got_int > 3)
- printk ("got_int >>>> 3\n");
- else
- printk ("got int = %d\n", got_int);
- got_int = 0;
- //schedule();
- enable_irq (IFXMIPS_MEI_INT);
- }
- //mbox_read(&rd_mbox[0],6);
- MEI_WAIT (100);
- }
-}
-
-static MEI_ERROR
-DFE_Loopback_Test (void)
-{
- int i = 0;
- u32 arc_debug_data = 0, temp;
-
- meiResetARC ();
- // start the clock
- arc_debug_data = ACL_CLK_MODE_ENABLE;
- meiDebugWrite (CRI_CCR0, &arc_debug_data, 1);
-
-#if defined( DFE_PING_TEST )|| defined( DFE_ATM_LOOPBACK)
- // WriteARCreg(AUX_XMEM_LTEST,0);
- meiControlModeSwitch (MEI_MASTER_MODE);
-#define AUX_XMEM_LTEST 0x128
- _meiDebugLongWordWrite (MEI_DEBUG_DEC_AUX_MASK, AUX_XMEM_LTEST, 0);
- meiControlModeSwitch (JTAG_MASTER_MODE);
-
- // WriteARCreg(AUX_XDMA_GAP,0);
- meiControlModeSwitch (MEI_MASTER_MODE);
-#define AUX_XDMA_GAP 0x114
- _meiDebugLongWordWrite (MEI_DEBUG_DEC_AUX_MASK, AUX_XDMA_GAP, 0);
- meiControlModeSwitch (JTAG_MASTER_MODE);
-
- meiControlModeSwitch (MEI_MASTER_MODE);
- temp = 0;
- _meiDebugLongWordWrite (MEI_DEBUG_DEC_AUX_MASK,
- (u32) MEI_XDATA_BASE_SH, temp);
- meiControlModeSwitch (JTAG_MASTER_MODE);
-
- i = alloc_processor_memory (SDRAM_SEGMENT_SIZE * 16, adsl_mem_info);
- if (i >= 0) {
- int idx;
-
- for (idx = 0; idx < i; idx++) {
- adsl_mem_info[idx].type = FREE_RELOAD;
- IFXMIPS_WRITE_REGISTER_L ((((uint32_t)
- adsl_mem_info[idx].
- address) & 0x0fffffff),
- MEI_XMEM_BAR_BASE + idx * 4);
- printk ("bar%d(%X)=%X\n", idx,
- MEI_XMEM_BAR_BASE + idx * 4,
- (((uint32_t) adsl_mem_info[idx].
- address) & 0x0fffffff));
- memset ((u8 *) adsl_mem_info[idx].address, 0,
- SDRAM_SEGMENT_SIZE);
- }
-
- meiLongwordWrite ( MEI_XDATA_BASE_SH, ((unsigned long)
- adsl_mem_info
- [XDATA_REGISTER].
- address) &
- 0x0FFFFFFF);
-
- }
- else {
- printk ("cannot load image: no memory\n\n");
- return MEI_FAILURE;
- }
- //WriteARCreg(AUX_IC_CTRL,2);
- meiControlModeSwitch (MEI_MASTER_MODE);
-#define AUX_IC_CTRL 0x11
- _meiDebugLongWordWrite (MEI_DEBUG_DEC_AUX_MASK, AUX_IC_CTRL, 2);
- meiControlModeSwitch (JTAG_MASTER_MODE);
-
- meiHaltArc ();
-
-#ifdef DFE_PING_TEST
-
- printk ("ping test image size=%d\n", sizeof (code_array));
- memcpy ((u8 *) (adsl_mem_info[0].address + 0x1004), &code_array[0],
- sizeof (code_array));
- load_jump_table (0x80000 + 0x1004);
-
-#endif //DFE_PING_TEST
-
- printk ("ARC ping test code download complete\n");
-#endif //defined( DFE_PING_TEST )|| defined( DFE_ATM_LOOPBACK)
-#ifdef DFE_MEM_TEST
- meiLongwordWrite (ARC_TO_MEI_INT_MASK, MSGAV_EN);
-
- arc_code_page_download (1537, &mem_test_code_array[0]);
- printk ("ARC mem test code download complete\n");
-#endif //DFE_MEM_TEST
-#ifdef DFE_ATM_LOOPBACK
- arc_debug_data = 0xf;
- arc_code_page_download (1077, &code_array[0]);
- // Start Iridia IT_AMODE (in dmp access) why is it required?
- meiDebugWrite (0x32010, &arc_debug_data, 1);
-#endif //DFE_ATM_LOOPBACK
- meiMailboxInterruptsEnable ();
- meiRunArc ();
-
-#ifdef DFE_PING_TEST
- arc_ping_testing ();
-#endif //DFE_PING_TEST
-#ifdef DFE_MEM_TEST
- wait_mem_test_result ();
-#endif //DFE_MEM_TEST
-
- free_image_buffer (FREE_ALL);
- return MEI_SUCCESS;
-}
-
-#endif //DFE_LOOPBACK
-//end of TODO, for loopback test
-
-#if defined(CONFIG_IFXMIPS_MEI_LED) && defined(DATA_LED_SUPPORT)
-
-/*
- * Led Thread Main function
- */
-static int
-led_poll (void *unused)
-{
- struct task_struct *tsk = current;
-
- daemonize("mei_led_poll");
- strcpy (tsk->comm, "atm_led");
- sigfillset (&tsk->blocked);
-
- stop_led_module = 0; //begin polling ...
-
- while (!stop_led_module) {
- if (led_status_on || led_need_to_flash) {
- adsl_led_flash_task ();
- }
- if (led_status_on) //sleep 200 ms to check if need to turn led off
- {
- interruptible_sleep_on_timeout
- (&wait_queue_led_polling, 25);
- }
- else {
- interruptible_sleep_on (&wait_queue_led_polling);
- }
- }
- return 0;
-}
-
-/*
- * API for atm driver to notify led thread a data coming/sending
- */
-#if defined (CONFIG_ATM_IFXMIPS)
-static int
-adsl_led_flash (void)
-{
- if (!modem_ready)
- return 0;
-
- if (led_status_on == 0 && led_need_to_flash == 0)
- {
- wake_up_interruptible (&wait_queue_led_polling); //wake up and clean led module
- }
- led_need_to_flash = 1; //asking to flash led
-
- return 0;
-}
-#endif
-/*
- * Main task for led controlling.
- */
-static int
-adsl_led_flash_task (void)
-{
-#ifdef DATA_LED_ADSL_FW_HANDLE
- u16 one = 1;
- u16 zero = 0;
- u16 data = 0x0600;
- u16 CMVMSG[MSG_LENGTH];
-#endif
-
-// printk("Task Running...\n"); //joelin test
-
- if (!showtime) {
- led_need_to_flash = 0;
- led_status_on = 0;
- return 0;
- }
-
- if (led_status_on == 0 && led_need_to_flash == 1) {
-
-#ifdef DATA_LED_ADSL_FW_HANDLE
- data = 0x0901; //flash
- send_cmv (H2D_CMV_WRITE, INFO, 91, 5, 1, &data, CMVMSG); //use GPIO9 for TR68 data led .flash.
-#else
- ifxmips_led_blink_set(0x0); // data
- ifxmips_led_blink_set(0x1); // link
-#endif
- led_status_on = 1;
-
- }
- else if (led_status_on == 1 && led_need_to_flash == 0) {
-#ifdef DATA_LED_ADSL_FW_HANDLE
-#ifdef DATA_LED_ON_MODE
- data = 0x0903; //use GPIO9 for TR68 data led .turn on.
-#else
- data = 0x0900; //off
-#endif
- printk ("off %04X\n", data);
- send_cmv (H2D_CMV_WRITE, INFO, 91, 5, 1, &data, CMVMSG); //use GPIO9 for TR68 data led .off.
-#else
-#endif
- led_status_on = 0;
- }
- led_need_to_flash = 0;
- return 0;
-}
-
-/*
- * Led initialization function
- * This function create a thread to polling atm traffic and do led blanking
- */
-static int
-ifxmips_mei_led_init (void)
-{
- init_waitqueue_head (&wait_queue_led_polling); // adsl led for led function
- kernel_thread (led_poll, NULL, CLONE_FS | CLONE_FILES | CLONE_SIGHAND | CLONE_THREAD);
- return 0;
-}
-
-/*
- * Led destory function
- */
-static int
-ifxmips_mei_led_cleanup (void)
-{
- stop_led_module = 1; //wake up and clean led module
- wake_up_interruptible (&wait_queue_led_polling); //wake up and clean led module
- return 0;
-}
-#endif //#ifdef CONFIG_IFXMIPS_MEI_LED
-
-////////////////////////////////////////////////////////////////////////////
-int __init
-ifxmips_mei_init_module (void)
-{
- struct proc_dir_entry *entry;
- int i;
- u32 temp;
-#ifdef CONFIG_DEVFS_FS
- char buf[10];
-#endif
- reg_entry_t regs_temp[PROC_ITEMS] = // Items being debugged
- {
- /* { flag, name, description } */
- {&arcmsgav, "arcmsgav", "arc to mei message ", 0},
- {&cmv_reply, "cmv_reply", "cmv needs reply", 0},
- {&cmv_waiting, "cmv_waiting",
- "waiting for cmv reply from arc", 0},
- {&indicator_count, "indicator_count",
- "ARC to MEI indicator count", 0},
- {&cmv_count, "cmv_count", "MEI to ARC CMVs", 0},
- {&reply_count, "reply_count", "ARC to MEI Reply", 0},
- {(int *) Recent_indicator, "Recent_indicator",
- "most recent indicator", 0},
- {(int *) 8, "version", "version of firmware", 0},
- };
- do_gettimeofday (&time_disconnect);
-
- printk ("Danube MEI version:%s\n", IFXMIPS_MEI_VERSION);
-
- memcpy ((char *) regs, (char *) regs_temp, sizeof (regs_temp));
- MEI_MUTEX_INIT (mei_sema, 1); // semaphore initialization, mutex
- MEI_INIT_WAKELIST ("arcq", wait_queue_arcmsgav); // for ARCMSGAV
- MEI_INIT_WAKELIST ("arcldq", wait_queue_loop_diagnostic); // for loop diagnostic function
-#ifdef IFX_ADSL_L3_MODE_SUPPORT
- MEI_INIT_WAKELIST ("arcl3q", wait_queue_l3); // for l3 power mode
-#endif //IFX_ADSL_L3_MODE_SUPPORT
-
-
- memset (&adsl_mem_info[0], 0, sizeof (smmu_mem_info_t) * MAX_BAR_REGISTERS);
-#if defined(CONFIG_IFXMIPS_MEI_LED) && defined(DATA_LED_SUPPORT)
- printk("not enabling mei leds due to bug that makes the board hang\n");
-// ifxmips_mei_led_init ();
-#endif
-
-#ifdef CONFIG_IFXMIPS_MEI_MIB
- ifxmips_mei_mib_init ();
-#endif
-
-#ifdef IFXMIPS_CLEAR_EOC
- MEI_INIT_WAKELIST ("arceoc", wait_queue_hdlc_poll);
- ifxmips_mei_ceoc_init ();
-#endif
- // power up mei
- temp = ifxmips_r32(IFXMIPS_PMU_PWDCR);
- temp &= 0xffff7dbe;
- ifxmips_w32(temp, IFXMIPS_PMU_PWDCR);
-
-#if defined (CONFIG_ATM_IFXMIPS)
- IFX_ATM_LED_Callback_Register (adsl_led_flash);
-#endif
- if (register_chrdev (major, IFXMIPS_MEI_DEVNAME, &mei_operations) != 0) {
- printk("\n\n unable to register major for ifxmips_mei!!!");
- return -ENODEV;
- } else {
- printk("registered ifxmips_mei on #%d\n", major);
- }
-
- disable_irq(IFXMIPS_MEI_INT);
-
- if (request_irq(IFXMIPS_MEI_INT, mei_interrupt_arcmsgav, 0, "ifxmips_mei_arcmsgav", NULL) != 0) {
- printk("\n\n unable to register irq(%d) for ifxmips_mei!!!",
- IFXMIPS_MEI_INT);
- return -1;
- }
-
-// enable_irq(IFXMIPS_MEI_INT);
- // procfs
- meidir = proc_mkdir(MEI_DIRNAME, &proc_root);
- if (meidir == NULL)
- {
- printk(": can't create /proc/" MEI_DIRNAME "\n\n");
- return -ENOMEM;
- }
-
- for (i = 0; i < NUM_OF_REG_ENTRY; i++) {
- entry = create_proc_entry (regs[i].name,
- S_IWUSR | S_IRUSR | S_IRGRP | S_IROTH, meidir);
- if (entry)
- {
- regs[i].low_ino = entry->low_ino;
- entry->proc_fops = &proc_operations;
- } else {
- printk (": can't create /proc/" MEI_DIRNAME "/%s\n\n", regs[i].name);
- return -ENOMEM;
- }
- }
-
- ///////////////////////////////// register net device ////////////////////////////
-#ifdef DFE_LOOPBACK
- DFE_Loopback_Test ();
-#endif //DFE_LOOPBACK
- return 0;
-}
-
-void __exit
-ifxmips_mei_cleanup_module (void)
-{
- int i;
-
-#if defined(CONFIG_IFXMIPS_MEI_LED) && defined(DATA_LED_SUPPORT)
- ifxmips_mei_led_cleanup ();
-#endif
- showtime = 0; //joelin,clear task
-
-#ifdef CONFIG_PROC_FS
- for (i = 0; i < NUM_OF_REG_ENTRY; i++)
- remove_proc_entry (regs[i].name, meidir);
-
- remove_proc_entry (MEI_DIRNAME, &proc_root);
-#endif //CONFIG_PROC_FS
-
-#if defined (CONFIG_ATM_IFXMIPS)
- IFX_ATM_LED_Callback_Unregister (adsl_led_flash);
-#endif
- disable_irq (IFXMIPS_MEI_INT);
- free_irq(IFXMIPS_MEI_INT, NULL);
-
-#ifdef CONFIG_DEVFS_FS
- devfs_unregister (mei_devfs_handle);
-#else
- unregister_chrdev (major, "ifxmips_mei");
-#endif
-#ifdef CONFIG_IFXMIPS_MEI_MIB
- ifxmips_mei_mib_cleanup ();
-#endif
-
- free_image_buffer (FREE_ALL);
- return;
-}
-
-EXPORT_SYMBOL (meiDebugRead);
-EXPORT_SYMBOL (meiDebugWrite);
-EXPORT_SYMBOL (ifx_me_hdlc_send);
-EXPORT_SYMBOL (ifx_mei_hdlc_read);
-MODULE_LICENSE ("GPL");
-
-module_init (ifxmips_mei_init_module);
-module_exit (ifxmips_mei_cleanup_module);
+++ /dev/null
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- * Copyright(C) 2006 infineon
- * Copyright(C) 2007 John Crispin <blogic@openwrt.org>
- *
- */
-
-/*
-### TO DO: general issues:
- - power management
- - interrupt handling (direct/indirect)
- - pin/mux-handling (just overall concept due to project dependency)
- - multiple instances capability
- - slave functionality
-*/
-
-#include <linux/module.h>
-#include <linux/errno.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/timer.h>
-#include <linux/interrupt.h>
-#include <linux/major.h>
-#include <linux/string.h>
-#include <linux/fs.h>
-#include <linux/fcntl.h>
-#include <linux/ptrace.h>
-#include <linux/mm.h>
-#include <linux/ioport.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/spinlock.h>
-#include <linux/slab.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/uaccess.h>
-#include <linux/bitops.h>
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/version.h>
-
-#include <asm/system.h>
-#include <asm/ifxmips/ifxmips.h>
-#include <asm/ifxmips/ifxmips_irq.h>
-#include <asm/ifxmips/ifx_ssc_defines.h>
-#include <asm/ifxmips/ifx_ssc.h>
-
-/* allow the user to set the major device number */
-static int maj;
-
-/*
- * This is the per-channel data structure containing pointers, flags
- * and variables for the port. This driver supports a maximum of PORT_CNT.
- * isp is allocated in ifx_ssc_init() based on the chip version.
- */
-static struct ifx_ssc_port *isp;
-
-/* other forward declarations */
-static unsigned int ifx_ssc_get_kernel_clk(struct ifx_ssc_port *info);
-static void tx_int(struct ifx_ssc_port *);
-
-extern unsigned int ifxmips_get_fpi_hz(void);
-extern void ifxmips_mask_and_ack_irq(unsigned int irq_nr);
-
-static inline unsigned int ifx_ssc_get_kernel_clk(struct ifx_ssc_port *info)
-{
- unsigned int rmc;
-
- rmc = (ifxmips_r32(IFXMIPS_SSC_CLC) & IFX_CLC_RUN_DIVIDER_MASK) >> IFX_CLC_RUN_DIVIDER_OFFSET;
- if (rmc == 0) {
- printk("ifx_ssc_get_kernel_clk rmc==0 \n");
- return 0;
- }
- return ifxmips_get_fpi_hz() / rmc;
-}
-
-static inline void rx_int(struct ifx_ssc_port *info)
-{
- int fifo_fill_lev, bytes_in_buf, i;
- unsigned long tmp_val;
- unsigned long *tmp_ptr;
- unsigned int rx_valid_cnt;
- /* number of words waiting in the RX FIFO */
- fifo_fill_lev = (ifxmips_r32(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_RECEIVED_WORDS_MASK) >> IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET;
- bytes_in_buf = info->rxbuf_end - info->rxbuf_ptr;
- /* transfer with 32 bits per entry */
- while ((bytes_in_buf >= 4) && (fifo_fill_lev > 0)) {
- tmp_ptr = (unsigned long *)info->rxbuf_ptr;
- *tmp_ptr = ifxmips_r32(IFXMIPS_SSC_RB);
- info->rxbuf_ptr += 4;
- info->stats.rxBytes += 4;
- fifo_fill_lev--;
- bytes_in_buf -= 4;
- }
-
- /* now do the rest as mentioned in STATE.RXBV */
- while ((bytes_in_buf > 0) && (fifo_fill_lev > 0)) {
- rx_valid_cnt = (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET;
- if (rx_valid_cnt == 0)
- break;
-
- if (rx_valid_cnt > bytes_in_buf)
- rx_valid_cnt = bytes_in_buf;
-
- tmp_val = ifxmips_r32(IFXMIPS_SSC_RB);
-
- for (i = 0; i < rx_valid_cnt; i++) {
- *info->rxbuf_ptr = (tmp_val >> (8 * (rx_valid_cnt - i - 1))) & 0xff;
- bytes_in_buf--;
- info->rxbuf_ptr++;
- }
- info->stats.rxBytes += rx_valid_cnt;
- }
-
- /* check if transfer is complete */
- if (info->rxbuf_ptr >= info->rxbuf_end) {
- disable_irq(IFXMIPS_SSC_RIR);
- wake_up_interruptible(&info->rwait);
- } else if ((info->opts.modeRxTx == IFX_SSC_MODE_RX) && (ifxmips_r32(IFXMIPS_SSC_RXCNT) == 0)) {
- if (info->rxbuf_end - info->rxbuf_ptr < IFX_SSC_RXREQ_BLOCK_SIZE)
- ifxmips_w32((info->rxbuf_end - info->rxbuf_ptr) << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
- else
- ifxmips_w32(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
- }
-}
-
-static inline void tx_int(struct ifx_ssc_port *info)
-{
-
- int fifo_space, fill, i;
- fifo_space = ((ifxmips_r32(IFXMIPS_SSC_ID) & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET)
- -((ifxmips_r32(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK) >> IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET);
-
- if (fifo_space == 0)
- return;
-
- fill = info->txbuf_end - info->txbuf_ptr;
-
- if (fill > fifo_space * 4)
- fill = fifo_space * 4;
-
- for (i = 0; i < fill / 4; i++) {
- /* at first 32 bit access */
- ifxmips_w32(*(UINT32 *)info->txbuf_ptr, IFXMIPS_SSC_TB);
- info->txbuf_ptr += 4;
- }
-
- fifo_space -= fill / 4;
- info->stats.txBytes += fill & ~0x3;
- fill &= 0x3;
- if ((fifo_space > 0) & (fill > 1)) {
- /* trailing 16 bit access */
- WRITE_PERIPHERAL_REGISTER_16(*(UINT16 *)info->txbuf_ptr, info->mapbase + IFX_SSC_TB);
- info->txbuf_ptr += 2;
- info->stats.txBytes += 2;
- fifo_space--;
- fill -= 2;
- }
-
- if ((fifo_space > 0) & (fill > 0)) {
- /* trailing 8 bit access */
- WRITE_PERIPHERAL_REGISTER_8(*(UINT8 *)info->txbuf_ptr, info->mapbase + IFX_SSC_TB);
- info->txbuf_ptr++;
- info->stats.txBytes++;
- }
-
- /* check if transmission complete */
- if (info->txbuf_ptr >= info->txbuf_end) {
- disable_irq(IFXMIPS_SSC_TIR);
- kfree(info->txbuf);
- info->txbuf = NULL;
- }
-
-}
-
-irqreturn_t ifx_ssc_rx_int(int irq, void *dev_id)
-{
- struct ifx_ssc_port *info = (struct ifx_ssc_port *)dev_id;
- rx_int(info);
-
- return IRQ_HANDLED;
-}
-
-irqreturn_t ifx_ssc_tx_int(int irq, void *dev_id)
-{
- struct ifx_ssc_port *info = (struct ifx_ssc_port *)dev_id;
- tx_int(info);
-
- return IRQ_HANDLED;
-}
-
-irqreturn_t ifx_ssc_err_int(int irq, void *dev_id)
-{
- struct ifx_ssc_port *info = (struct ifx_ssc_port *)dev_id;
- unsigned int state;
- unsigned int write_back = 0;
- unsigned long flags;
-
- local_irq_save(flags);
- state = ifxmips_r32(IFXMIPS_SSC_STATE);
-
- if ((state & IFX_SSC_STATE_RX_UFL) != 0) {
- info->stats.rxUnErr++;
- write_back |= IFX_SSC_WHBSTATE_CLR_RX_UFL_ERROR;
- }
-
- if ((state & IFX_SSC_STATE_RX_OFL) != 0) {
- info->stats.rxOvErr++;
- write_back |= IFX_SSC_WHBSTATE_CLR_RX_OFL_ERROR;
- }
-
- if ((state & IFX_SSC_STATE_TX_OFL) != 0) {
- info->stats.txOvErr++;
- write_back |= IFX_SSC_WHBSTATE_CLR_TX_OFL_ERROR;
- }
-
- if ((state & IFX_SSC_STATE_TX_UFL) != 0) {
- info->stats.txUnErr++;
- write_back |= IFX_SSC_WHBSTATE_CLR_TX_UFL_ERROR;
- }
-
- if ((state & IFX_SSC_STATE_MODE_ERR) != 0) {
- info->stats.modeErr++;
- write_back |= IFX_SSC_WHBSTATE_CLR_MODE_ERROR;
- }
-
- if (write_back)
- ifxmips_w32(write_back, IFXMIPS_SSC_WHBSTATE);
-
- local_irq_restore(flags);
-
- return IRQ_HANDLED;
-}
-
-static void ifx_ssc_abort(struct ifx_ssc_port *info)
-{
- unsigned long flags;
- bool enabled;
-
- local_irq_save(flags);
-
- disable_irq(IFXMIPS_SSC_RIR);
- disable_irq(IFXMIPS_SSC_TIR);
- disable_irq(IFXMIPS_SSC_EIR);
-
- local_irq_restore(flags);
-
- /* disable SSC(also aborts a receive request!) */
- /* ### TO DO: Perhaps it's better to abort after the receiption of a
- complete word. The disable cuts the transmission immediatly and
- releases the chip selects. This could result in unpredictable
- behavior of connected external devices!
- */
- enabled = (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED) != 0;
- ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
-
- /* flush fifos */
- ifxmips_w32(IFX_SSC_XFCON_FIFO_FLUSH, IFXMIPS_SSC_TXFCON);
- ifxmips_w32(IFX_SSC_XFCON_FIFO_FLUSH, IFXMIPS_SSC_RXFCON);
-
- /* free txbuf */
- if (info->txbuf != NULL) {
- kfree(info->txbuf);
- info->txbuf = NULL;
- }
-
- /* wakeup read process */
- if (info->rxbuf != NULL)
- wake_up_interruptible(&info->rwait);
-
- /* clear pending int's */
- ifxmips_mask_and_ack_irq(IFXMIPS_SSC_RIR);
- ifxmips_mask_and_ack_irq(IFXMIPS_SSC_TIR);
- ifxmips_mask_and_ack_irq(IFXMIPS_SSC_EIR);
-
- /* clear error flags */
- ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE);
-
- if (enabled)
- ifxmips_w32(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
-
-}
-
-/*
- * This routine is called whenever a port is opened. It enforces
- * exclusive opening of a port and enables interrupts, etc.
- */
-int ifx_ssc_open(struct inode *inode, struct file *filp)
-{
- struct ifx_ssc_port *info;
- int line;
- int from_kernel = 0;
-
- if ((inode == (struct inode *)0) || (inode == (struct inode *)1)) {
- from_kernel = 1;
- line = (int) inode;
- } else
- line = MINOR(filp->f_dentry->d_inode->i_rdev);
-
- /* don't open more minor devices than we can support */
- if (line < 0 || line >= PORT_CNT)
- return -ENXIO;
-
- info = &isp[line];
-
- /* exclusive open */
- if (info->port_is_open != 0)
- return -EBUSY;
- info->port_is_open++;
-
- disable_irq(IFXMIPS_SSC_RIR);
- disable_irq(IFXMIPS_SSC_TIR);
- disable_irq(IFXMIPS_SSC_EIR);
-
- /* Flush and enable TX/RX FIFO */
- ifxmips_w32((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_TXFCON);
- ifxmips_w32((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_RXFCON);
-
- /* logically flush the software FIFOs */
- info->rxbuf_ptr = 0;
- info->txbuf_ptr = 0;
-
- /* clear all error bits */
- ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE);
-
- /* clear pending interrupts */
- ifxmips_mask_and_ack_irq(IFXMIPS_SSC_RIR);
- ifxmips_mask_and_ack_irq(IFXMIPS_SSC_TIR);
- ifxmips_mask_and_ack_irq(IFXMIPS_SSC_EIR);
-
- ifxmips_w32(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
-
- return 0;
-}
-EXPORT_SYMBOL(ifx_ssc_open);
-
-int ifx_ssc_close(struct inode *inode, struct file *filp)
-{
- struct ifx_ssc_port *info;
- int idx;
-
- if ((inode == (struct inode *)0) || (inode == (struct inode *)1))
- idx = (int) inode;
- else
- idx = MINOR(filp->f_dentry->d_inode->i_rdev);
-
- if (idx < 0 || idx >= PORT_CNT)
- return -ENXIO;
-
- info = &isp[idx];
- if (!info)
- return -ENXIO;
-
- ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
-
- ifx_ssc_abort(info);
-
- info->port_is_open--;
-
- return 0;
-}
-EXPORT_SYMBOL(ifx_ssc_close);
-
-static ssize_t ifx_ssc_read_helper_poll(struct ifx_ssc_port *info, char *buf,
- size_t len, int from_kernel)
-{
- ssize_t ret_val;
- unsigned long flags;
-
- if (info->opts.modeRxTx == IFX_SSC_MODE_TX)
- return -EFAULT;
- local_irq_save(flags);
- info->rxbuf_ptr = info->rxbuf;
- info->rxbuf_end = info->rxbuf + len;
- local_irq_restore(flags);
- /* Vinetic driver always works in IFX_SSC_MODE_RXTX */
- /* TXRX in poll mode */
- while (info->rxbuf_ptr < info->rxbuf_end) {
- if (info->txbuf_ptr < info->txbuf_end)
- tx_int(info);
-
- rx_int(info);
- };
-
- ret_val = info->rxbuf_ptr - info->rxbuf;
-
- return ret_val;
-}
-
-static ssize_t ifx_ssc_read_helper(struct ifx_ssc_port *info, char *buf,
- size_t len, int from_kernel)
-{
- ssize_t ret_val;
- unsigned long flags;
- DECLARE_WAITQUEUE(wait, current);
-
- if (info->opts.modeRxTx == IFX_SSC_MODE_TX)
- return -EFAULT;
-
- local_irq_save(flags);
- info->rxbuf_ptr = info->rxbuf;
- info->rxbuf_end = info->rxbuf + len;
-
- if (info->opts.modeRxTx == IFX_SSC_MODE_RXTX) {
- if ((info->txbuf == NULL) || (info->txbuf != info->txbuf_ptr) || (info->txbuf_end != len + info->txbuf)) {
- local_irq_restore(flags);
- printk("IFX SSC - %s: write must be called before calling " "read in combined RX/TX!\n", __func__);
- return -EFAULT;
- }
-
- local_irq_restore(flags);
- tx_int(info);
-
- if (info->txbuf_ptr < info->txbuf_end)
- enable_irq(IFXMIPS_SSC_TIR);
-
- enable_irq(IFXMIPS_SSC_RIR);
- } else {
- local_irq_restore(flags);
- if (ifxmips_r32(IFXMIPS_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK)
- return -EBUSY;
- enable_irq(IFXMIPS_SSC_RIR);
- if (len < IFX_SSC_RXREQ_BLOCK_SIZE)
- ifxmips_w32(len << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
- else
- ifxmips_w32(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
- }
-
- __add_wait_queue(&info->rwait, &wait);
- set_current_state(TASK_INTERRUPTIBLE);
-
- do {
- local_irq_save(flags);
- if (info->rxbuf_ptr >= info->rxbuf_end)
- break;
-
- local_irq_restore(flags);
-
- if (signal_pending(current)) {
- ret_val = -ERESTARTSYS;
- goto out;
- }
- schedule();
- } while (1);
-
- ret_val = info->rxbuf_ptr - info->rxbuf;
- local_irq_restore(flags);
-
-out:
- current->state = TASK_RUNNING;
- __remove_wait_queue(&info->rwait, &wait);
-
- return ret_val;
-}
-
-static ssize_t ifx_ssc_write_helper(struct ifx_ssc_port *info, const char *buf,
- size_t len, int from_kernel)
-{
- if (info->opts.modeRxTx == IFX_SSC_MODE_RX)
- return -EFAULT;
-
- info->txbuf_ptr = info->txbuf;
- info->txbuf_end = len + info->txbuf;
- if (info->opts.modeRxTx == IFX_SSC_MODE_TX) {
- tx_int(info);
- if (info->txbuf_ptr < info->txbuf_end)
- enable_irq(IFXMIPS_SSC_TIR);
- }
-
- return len;
-}
-
-ssize_t ifx_ssc_kread(int port, char *kbuf, size_t len)
-{
- struct ifx_ssc_port *info;
- ssize_t ret_val;
-
- if (port < 0 || port >= PORT_CNT)
- return -ENXIO;
-
- if (len == 0)
- return 0;
-
- info = &isp[port];
-
- if (info->rxbuf != NULL) {
- printk("SSC device busy\n");
- return -EBUSY;
- }
-
- info->rxbuf = kbuf;
- if (info->rxbuf == NULL) {
- printk("SSC device error\n");
- return -EINVAL;
- }
-
- ret_val = ifx_ssc_read_helper_poll(info, kbuf, len, 1);
- info->rxbuf = NULL;
-
- disable_irq(IFXMIPS_SSC_RIR);
-
- return ret_val;
-}
-EXPORT_SYMBOL(ifx_ssc_kread);
-
-ssize_t ifx_ssc_kwrite(int port, const char *kbuf, size_t len)
-{
- struct ifx_ssc_port *info;
- ssize_t ret_val;
-
- if (port < 0 || port >= PORT_CNT)
- return -ENXIO;
-
- if (len == 0)
- return 0;
-
- info = &isp[port];
-
- /* check if transmission in progress */
- if (info->txbuf != NULL)
- return -EBUSY;
-
- info->txbuf = (char *)kbuf;
-
- ret_val = ifx_ssc_write_helper(info, info->txbuf, len, 1);
-
- if (ret_val < 0)
- info->txbuf = NULL;
-
- return ret_val;
-}
-EXPORT_SYMBOL(ifx_ssc_kwrite);
-
-static ssize_t ifx_ssc_read(struct file *filp, char *ubuf, size_t len, loff_t *off)
-{
- ssize_t ret_val;
- int idx;
- struct ifx_ssc_port *info;
-
- idx = MINOR(filp->f_dentry->d_inode->i_rdev);
- info = &isp[idx];
-
- if (info->rxbuf != NULL)
- return -EBUSY;
-
- info->rxbuf = kmalloc(len + 3, GFP_KERNEL);
- if (info->rxbuf == NULL)
- return -ENOMEM;
-
- ret_val = ifx_ssc_read_helper(info, info->rxbuf, len, 0);
- if (copy_to_user((void *)ubuf, info->rxbuf, ret_val) != 0)
- ret_val = -EFAULT;
-
- disable_irq(IFXMIPS_SSC_RIR);
-
- kfree(info->rxbuf);
- info->rxbuf = NULL;
-
- return ret_val;
-}
-
-static ssize_t ifx_ssc_write(struct file *filp, const char *ubuf, size_t len, loff_t *off)
-{
- int idx;
- struct ifx_ssc_port *info;
- int ret_val;
-
- if (len == 0)
- return 0;
-
- idx = MINOR(filp->f_dentry->d_inode->i_rdev);
- info = &isp[idx];
-
- if (info->txbuf != NULL)
- return -EBUSY;
-
- info->txbuf = kmalloc(len + 3, GFP_KERNEL);
- if (info->txbuf == NULL)
- return -ENOMEM;
-
- ret_val = copy_from_user(info->txbuf, ubuf, len);
- if (ret_val == 0)
- ret_val = ifx_ssc_write_helper(info, info->txbuf, len, 0);
- else
- ret_val = -EFAULT;
-
- if (ret_val < 0) {
- kfree(info->txbuf);
- info->txbuf = NULL;
- }
-
- return ret_val;
-}
-
-static struct ifx_ssc_frm_status *ifx_ssc_frm_status_get(struct ifx_ssc_port *info)
-{
- unsigned long tmp;
-
- tmp = ifxmips_r32(IFXMIPS_SSC_SFSTAT);
- info->frm_status.DataBusy = (tmp & IFX_SSC_SFSTAT_IN_DATA) > 0;
- info->frm_status.PauseBusy = (tmp & IFX_SSC_SFSTAT_IN_PAUSE) > 0;
- info->frm_status.DataCount = (tmp & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET;
- info->frm_status.PauseCount = (tmp & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET;
- tmp = ifxmips_r32(IFXMIPS_SSC_SFCON);
- info->frm_status.EnIntAfterData = (tmp & IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE) > 0;
- info->frm_status.EnIntAfterPause = (tmp & IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE) > 0;
-
- return &info->frm_status;
-}
-
-static struct ifx_ssc_frm_opts *ifx_ssc_frm_control_get(struct ifx_ssc_port *info)
-{
- unsigned long tmp;
-
- tmp = ifxmips_r32(IFXMIPS_SSC_SFCON);
- info->frm_opts.FrameEnable = (tmp & IFX_SSC_SFCON_SF_ENABLE) > 0;
- info->frm_opts.DataLength = (tmp & IFX_SSC_SFCON_DATA_LENGTH_MASK) >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET;
- info->frm_opts.PauseLength = (tmp & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET;
- info->frm_opts.IdleData = (tmp & IFX_SSC_SFCON_PAUSE_DATA_MASK) >> IFX_SSC_SFCON_PAUSE_DATA_OFFSET;
- info->frm_opts.IdleClock = (tmp & IFX_SSC_SFCON_PAUSE_CLOCK_MASK) >> IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET;
- info->frm_opts.StopAfterPause = (tmp & IFX_SSC_SFCON_STOP_AFTER_PAUSE) > 0;
-
- return &info->frm_opts;
-}
-
-static int ifx_ssc_frm_control_set(struct ifx_ssc_port *info)
-{
- unsigned long tmp;
-
- if ((info->frm_opts.DataLength > IFX_SSC_SFCON_DATA_LENGTH_MAX)
- || (info->frm_opts.DataLength < 1)
- || (info->frm_opts.PauseLength > IFX_SSC_SFCON_PAUSE_LENGTH_MAX)
- || (info->frm_opts.PauseLength < 1)
- || (info->frm_opts.IdleData & ~(IFX_SSC_SFCON_PAUSE_DATA_MASK >> IFX_SSC_SFCON_PAUSE_DATA_OFFSET))
- || (info->frm_opts.IdleClock & ~(IFX_SSC_SFCON_PAUSE_CLOCK_MASK >> IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET)))
- return -EINVAL;
-
- /* read interrupt bits(they're not changed here) */
- tmp = ifxmips_r32(IFXMIPS_SSC_SFCON) &
- (IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE | IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE);
-
- /* set all values with respect to it's bit position(for data and pause
- length set N-1) */
- tmp = (info->frm_opts.DataLength - 1) << IFX_SSC_SFCON_DATA_LENGTH_OFFSET;
- tmp |= (info->frm_opts.PauseLength - 1) << IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET;
- tmp |= info->frm_opts.IdleData << IFX_SSC_SFCON_PAUSE_DATA_OFFSET;
- tmp |= info->frm_opts.IdleClock << IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET;
- tmp |= info->frm_opts.FrameEnable * IFX_SSC_SFCON_SF_ENABLE;
- tmp |= info->frm_opts.StopAfterPause * IFX_SSC_SFCON_STOP_AFTER_PAUSE;
-
- ifxmips_w32(tmp, IFXMIPS_SSC_SFCON);
-
- return 0;
-}
-
-static int ifx_ssc_rxtx_mode_set(struct ifx_ssc_port *info, unsigned int val)
-{
- unsigned long tmp;
-
- if (!(info) || (val & ~(IFX_SSC_MODE_MASK)))
- return -EINVAL;
-
- if ((ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_BUSY)
- || (ifxmips_r32(IFXMIPS_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK))
- return -EBUSY;
-
- tmp = (ifxmips_r32(IFXMIPS_SSC_CON) & ~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF)) | (val);
- ifxmips_w32(tmp, IFXMIPS_SSC_SFCON);
- info->opts.modeRxTx = val;
-
- return 0;
-}
-
-static int ifx_ssc_sethwopts(struct ifx_ssc_port *info)
-{
- unsigned long flags, bits;
- struct ifx_ssc_hwopts *opts = &info->opts;
-
- if ((opts->dataWidth < IFX_SSC_MIN_DATA_WIDTH)
- || (opts->dataWidth > IFX_SSC_MAX_DATA_WIDTH))
- return -EINVAL;
-
- bits = (opts->dataWidth - 1) << IFX_SSC_CON_DATA_WIDTH_OFFSET;
- bits |= IFX_SSC_CON_ENABLE_BYTE_VALID;
-
- if (opts->rxOvErrDetect)
- bits |= IFX_SSC_CON_RX_OFL_CHECK;
- if (opts->rxUndErrDetect)
- bits |= IFX_SSC_CON_RX_UFL_CHECK;
- if (opts->txOvErrDetect)
- bits |= IFX_SSC_CON_TX_OFL_CHECK;
- if (opts->txUndErrDetect)
- bits |= IFX_SSC_CON_TX_UFL_CHECK;
- if (opts->loopBack)
- bits |= IFX_SSC_CON_LOOPBACK_MODE;
- if (opts->echoMode)
- bits |= IFX_SSC_CON_ECHO_MODE_ON;
- if (opts->headingControl)
- bits |= IFX_SSC_CON_MSB_FIRST;
- if (opts->clockPhase)
- bits |= IFX_SSC_CON_LATCH_THEN_SHIFT;
- if (opts->clockPolarity)
- bits |= IFX_SSC_CON_CLOCK_FALL;
-
- switch (opts->modeRxTx) {
- case IFX_SSC_MODE_TX:
- bits |= IFX_SSC_CON_RX_OFF;
- break;
- case IFX_SSC_MODE_RX:
- bits |= IFX_SSC_CON_TX_OFF;
- break;
- }
-
- local_irq_save(flags);
-
- ifxmips_w32(bits, IFXMIPS_SSC_CON);
- ifxmips_w32((info->opts.gpoCs << IFX_SSC_GPOCON_ISCSB0_POS) |
- (info->opts.gpoInv << IFX_SSC_GPOCON_INVOUT0_POS), IFXMIPS_SSC_GPOCON);
-
- ifxmips_w32(info->opts.gpoCs << IFX_SSC_WHBGPOSTAT_SETOUT0_POS, IFXMIPS_SSC_WHBGPOSTAT);
-
- /* master mode */
- if (opts->masterSelect)
- ifxmips_w32(IFX_SSC_WHBSTATE_SET_MASTER_SELECT, IFXMIPS_SSC_WHBSTATE);
- else
- ifxmips_w32(IFX_SSC_WHBSTATE_CLR_MASTER_SELECT, IFXMIPS_SSC_WHBSTATE);
-
- /* init serial framing */
- ifxmips_w32(0, IFXMIPS_SSC_SFCON);
- /* set up the port pins */
- /* check for general requirements to switch(external) pad/pin characteristics */
- /* TODO: P0.9 SPI_CS4, P0.10 SPI_CS5, P 0.11 SPI_CS6, because of ASC0 */
- /* p0.15 SPI_CS1(EEPROM), P0.13 SPI_CS3, */
- /* Set p0.15 to alternative 01, others to 00(In/OUT) */
- *(IFXMIPS_GPIO_P0_DIR) = (*IFXMIPS_GPIO_P0_DIR) | (0xA000);
- *(IFXMIPS_GPIO_P0_ALTSEL0) = (((*IFXMIPS_GPIO_P0_ALTSEL0) | (0x8000)) & (~(0x2000)));
- *(IFXMIPS_GPIO_P0_ALTSEL1) = (((*IFXMIPS_GPIO_P0_ALTSEL1) & (~0x8000)) & (~(0x2000)));
- *(IFXMIPS_GPIO_P0_OD) = (*IFXMIPS_GPIO_P0_OD) | 0xA000;
-
- /* p1.6 SPI_CS2(SFLASH), p1.0 SPI_DIN, p1.1 SPI_DOUT, p1.2 SPI_CLK */
- *(IFXMIPS_GPIO_P1_DIR) = ((*IFXMIPS_GPIO_P1_DIR) | (0x46)) & (~1);
- *(IFXMIPS_GPIO_P1_ALTSEL0) = ((*IFXMIPS_GPIO_P1_ALTSEL0) | (0x47));
- *(IFXMIPS_GPIO_P1_ALTSEL1) = (*IFXMIPS_GPIO_P1_ALTSEL1) & (~0x47);
- *(IFXMIPS_GPIO_P1_OD) = (*IFXMIPS_GPIO_P1_OD) | 0x0046;
-
- /*CS3 */
- /*TODO: CS4 CS5 CS6 */
- *IFXMIPS_GPIO_P0_OUT = ((*IFXMIPS_GPIO_P0_OUT) | 0x2000);
-
- local_irq_restore(flags);
-
- return 0;
-}
-
-static int ifx_ssc_set_baud(struct ifx_ssc_port *info, unsigned int baud)
-{
- unsigned int ifx_ssc_clock;
- unsigned int br;
- unsigned long flags;
- bool enabled;
- int retval = 0;
-
- ifx_ssc_clock = ifx_ssc_get_kernel_clk(info);
- if (ifx_ssc_clock == 0) {
- retval = -EINVAL;
- goto out;
- }
-
- local_irq_save(flags);
-
- enabled = (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
- ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
-
- br = (((ifx_ssc_clock >> 1) + baud / 2) / baud) - 1;
- wmb();
-
- if (br > 0xffff || ((br == 0) &&
- ((ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_MASTER) == 0))) {
- local_irq_restore(flags);
- printk("%s: invalid baudrate %u\n", __func__, baud);
- return -EINVAL;
- }
-
- ifxmips_w32(br, IFXMIPS_SSC_BR);
-
- if (enabled)
- ifxmips_w32(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
-
- local_irq_restore(flags);
-
-out:
- return retval;
-}
-
-static int ifx_ssc_hwinit(struct ifx_ssc_port *info)
-{
- unsigned long flags;
- bool enabled;
-
- enabled = (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
- ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
-
- if (ifx_ssc_sethwopts(info) < 0) {
- printk("%s: setting the hardware options failed\n", __func__);
- return -EINVAL;
- }
-
- if (ifx_ssc_set_baud(info, info->baud) < 0) {
- printk("%s: setting the baud rate failed\n", __func__);
- return -EINVAL;
- }
-
- local_irq_save(flags);
-
- /* TX FIFO */
- ifxmips_w32((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_TXFCON);
- /* RX FIFO */
- ifxmips_w32((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_RXFCON);
-
- local_irq_restore(flags);
-
- if (enabled)
- ifxmips_w32(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
-
- return 0;
-}
-
-int ifx_ssc_ioctl(struct inode *inode, struct file *filp,
- unsigned int cmd, unsigned long data)
-{
- struct ifx_ssc_port *info;
- int line, ret_val = 0;
- unsigned long flags;
- unsigned long tmp;
- int from_kernel = 0;
-
- if ((inode == (struct inode *)0) || (inode == (struct inode *)1)) {
- from_kernel = 1;
- line = (int) inode;
- } else
- line = MINOR(filp->f_dentry->d_inode->i_rdev);
-
- if (line < 0 || line >= PORT_CNT)
- return -ENXIO;
-
- info = &isp[line];
-
- switch (cmd) {
- case IFX_SSC_STATS_READ:
- /* data must be a pointer to a struct ifx_ssc_statistics */
- if (from_kernel)
- memcpy((void *)data, (void *)&info->stats,
- sizeof(struct ifx_ssc_statistics));
- else if (copy_to_user((void *)data,
- (void *)&info->stats,
- sizeof(struct ifx_ssc_statistics)))
- ret_val = -EFAULT;
- break;
- case IFX_SSC_STATS_RESET:
- /* just resets the statistics counters */
- memset((void *)&info->stats, 0,
- sizeof(struct ifx_ssc_statistics));
- break;
- case IFX_SSC_BAUD_SET:
- /* if the buffers are not empty then the port is */
- /* busy and we shouldn't change things on-the-fly! */
- if (!info->txbuf || !info->rxbuf ||
- (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_BUSY)) {
- ret_val = -EBUSY;
- break;
- }
- /* misuse flags */
- if (from_kernel)
- flags = *((unsigned long *)data);
- else if (copy_from_user((void *)&flags,
- (void *)data, sizeof(flags))) {
- ret_val = -EFAULT;
- break;
- }
- if (flags == 0) {
- ret_val = -EINVAL;
- break;
- }
- if (ifx_ssc_set_baud(info, flags) < 0) {
- ret_val = -EINVAL;
- break;
- }
- info->baud = flags;
- break;
- case IFX_SSC_BAUD_GET:
- if (from_kernel)
- *((unsigned int *)data) = info->baud;
- else if (copy_to_user((void *)data,
- (void *)&info->baud,
- sizeof(unsigned long)))
- ret_val = -EFAULT;
- break;
- case IFX_SSC_RXTX_MODE_SET:
- if (from_kernel)
- tmp = *((unsigned long *)data);
- else if (copy_from_user((void *)&tmp,
- (void *)data, sizeof(tmp))) {
- ret_val = -EFAULT;
- break;
- }
- ret_val = ifx_ssc_rxtx_mode_set(info, tmp);
- break;
- case IFX_SSC_RXTX_MODE_GET:
- tmp = ifxmips_r32(IFXMIPS_SSC_CON) &
- (~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF));
- if (from_kernel)
- *((unsigned int *)data) = tmp;
- else if (copy_to_user((void *)data,
- (void *)&tmp, sizeof(tmp)))
- ret_val = -EFAULT;
- break;
-
- case IFX_SSC_ABORT:
- ifx_ssc_abort(info);
- break;
-
- case IFX_SSC_GPO_OUT_SET:
- if (from_kernel)
- tmp = *((unsigned long *)data);
- else if (copy_from_user((void *)&tmp,
- (void *)data, sizeof(tmp))) {
- ret_val = -EFAULT;
- break;
- }
- if (tmp > IFX_SSC_MAX_GPO_OUT)
- ret_val = -EINVAL;
- else
- ifxmips_w32(1 << (tmp + IFX_SSC_WHBGPOSTAT_SETOUT0_POS),
- IFXMIPS_SSC_WHBGPOSTAT);
- break;
- case IFX_SSC_GPO_OUT_CLR:
- if (from_kernel)
- tmp = *((unsigned long *)data);
- else if (copy_from_user((void *)&tmp, (void *)data, sizeof(tmp))) {
- ret_val = -EFAULT;
- break;
- }
- if (tmp > IFX_SSC_MAX_GPO_OUT)
- ret_val = -EINVAL;
- else
- ifxmips_w32(1 << (tmp + IFX_SSC_WHBGPOSTAT_CLROUT0_POS),
- IFXMIPS_SSC_WHBGPOSTAT);
- break;
- case IFX_SSC_GPO_OUT_GET:
- tmp = ifxmips_r32(IFXMIPS_SSC_GPOSTAT);
- if (from_kernel)
- *((unsigned int *)data) = tmp;
- else if (copy_to_user((void *)data,
- (void *)&tmp, sizeof(tmp)))
- ret_val = -EFAULT;
- break;
- case IFX_SSC_FRM_STATUS_GET:
- ifx_ssc_frm_status_get(info);
- if (from_kernel)
- memcpy((void *)data, (void *)&info->frm_status,
- sizeof(struct ifx_ssc_frm_status));
- else if (copy_to_user((void *)data,
- (void *)&info->frm_status,
- sizeof(struct ifx_ssc_frm_status)))
- ret_val = -EFAULT;
- break;
- case IFX_SSC_FRM_CONTROL_GET:
- ifx_ssc_frm_control_get(info);
- if (from_kernel)
- memcpy((void *)data, (void *)&info->frm_opts,
- sizeof(struct ifx_ssc_frm_opts));
- else if (copy_to_user((void *)data,
- (void *)&info->frm_opts,
- sizeof(struct ifx_ssc_frm_opts)))
- ret_val = -EFAULT;
- break;
- case IFX_SSC_FRM_CONTROL_SET:
- if (from_kernel)
- memcpy((void *)&info->frm_opts, (void *)data,
- sizeof(struct ifx_ssc_frm_opts));
- else if (copy_to_user((void *)&info->frm_opts,
- (void *)data,
- sizeof(struct ifx_ssc_frm_opts))) {
- ret_val = -EFAULT;
- break;
- }
- ret_val = ifx_ssc_frm_control_set(info);
- break;
- case IFX_SSC_HWOPTS_SET:
- /* data must be a pointer to a struct ifx_ssc_hwopts */
- /* if the buffers are not empty then the port is */
- /* busy and we shouldn't change things on-the-fly! */
- if (!info->txbuf || !info->rxbuf ||
- (ifxmips_r32(IFXMIPS_SSC_STATE)
- & IFX_SSC_STATE_BUSY)) {
- ret_val = -EBUSY;
- break;
- }
- if (from_kernel)
- memcpy((void *)&info->opts, (void *)data,
- sizeof(struct ifx_ssc_hwopts));
- else if (copy_from_user((void *)&info->opts,
- (void *)data, sizeof(struct ifx_ssc_hwopts))) {
- ret_val = -EFAULT;
- break;
- }
- if (ifx_ssc_hwinit(info) < 0)
- ret_val = -EIO;
- break;
- case IFX_SSC_HWOPTS_GET:
- /* data must be a pointer to a struct ifx_ssc_hwopts */
- if (from_kernel)
- memcpy((void *)data, (void *)&info->opts,
- sizeof(struct ifx_ssc_hwopts));
- else if (copy_to_user((void *)data,
- (void *)&info->opts,
- sizeof(struct ifx_ssc_hwopts)))
- ret_val = -EFAULT;
- break;
- default:
- ret_val = -ENOIOCTLCMD;
- }
-
- return ret_val;
-}
-EXPORT_SYMBOL(ifx_ssc_ioctl);
-
-static struct file_operations ifx_ssc_fops = {
- .owner = THIS_MODULE,
- .read = ifx_ssc_read,
- .write = ifx_ssc_write,
- .ioctl = ifx_ssc_ioctl,
- .open = ifx_ssc_open,
- .release = ifx_ssc_close,
-};
-
-int __init ifx_ssc_init(void)
-{
- struct ifx_ssc_port *info;
- int i, nbytes;
- unsigned long flags;
- int ret_val;
-
- ret_val = -ENOMEM;
- nbytes = PORT_CNT * sizeof(struct ifx_ssc_port);
- isp = kmalloc(nbytes, GFP_KERNEL);
-
- if (isp == NULL) {
- printk("%s: no memory for isp\n", __func__);
- return ret_val;
- }
- memset(isp, 0, nbytes);
-
- ret_val = -ENXIO;
- i = register_chrdev(maj, "ssc", &ifx_ssc_fops);
- if (i < 0) {
- printk("Unable to register major %d for the Infineon SSC\n", maj);
- if (maj == 0) {
- goto errout;
- } else {
- maj = 0;
- i = register_chrdev(maj, "ssc", &ifx_ssc_fops);
- if (i < 0) {
- printk("Unable to register major %d for the Infineon SSC\n", maj);
- goto errout;
- }
- }
- }
-
- if (maj == 0)
- maj = i;
-
- /* set default values in ifx_ssc_port */
- for (i = 0; i < PORT_CNT; i++) {
- info = &isp[i];
- info->port_nr = i;
- /* default values for the HwOpts */
- info->opts.AbortErrDetect = IFX_SSC_DEF_ABRT_ERR_DETECT;
- info->opts.rxOvErrDetect = IFX_SSC_DEF_RO_ERR_DETECT;
- info->opts.rxUndErrDetect = IFX_SSC_DEF_RU_ERR_DETECT;
- info->opts.txOvErrDetect = IFX_SSC_DEF_TO_ERR_DETECT;
- info->opts.txUndErrDetect = IFX_SSC_DEF_TU_ERR_DETECT;
- info->opts.loopBack = IFX_SSC_DEF_LOOP_BACK;
- info->opts.echoMode = IFX_SSC_DEF_ECHO_MODE;
- info->opts.idleValue = IFX_SSC_DEF_IDLE_DATA;
- info->opts.clockPolarity = IFX_SSC_DEF_CLOCK_POLARITY;
- info->opts.clockPhase = IFX_SSC_DEF_CLOCK_PHASE;
- info->opts.headingControl = IFX_SSC_DEF_HEADING_CONTROL;
- info->opts.dataWidth = IFX_SSC_DEF_DATA_WIDTH;
- info->opts.modeRxTx = IFX_SSC_DEF_MODE_RXTX;
- info->opts.gpoCs = IFX_SSC_DEF_GPO_CS;
- info->opts.gpoInv = IFX_SSC_DEF_GPO_INV;
- info->opts.masterSelect = IFX_SSC_DEF_MASTERSLAVE;
- info->baud = IFX_SSC_DEF_BAUDRATE;
- info->rxbuf = NULL;
- info->txbuf = NULL;
- /* values specific to SSC1 */
- if (i == 0)
- info->mapbase = IFXMIPS_SSC_BASE_ADDR;
-
- ifxmips_w32(IFX_SSC_DEF_RMC << IFX_CLC_RUN_DIVIDER_OFFSET, IFXMIPS_SSC_CLC);
-
- init_waitqueue_head(&info->rwait);
-
- local_irq_save(flags);
-
- /* init serial framing register */
- ifxmips_w32(IFX_SSC_DEF_SFCON, IFXMIPS_SSC_SFCON);
-
- ret_val = request_irq(IFXMIPS_SSC_TIR, ifx_ssc_tx_int, IRQF_DISABLED, "ifx_ssc_tx", info);
- if (ret_val) {
- printk("%s: unable to get irq %d\n", __func__, IFXMIPS_SSC_TIR);
- local_irq_restore(flags);
- goto errout;
- }
-
- ret_val = request_irq(IFXMIPS_SSC_RIR, ifx_ssc_rx_int, IRQF_DISABLED, "ifx_ssc_rx", info);
- if (ret_val) {
- printk("%s: unable to get irq %d\n", __func__, IFXMIPS_SSC_RIR);
- local_irq_restore(flags);
- goto irqerr;
- }
-
- ret_val = request_irq(IFXMIPS_SSC_EIR, ifx_ssc_err_int, IRQF_DISABLED, "ifx_ssc_err", info);
- if (ret_val) {
- printk("%s: unable to get irq %d\n", __func__, IFXMIPS_SSC_EIR);
- local_irq_restore(flags);
- goto irqerr;
- }
- ifxmips_w32(IFX_SSC_DEF_IRNEN, IFXMIPS_SSC_IRN);
-
- #if 0
- enable_irq(IFXMIPS_SSC_TIR);
- enable_irq(IFXMIPS_SSC_RIR);
- enable_irq(IFXMIPS_SSC_EIR);
- #endif
-
- local_irq_restore(flags);
- }
-
- for (i = 0; i < PORT_CNT; i++) {
- info = &isp[i];
- if (ifx_ssc_hwinit(info) < 0) {
- printk("%s: hardware init failed for port %d\n", __func__, i);
- goto irqerr;
- }
- }
-
-
- return 0;
-
-irqerr:
- free_irq(IFXMIPS_SSC_TIR, &isp[0]);
- free_irq(IFXMIPS_SSC_RIR, &isp[0]);
- free_irq(IFXMIPS_SSC_EIR, &isp[0]);
-errout:
- kfree(isp);
- return ret_val;
-}
-
-void __exit ifx_ssc_cleanup_module(void)
-{
- int i;
-
- for (i = 0; i < PORT_CNT; i++) {
- ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
- free_irq(IFXMIPS_SSC_TIR, &isp[i]);
- free_irq(IFXMIPS_SSC_RIR, &isp[i]);
- free_irq(IFXMIPS_SSC_EIR, &isp[i]);
- }
- kfree(isp);
-}
-
-module_init(ifx_ssc_init);
-module_exit(ifx_ssc_cleanup_module);
-
-inline int ifx_ssc_cs_low(u32 pin)
-{
- int ret = 0;
- ret = ifx_ssc_ioctl((struct inode *)0, NULL, IFX_SSC_GPO_OUT_CLR, (unsigned long) &pin);
- if (ret)
- printk("clear CS %d fails\n", pin);
- wmb();
-
- return ret;
-}
-EXPORT_SYMBOL(ifx_ssc_cs_low);
-
-inline int ifx_ssc_cs_high(u32 pin)
-{
- int ret = 0;
- ret = ifx_ssc_ioctl((struct inode *)0, NULL, IFX_SSC_GPO_OUT_SET, (unsigned long) &pin);
- if (ret)
- printk("set CS %d fails\n", pin);
- wmb();
-
- return ret;
-}
-EXPORT_SYMBOL(ifx_ssc_cs_high);
-
-static int ssc_session(char *tx_buf, u32 tx_len, char *rx_buf, u32 rx_len)
-{
- int ret = 0;
-
- char *ssc_tx_buf = NULL;
- char *ssc_rx_buf = NULL;
- int eff_size = 0;
- u8 mode = 0;
-
- if (tx_buf == NULL && tx_len == 0 && rx_buf == NULL && rx_len == 0) {
- printk("invalid parameters\n");
- ret = -EINVAL;
- goto ssc_session_exit;
- } else if (tx_buf == NULL || tx_len == 0) {
- if (rx_buf != NULL && rx_len != 0) {
- mode = IFX_SSC_MODE_RX;
- } else {
- printk("invalid parameters\n");
- ret = -EINVAL;
- goto ssc_session_exit;
- }
- } else if (rx_buf == NULL || rx_len == 0) {
- if (tx_buf != NULL && tx_len != 0)
- mode = IFX_SSC_MODE_TX;
- else {
- printk("invalid parameters\n");
- ret = -EINVAL;
- goto ssc_session_exit;
- }
- } else
- mode = IFX_SSC_MODE_RXTX;
-
- if (mode == IFX_SSC_MODE_RXTX)
- eff_size = tx_len + rx_len;
- else if (mode == IFX_SSC_MODE_RX)
- eff_size = rx_len;
- else
- eff_size = tx_len;
-
- /* 4 bytes alignment, required by driver */
- ssc_tx_buf = kmalloc(sizeof(char) *
- ((eff_size + 3) & (~3)),
- GFP_ATOMIC);
- ssc_rx_buf = kmalloc(sizeof(char) *
- ((eff_size + 3) & (~3)),
- GFP_ATOMIC);
- if (ssc_tx_buf == NULL || ssc_rx_buf == NULL) {
- printk("no memory for size of %d\n", eff_size);
- ret = -ENOMEM;
- goto ssc_session_exit;
- }
- memset((void *)ssc_tx_buf, 0, eff_size);
- memset((void *)ssc_rx_buf, 0, eff_size);
-
- if (tx_len > 0)
- memcpy(ssc_tx_buf, tx_buf, tx_len);
-
- ret = ifx_ssc_kwrite(0, ssc_tx_buf, eff_size);
-
- if (ret > 0)
- ssc_tx_buf = NULL; /* should be freed by ifx_ssc_kwrite */
-
- if (ret != eff_size) {
- printk("ifx_ssc_write return %d\n", ret);
- goto ssc_session_exit;
- }
- ret = ifx_ssc_kread(0, ssc_rx_buf, eff_size);
- if (ret != eff_size) {
- printk("ifx_ssc_read return %d\n", ret);
- goto ssc_session_exit;
- }
-
- memcpy(rx_buf, ssc_rx_buf + tx_len, rx_len);
-
- if (mode == IFX_SSC_MODE_TX)
- ret = tx_len;
- else
- ret = rx_len;
-
-ssc_session_exit:
- if (ssc_tx_buf != NULL)
- kfree(ssc_tx_buf);
- if (ssc_rx_buf != NULL)
- kfree(ssc_rx_buf);
-
- if (ret < 0)
- printk("ssc session fails\n");
-
- return ret;
-}
-
-int ifx_ssc_txrx(char *tx_buf, u32 tx_len, char *rx_buf, u32 rx_len)
-{
- return ssc_session(tx_buf, tx_len, rx_buf, rx_len);
-}
-EXPORT_SYMBOL(ifx_ssc_txrx);
-
-int ifx_ssc_tx(char *tx_buf, u32 tx_len)
-{
- return ssc_session(tx_buf, tx_len, NULL, 0);
-}
-EXPORT_SYMBOL(ifx_ssc_tx);
-
-int ifx_ssc_rx(char *rx_buf, u32 rx_len)
-{
- return ssc_session(NULL, 0, rx_buf, rx_len);
-}
-EXPORT_SYMBOL(ifx_ssc_rx);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
-MODULE_DESCRIPTION("ifxmips ssc driver");
-
#define DRVNAME "ifxmips_led"
+/* might need to be changed depending on shift register used on the pcb */
#if 1
#define IFXMIPS_LED_CLK_EDGE IFXMIPS_LED_FALLING
#else
{
int i = 0;
- /* we need to setup pins SH,D,ST (4,5,6) */
+ /* leds are controlled via a shift register
+ we need to setup pins SH,D,ST (4,5,6) to make it work */
for (i = 4; i < 7; i++) {
ifxmips_port_set_altsel0(IFXMIPS_LED_GPIO_PORT, i);
ifxmips_port_clear_altsel1(IFXMIPS_LED_GPIO_PORT, i);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
-MODULE_DESCRIPTION("ethernet map driver for IFXMIPS boards");
+MODULE_DESCRIPTION("ethernet driver for IFXMIPS boards");
projects / openwrt / staging / lynxis.git / commitdiff