drm/amdgpu: remove all sh mem register modification in vm flush

Leave that at the values set during init.  No need to update
them repeatedly.

Signed-off-by: monk.liu <monk.liu@amd.com>
Signed-off-by: David Zhang <david1.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Jammy Zhou <jammy.zhou@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 7c816b5cf17a0be33dcd149a723558f36f0ea2b4..ef5e9f9b5ab278800a725d363000f1b5a436b438 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -829,8 +829,6 @@ static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
 {
        u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
                          SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
-       u32 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 
-                                      SH_MEM_ALIGNMENT_MODE_UNALIGNED);
 
        amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
        if (vm_id < 8) {
@@ -840,31 +838,6 @@ static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
        }
        amdgpu_ring_write(ring, pd_addr >> 12);
 
-       /* update SH_MEM_* regs */
-       amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
-       amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
-       amdgpu_ring_write(ring, VMID(vm_id));
-
-       amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
-       amdgpu_ring_write(ring, mmSH_MEM_BASES);
-       amdgpu_ring_write(ring, 0);
-
-       amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
-       amdgpu_ring_write(ring, mmSH_MEM_CONFIG);
-       amdgpu_ring_write(ring, sh_mem_cfg);
-
-       amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
-       amdgpu_ring_write(ring, mmSH_MEM_APE1_BASE);
-       amdgpu_ring_write(ring, 1);
-
-       amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
-       amdgpu_ring_write(ring, mmSH_MEM_APE1_LIMIT);
-       amdgpu_ring_write(ring, 0);
-
-       amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
-       amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
-       amdgpu_ring_write(ring, VMID(0));
-
        /* flush TLB */
        amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
        amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 0057699cb8fa3100622445304c03e3b9531e7435..58a20be93c14216df35f1064223f294f542cddfd 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -3593,33 +3593,6 @@ static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
        amdgpu_ring_write(ring, 0);
        amdgpu_ring_write(ring, pd_addr >> 12);
 
-       /* update SH_MEM_* regs */
-       amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-       amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-                                WRITE_DATA_DST_SEL(0)));
-       amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
-       amdgpu_ring_write(ring, 0);
-       amdgpu_ring_write(ring, VMID(vm_id));
-
-       amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6));
-       amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-                                WRITE_DATA_DST_SEL(0)));
-       amdgpu_ring_write(ring, mmSH_MEM_BASES);
-       amdgpu_ring_write(ring, 0);
-
-       amdgpu_ring_write(ring, 0); /* SH_MEM_BASES */
-       amdgpu_ring_write(ring, 0); /* SH_MEM_CONFIG */
-       amdgpu_ring_write(ring, 1); /* SH_MEM_APE1_BASE */
-       amdgpu_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */
-
-       amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-       amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-                                WRITE_DATA_DST_SEL(0)));
-       amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
-       amdgpu_ring_write(ring, 0);
-       amdgpu_ring_write(ring, VMID(0));
-
-
        /* bits 0-15 are the VM contexts0-15 */
        amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
        amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index a7d687da10d7692e2ebe504e36ac6e1b0298c7bb..c3aebdffeea18a4936a247955ec462120407d9f5 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -3800,7 +3800,6 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
                                        unsigned vm_id, uint64_t pd_addr)
 {
        int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
-       u32 srbm_gfx_cntl = 0;
 
        amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
        amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
@@ -3815,35 +3814,6 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
        amdgpu_ring_write(ring, 0);
        amdgpu_ring_write(ring, pd_addr >> 12);
 
-       /* update SH_MEM_* regs */
-       srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vm_id);
-       amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-       amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-                                WRITE_DATA_DST_SEL(0)));
-       amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
-       amdgpu_ring_write(ring, 0);
-       amdgpu_ring_write(ring, srbm_gfx_cntl);
-
-       amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6));
-       amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-                                WRITE_DATA_DST_SEL(0)));
-       amdgpu_ring_write(ring, mmSH_MEM_BASES);
-       amdgpu_ring_write(ring, 0);
-
-       amdgpu_ring_write(ring, 0); /* SH_MEM_BASES */
-       amdgpu_ring_write(ring, 0); /* SH_MEM_CONFIG */
-       amdgpu_ring_write(ring, 1); /* SH_MEM_APE1_BASE */
-       amdgpu_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */
-
-       srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, 0);
-       amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-       amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-                                WRITE_DATA_DST_SEL(0)));
-       amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
-       amdgpu_ring_write(ring, 0);
-       amdgpu_ring_write(ring, srbm_gfx_cntl);
-
-
        /* bits 0-15 are the VM contexts0-15 */
        /* invalidate the cache */
        amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 64de8f60e3a502a1e595710ad2b26a852a6668e6..d09aa7eeb40e5f8b872661cc013962b4a2ab1af6 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -890,10 +890,6 @@ static void sdma_v2_4_vm_pad_ib(struct amdgpu_ib *ib)
 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
                                         unsigned vm_id, uint64_t pd_addr)
 {
-       u32 srbm_gfx_cntl = 0;
-       u32 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 
-                                      SH_MEM_ALIGNMENT_MODE_UNALIGNED);
-
        amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
                          SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
        if (vm_id < 8) {
@@ -903,40 +899,6 @@ static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
        }
        amdgpu_ring_write(ring, pd_addr >> 12);
 
-       /* update SH_MEM_* regs */
-       srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vm_id);
-       amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-                         SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-       amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
-       amdgpu_ring_write(ring, srbm_gfx_cntl);
-
-       amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-                         SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-       amdgpu_ring_write(ring, mmSH_MEM_BASES);
-       amdgpu_ring_write(ring, 0);
-
-       amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-                         SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-       amdgpu_ring_write(ring, mmSH_MEM_CONFIG);
-       amdgpu_ring_write(ring, sh_mem_cfg);
-
-       amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-                         SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-       amdgpu_ring_write(ring, mmSH_MEM_APE1_BASE);
-       amdgpu_ring_write(ring, 1);
-
-       amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-                         SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-       amdgpu_ring_write(ring, mmSH_MEM_APE1_LIMIT);
-       amdgpu_ring_write(ring, 0);
-
-       srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, 0);
-       amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-                         SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-       amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
-       amdgpu_ring_write(ring, srbm_gfx_cntl);
-
-
        /* flush TLB */
        amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
                          SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index bf3cefc447ca192a6e167bbafc4f33694d010448..555c0e1e4c97dfa6b71d7034b673d919df7ed7ac 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -953,10 +953,6 @@ static void sdma_v3_0_vm_pad_ib(struct amdgpu_ib *ib)
 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
                                         unsigned vm_id, uint64_t pd_addr)
 {
-       u32 srbm_gfx_cntl = 0;
-       u32 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 
-                                      SH_MEM_ALIGNMENT_MODE_UNALIGNED);
-
        amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
                          SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
        if (vm_id < 8) {
@@ -966,40 +962,6 @@ static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
        }
        amdgpu_ring_write(ring, pd_addr >> 12);
 
-       /* update SH_MEM_* regs */
-       srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vm_id);
-       amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-                         SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-       amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
-       amdgpu_ring_write(ring, srbm_gfx_cntl);
-
-       amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-                         SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-       amdgpu_ring_write(ring, mmSH_MEM_BASES);
-       amdgpu_ring_write(ring, 0);
-
-       amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-                         SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-       amdgpu_ring_write(ring, mmSH_MEM_CONFIG);
-       amdgpu_ring_write(ring, sh_mem_cfg);
-
-       amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-                         SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-       amdgpu_ring_write(ring, mmSH_MEM_APE1_BASE);
-       amdgpu_ring_write(ring, 1);
-
-       amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-                         SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-       amdgpu_ring_write(ring, mmSH_MEM_APE1_LIMIT);
-       amdgpu_ring_write(ring, 0);
-
-       srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, 0);
-       amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
-                         SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-       amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
-       amdgpu_ring_write(ring, srbm_gfx_cntl);
-
-
        /* flush TLB */
        amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
                          SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));