drm/amd/pp: Unify powergate_uvd/vce/mmhub to set_powergating_by_smu

Some HW ip blocks need call SMU to enter/leave power gate state.
So export common set_powergating_by_smu interface.

1. keep consistent with set_clockgating_by_smu
2. scales easily to powergate other ip(gfx) if necessary

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index c6d6926256875c0033a3c5a836bfd39a810f7282..ff24e1cc5b65bd66e4657e833a97e1d18ae4d2b3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -287,12 +287,6 @@ enum amdgpu_pcie_gen {
 #define amdgpu_dpm_force_performance_level(adev, l) \
                ((adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)))
 
-#define amdgpu_dpm_powergate_uvd(adev, g) \
-               ((adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)))
-
-#define amdgpu_dpm_powergate_vce(adev, g) \
-               ((adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)))
-
 #define amdgpu_dpm_get_current_power_state(adev) \
                ((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle))
 
@@ -347,6 +341,10 @@ enum amdgpu_pcie_gen {
                ((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\
                        (adev)->powerplay.pp_handle, msg_id))
 
+#define amdgpu_dpm_set_powergating_by_smu(adev, block_type, gate) \
+               ((adev)->powerplay.pp_funcs->set_powergating_by_smu(\
+                       (adev)->powerplay.pp_handle, block_type, gate))
+
 #define amdgpu_dpm_get_power_profile_mode(adev, buf) \
                ((adev)->powerplay.pp_funcs->get_power_profile_mode(\
                        (adev)->powerplay.pp_handle, buf))
@@ -359,10 +357,6 @@ enum amdgpu_pcie_gen {
                ((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\
                        (adev)->powerplay.pp_handle, type, parameter, size))
 
-#define amdgpu_dpm_powergate_mmhub(adev) \
-               ((adev)->powerplay.pp_funcs->powergate_mmhub( \
-               (adev)->powerplay.pp_handle))
-
 struct amdgpu_dpm {
        struct amdgpu_ps        *ps;
        /* number of valid power states */

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index fdb39982191540cfe2b58110625dab0543674e72..a003fd881a89f20daf77474acfbb36240f615844 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1729,10 +1729,10 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
 
 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
 {
-       if (adev->powerplay.pp_funcs->powergate_uvd) {
+       if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
                /* enable/disable UVD */
                mutex_lock(&adev->pm.mutex);
-               amdgpu_dpm_powergate_uvd(adev, !enable);
+               amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
                mutex_unlock(&adev->pm.mutex);
        } else {
                if (enable) {
@@ -1751,10 +1751,10 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
 
 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
 {
-       if (adev->powerplay.pp_funcs->powergate_vce) {
+       if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
                /* enable/disable VCE */
                mutex_lock(&adev->pm.mutex);
-               amdgpu_dpm_powergate_vce(adev, !enable);
+               amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
                mutex_unlock(&adev->pm.mutex);
        } else {
                if (enable) {

diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index c9d45cffca567d8295615dce20066915aabcfb3f..7c4ff71e7476ede9e760d08992ee30547bda0842 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -6767,6 +6767,19 @@ static int ci_dpm_read_sensor(void *handle, int idx,
        }
 }
 
+static int ci_set_powergating_by_smu(void *handle,
+                               uint32_t block_type, bool gate)
+{
+       switch (block_type) {
+       case AMD_IP_BLOCK_TYPE_UVD:
+               ci_dpm_powergate_uvd(handle, gate);
+               break;
+       default:
+               break;
+       }
+       return 0;
+}
+
 static const struct amd_ip_funcs ci_dpm_ip_funcs = {
        .name = "ci_dpm",
        .early_init = ci_dpm_early_init,
@@ -6804,7 +6817,7 @@ static const struct amd_pm_funcs ci_dpm_funcs = {
        .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
        .force_performance_level = &ci_dpm_force_performance_level,
        .vblank_too_short = &ci_dpm_vblank_too_short,
-       .powergate_uvd = &ci_dpm_powergate_uvd,
+       .set_powergating_by_smu = &ci_set_powergating_by_smu,
        .set_fan_control_mode = &ci_dpm_set_fan_control_mode,
        .get_fan_control_mode = &ci_dpm_get_fan_control_mode,
        .set_fan_speed_percent = &ci_dpm_set_fan_speed_percent,

diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index 46de1fd18a7ba0b0be311cebfb5fc4592e3e31c4..3f57f6463dc880c797429d9f3080894b929e5eff 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -3306,6 +3306,19 @@ static int kv_dpm_read_sensor(void *handle, int idx,
        }
 }
 
+static int kv_set_powergating_by_smu(void *handle,
+                               uint32_t block_type, bool gate)
+{
+       switch (block_type) {
+       case AMD_IP_BLOCK_TYPE_UVD:
+               kv_dpm_powergate_uvd(handle, gate);
+               break;
+       default:
+               break;
+       }
+       return 0;
+}
+
 static const struct amd_ip_funcs kv_dpm_ip_funcs = {
        .name = "kv_dpm",
        .early_init = kv_dpm_early_init,
@@ -3342,7 +3355,7 @@ static const struct amd_pm_funcs kv_dpm_funcs = {
        .print_power_state = &kv_dpm_print_power_state,
        .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
        .force_performance_level = &kv_dpm_force_performance_level,
-       .powergate_uvd = &kv_dpm_powergate_uvd,
+       .set_powergating_by_smu = kv_set_powergating_by_smu,
        .enable_bapm = &kv_dpm_enable_bapm,
        .get_vce_clock_state = amdgpu_get_vce_clock_state,
        .check_state_equal = kv_check_state_equal,

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 377f5362a3dfc34636b49a7a734456ab02dec2c3..e70a0d4d6db4111a59239accef4d47d0d6676d72 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -471,8 +471,8 @@ void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
                                                RENG_EXECUTE_ON_REG_UPDATE, 1);
                WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);
 
-               if (adev->powerplay.pp_funcs->powergate_mmhub)
-                       amdgpu_dpm_powergate_mmhub(adev);
+               if (adev->powerplay.pp_funcs->set_powergating_by_smu)
+                       amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GMC, true);
 
        } else {
                pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,

diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 0f9886298a84eaaa1fe2ca96e7e330f2f13a2493..4535756428f987ca38eee77e401b7a283424d649 100644 (file)
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -232,13 +232,13 @@ struct amd_pm_funcs {
        void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
        int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
 /* export to amdgpu */
-       void (*powergate_uvd)(void *handle, bool gate);
-       void (*powergate_vce)(void *handle, bool gate);
        struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
        int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
                        enum amd_pm_state_type *user_state);
        int (*load_firmware)(void *handle);
        int (*wait_for_fw_loading_complete)(void *handle);
+       int (*set_powergating_by_smu)(void *handle,
+                               uint32_t block_type, bool gate);
        int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
        int (*set_power_limit)(void *handle, uint32_t n);
        int (*get_power_limit)(void *handle, uint32_t *limit, bool default_limit);
@@ -269,7 +269,6 @@ struct amd_pm_funcs {
        int (*get_power_profile_mode)(void *handle, char *buf);
        int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
        int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
-       int (*powergate_mmhub)(void *handle);
 };
 
 #endif

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index b69da116b30c76109647f2d387a95d9f90142351..f68551ffb1e27abf53d53b4624377dea65720720 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -244,6 +244,7 @@ static int pp_set_powergating_state(void *handle,
        /* Enable/disable GFX per cu powergating through SMU */
        return hwmgr->hwmgr_func->powergate_gfx(hwmgr,
                        state == AMD_PG_STATE_GATE);
+
 }
 
 static int pp_suspend(void *handle)
@@ -1183,14 +1184,36 @@ static int pp_dpm_powergate_mmhub(void *handle)
        return hwmgr->hwmgr_func->powergate_mmhub(hwmgr);
 }
 
+static int pp_set_powergating_by_smu(void *handle,
+                               uint32_t block_type, bool gate)
+{
+       int ret = 0;
+
+       switch (block_type) {
+       case AMD_IP_BLOCK_TYPE_UVD:
+       case AMD_IP_BLOCK_TYPE_VCN:
+               pp_dpm_powergate_uvd(handle, gate);
+               break;
+       case AMD_IP_BLOCK_TYPE_VCE:
+               pp_dpm_powergate_vce(handle, gate);
+               break;
+       case AMD_IP_BLOCK_TYPE_GMC:
+               pp_dpm_powergate_mmhub(handle);
+               break;
+       case AMD_IP_BLOCK_TYPE_GFX:
+               break;
+       default:
+               break;
+       }
+       return ret;
+}
+
 static const struct amd_pm_funcs pp_dpm_funcs = {
        .load_firmware = pp_dpm_load_fw,
        .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
        .force_performance_level = pp_dpm_force_performance_level,
        .get_performance_level = pp_dpm_get_performance_level,
        .get_current_power_state = pp_dpm_get_current_power_state,
-       .powergate_vce = pp_dpm_powergate_vce,
-       .powergate_uvd = pp_dpm_powergate_uvd,
        .dispatch_tasks = pp_dpm_dispatch_tasks,
        .set_fan_control_mode = pp_dpm_set_fan_control_mode,
        .get_fan_control_mode = pp_dpm_get_fan_control_mode,
@@ -1210,6 +1233,7 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
        .get_vce_clock_state = pp_dpm_get_vce_clock_state,
        .switch_power_profile = pp_dpm_switch_power_profile,
        .set_clockgating_by_smu = pp_set_clockgating_by_smu,
+       .set_powergating_by_smu = pp_set_powergating_by_smu,
        .get_power_profile_mode = pp_get_power_profile_mode,
        .set_power_profile_mode = pp_set_power_profile_mode,
        .odn_edit_dpm_table = pp_odn_edit_dpm_table,
@@ -1227,5 +1251,4 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
        .set_watermarks_for_clocks_ranges = pp_set_watermarks_for_clocks_ranges,
        .display_clock_voltage_request = pp_display_clock_voltage_request,
        .get_display_mode_validation_clocks = pp_get_display_mode_validation_clocks,
-       .powergate_mmhub = pp_dpm_powergate_mmhub,
 };