Define this option to use the Bank addr/Extended addr
support on SPI flashes which has size > 16Mbytes.
+ CONFIG_SF_DUAL_FLASH Dual flash memories
+
+ Define this option to use dual flash support where two flash
+ memories can be connected with a given cs line.
+ currently Xilinx Zynq qspi support these type of connections.
+
- SystemACE Support:
CONFIG_SYSTEMACE
}
#endif
+#ifdef CONFIG_SF_DUAL_FLASH
static void spi_flash_dual_flash(struct spi_flash *flash, u32 *addr)
{
switch (flash->dual_flash) {
break;
}
}
+#endif
int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
{
check_status = poll_bit;
}
+#ifdef CONFIG_SF_DUAL_FLASH
if (spi->flags & SPI_XFER_U_PAGE)
flags |= SPI_XFER_U_PAGE;
-
+#endif
ret = spi_xfer(spi, 8, &cmd, NULL, flags);
if (ret) {
debug("SF: fail to read %s status register\n",
while (len) {
erase_addr = offset;
+#ifdef CONFIG_SF_DUAL_FLASH
if (flash->dual_flash > SF_SINGLE_FLASH)
spi_flash_dual_flash(flash, &erase_addr);
-
+#endif
#ifdef CONFIG_SPI_FLASH_BAR
ret = spi_flash_bank(flash, erase_addr);
if (ret < 0)
for (actual = 0; actual < len; actual += chunk_len) {
write_addr = offset;
+#ifdef CONFIG_SF_DUAL_FLASH
if (flash->dual_flash > SF_SINGLE_FLASH)
spi_flash_dual_flash(flash, &write_addr);
-
+#endif
#ifdef CONFIG_SPI_FLASH_BAR
ret = spi_flash_bank(flash, write_addr);
if (ret < 0)
while (len) {
read_addr = offset;
+#ifdef CONFIG_SF_DUAL_FLASH
if (flash->dual_flash > SF_SINGLE_FLASH)
spi_flash_dual_flash(flash, &read_addr);
-
+#endif
#ifdef CONFIG_SPI_FLASH_BAR
bank_sel = spi_flash_bank(flash, read_addr);
if (bank_sel < 0)
flash->page_size = ((ext_jedec == 0x4d00) ? 512 : 256) << flash->shift;
flash->sector_size = params->sector_size << flash->shift;
flash->size = flash->sector_size * params->nr_sectors << flash->shift;
+#ifdef CONFIG_SF_DUAL_FLASH
if (flash->dual_flash & SF_DUAL_STACKED_FLASH)
flash->size <<= 1;
+#endif
/* Compute erase sector and command */
if (params->flags & SECT_4K) {