+++ /dev/null
-Replace udelay(3000) with mdelay(3), because udelay(3000) fails on ARM
-
-Signed-off-by: Felix Fietkau <nbd@openwrt.org>
-
---- a/drivers/net/wireless/ath9k/recv.c
-+++ b/drivers/net/wireless/ath9k/recv.c
-@@ -737,7 +737,7 @@
- ath9k_hw_stoppcurecv(ah); /* disable PCU */
- ath9k_hw_setrxfilter(ah, 0); /* clear recv filter */
- stopped = ath9k_hw_stopdmarecv(ah); /* disable DMA engine */
-- udelay(3000); /* 3ms is long enough for 1 frame */
-+ mdelay(3); /* 3ms is long enough for 1 frame */
- tsf = ath9k_hw_gettsf64(ah);
- sc->sc_rxlink = NULL; /* just in case */
- return stopped;
+++ /dev/null
-Add missing include statements
-
-Signed-off-by: Felix Fietkau <nbd@openwrt.org>
-
---- a/drivers/net/wireless/ath9k/regd.c
-+++ b/drivers/net/wireless/ath9k/regd.c
-@@ -14,6 +14,8 @@
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-+#include <linux/kernel.h>
-+#include <linux/slab.h>
- #include "ath9k.h"
- #include "regd.h"
- #include "regd_common.h"
+++ /dev/null
-Add missing device ID for AR9160
-
-Signed-off-by: Felix Fietkau <nbd@openwrt.org>
-
---- a/drivers/net/wireless/ath9k/hw.c
-+++ b/drivers/net/wireless/ath9k/hw.c
-@@ -8329,6 +8329,8 @@
- case AR5416_DEVID_PCI:
- case AR5416_DEVID_PCIE:
- return "Atheros 5416";
-+ case AR9160_DEVID_PCI:
-+ return "Atheros 9160";
- case AR9280_DEVID_PCI:
- case AR9280_DEVID_PCIE:
- return "Atheros 9280";
-@@ -8350,6 +8352,7 @@
- switch (devid) {
- case AR5416_DEVID_PCI:
- case AR5416_DEVID_PCIE:
-+ case AR9160_DEVID_PCI:
- case AR9280_DEVID_PCI:
- case AR9280_DEVID_PCIE:
- ah = ath9k_hw_do_attach(devid, sc, mem, error);
+++ /dev/null
-Fix a return code check for ath9k_hw_nvram_read, this function returns
-AH_TRUE when the call succeeded
-
-Signed-off-by: Felix Fietkau <nbd@openwrt.org>
-
---- a/drivers/net/wireless/ath9k/hw.c
-+++ b/drivers/net/wireless/ath9k/hw.c
-@@ -803,7 +803,7 @@
- u_int16_t magic, magic2;
- int addr;
-
-- if (ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
-+ if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
- &magic)) {
- HDPRINTF(ah, HAL_DBG_EEPROM,
- "%s: Reading Magic # failed\n", __func__);
+++ /dev/null
-Remove the descriptor swap, as the driver already configures the hardware for
-descriptor swapping on big endian systems
-
-Signed-off-by: Felix Fietkau <nbd@openwrt.org>
-
---- a/drivers/net/wireless/ath9k/core.c
-+++ b/drivers/net/wireless/ath9k/core.c
-@@ -2141,22 +2141,6 @@
- memzero(dd, sizeof(*dd));
- }
-
--/*
-- * Endian Swap for transmit descriptor
-- *
-- * XXX: Move cpu_to_le32() into hw.c and anywhere we set them, then
-- * remove this.
--*/
--void ath_desc_swap(struct ath_desc *ds)
--{
-- ds->ds_link = cpu_to_le32(ds->ds_link);
-- ds->ds_data = cpu_to_le32(ds->ds_data);
-- ds->ds_ctl0 = cpu_to_le32(ds->ds_ctl0);
-- ds->ds_ctl1 = cpu_to_le32(ds->ds_ctl1);
-- ds->ds_hw[0] = cpu_to_le32(ds->ds_hw[0]);
-- ds->ds_hw[1] = cpu_to_le32(ds->ds_hw[1]);
--}
--
- /*************/
- /* Utilities */
- /*************/
---- a/drivers/net/wireless/ath9k/beacon.c
-+++ b/drivers/net/wireless/ath9k/beacon.c
-@@ -140,11 +140,6 @@
- series[0].RateFlags = (ctsrate) ? HAL_RATESERIES_RTS_CTS : 0;
- ath9k_hw_set11n_ratescenario(ah, ds, ds, 0,
- ctsrate, ctsduration, series, 4, 0);
--
-- /* NB: The desc swap function becomes void,
-- * if descriptor swapping is not enabled
-- */
-- ath_desc_swap(ds);
- }
-
- /* Move everything from the vap's mcast queue to the hardware cab queue.
---- a/drivers/net/wireless/ath9k/core.h
-+++ b/drivers/net/wireless/ath9k/core.h
-@@ -384,7 +384,6 @@
- void ath_descdma_cleanup(struct ath_softc *sc,
- struct ath_descdma *dd,
- struct list_head *head);
--void ath_desc_swap(struct ath_desc *ds);
-
- /******/
- /* RX */
---- a/drivers/net/wireless/ath9k/xmit.c
-+++ b/drivers/net/wireless/ath9k/xmit.c
-@@ -2062,7 +2062,6 @@
- AH_TRUE, /* first segment */
- (n_sg == 1) ? AH_TRUE : AH_FALSE, /* last segment */
- ds); /* first descriptor */
-- ath_desc_swap(ds);
-
- bf->bf_lastfrm = bf;
- bf->bf_ht = txctl->ht;
+++ /dev/null
-This patch fixes another endianness issue.
-DMA descriptors must always be accessed in native endianness.
-
-Signed-off-by: Felix Fietkau <nbd@openwrt.org>
-
---- a/drivers/net/wireless/ath9k/xmit.c
-+++ b/drivers/net/wireless/ath9k/xmit.c
-@@ -168,7 +168,7 @@
- __func__, txq->axq_qnum,
- ito64(bf->bf_daddr), bf->bf_desc);
- } else {
-- *txq->axq_link = cpu_to_le32(bf->bf_daddr);
-+ *txq->axq_link = bf->bf_daddr;
- DPRINTF(sc, ATH_DEBUG_XMIT, "%s: link[%u] (%p)=%llx (%p)\n",
- __func__,
- txq->axq_qnum, txq->axq_link,
void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds);
void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah,
struct ath_desc *ds, u_int vmf);
-enum hal_bool ath9k_hw_SetTxPowerLimit(struct ath_hal *ah, u_int32_t limit,
- u_int16_t tpcInDb);
+enum hal_bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u_int32_t limit);
enum hal_bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah);
int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum hal_tx_queue type,
const struct hal_txq_info *qInfo);
series[0].RateFlags = (ctsrate) ? HAL_RATESERIES_RTS_CTS : 0;
ath9k_hw_set11n_ratescenario(ah, ds, ds, 0,
ctsrate, ctsduration, series, 4, 0);
-
- /* NB: The desc swap function becomes void,
- * if descriptor swapping is not enabled
- */
- ath_desc_swap(ds);
}
/* Move everything from the vap's mcast queue to the hardware cab queue.
if (!cabq->axq_link)
ath9k_hw_puttxbuf(ah, cabq->axq_qnum, bfmcast->bf_daddr);
else
- *cabq->axq_link = cpu_to_le32(bfmcast->bf_daddr);
+ *cabq->axq_link = bfmcast->bf_daddr;
/* append the private vap mcast list to the cabq */
if (if_id != ATH_IF_ID_ANY) {
bf = ath_beacon_generate(sc, if_id);
if (bf != NULL) {
- if (bflink != &bfaddr)
- *bflink = cpu_to_le32(
- bf->bf_daddr);
- else
- *bflink = bf->bf_daddr;
+ *bflink = bf->bf_daddr;
bflink = &bf->bf_desc->ds_link;
bc++;
}
* if we're switching; e.g. 11a to 11b/g.
*/
ath_chan_change(sc, hchan);
- ath_update_txpow(sc, 0); /* update tx power state */
+ ath_update_txpow(sc); /* update tx power state */
/*
* Re-enable interrupts.
*/
* This is needed only to setup initial state
* but it's best done after a reset.
*/
- ath_update_txpow(sc, 0);
+ ath_update_txpow(sc);
/*
* Setup the hardware after reset:
*/
ath_chan_change(sc, &sc->sc_curchan);
- ath_update_txpow(sc, 0); /* update tx power state */
+ ath_update_txpow(sc); /* update tx power state */
if (sc->sc_beacons)
ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
* Set Transmit power in HAL
*
* This routine makes the actual HAL calls to set the new transmit power
- * limit. This also calls back into the protocol layer setting the max
- * transmit power limit.
+ * limit.
*/
-void ath_update_txpow(struct ath_softc *sc, u_int16_t tpcInDb)
+void ath_update_txpow(struct ath_softc *sc)
{
struct ath_hal *ah = sc->sc_ah;
- u_int32_t txpow, txpowlimit;
+ u_int32_t txpow;
- txpowlimit = (sc->sc_config.txpowlimit_override) ?
- sc->sc_config.txpowlimit_override : sc->sc_config.txpowlimit;
-
- if (sc->sc_curtxpow != txpowlimit) {
- ath9k_hw_SetTxPowerLimit(ah, txpowlimit, tpcInDb);
+ if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
+ ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
/* read back in case value is clamped */
ath9k_hw_getcapability(ah, HAL_CAP_TXPOW, 1, &txpow);
sc->sc_curtxpow = txpow;
}
-
- /* Fetch max tx power level and update protocal stack */
- ath9k_hw_getcapability(ah, HAL_CAP_TXPOW, 2, &txpow);
-
- ath__update_txpow(sc, sc->sc_curtxpow, txpow);
}
/* Return the current country and domain information */
memzero(dd, sizeof(*dd));
}
-/*
- * Endian Swap for transmit descriptor
- *
- * XXX: Move cpu_to_le32() into hw.c and anywhere we set them, then
- * remove this.
-*/
-void ath_desc_swap(struct ath_desc *ds)
-{
- ds->ds_link = cpu_to_le32(ds->ds_link);
- ds->ds_data = cpu_to_le32(ds->ds_data);
- ds->ds_ctl0 = cpu_to_le32(ds->ds_ctl0);
- ds->ds_ctl1 = cpu_to_le32(ds->ds_ctl1);
- ds->ds_hw[0] = cpu_to_le32(ds->ds_hw[0]);
- ds->ds_hw[1] = cpu_to_le32(ds->ds_hw[1]);
-}
-
/*************/
/* Utilities */
/*************/
void ath_descdma_cleanup(struct ath_softc *sc,
struct ath_descdma *dd,
struct list_head *head);
-void ath_desc_swap(struct ath_desc *ds);
/******/
/* RX */
int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
int ath_get_mac80211_qnum(u_int queue, struct ath_softc *sc);
void ath_setslottime(struct ath_softc *sc);
-void ath_update_txpow(struct ath_softc *sc, u_int16_t tpcInDb);
+void ath_update_txpow(struct ath_softc *sc);
int ath_cabq_update(struct ath_softc *);
void ath_get_currentCountry(struct ath_softc *sc,
struct hal_country_entry *ctry);
int direction,
dma_addr_t *pa);
void ath_mcast_merge(struct ath_softc *sc, u_int32_t mfilt[2]);
-void ath__update_txpow(struct ath_softc *sc,
- u_int16_t txpowlimit,
- u_int16_t txpowlevel);
enum hal_ht_macmode ath_cwm_macmode(struct ath_softc *sc);
#endif /* CORE_H */
u_int16_t magic, magic2;
int addr;
- if (ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
+ if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
&magic)) {
HDPRINTF(ah, HAL_DBG_EEPROM,
"%s: Reading Magic # failed\n", __func__);
else
el = ahp->ah_eeprom.baseEepHeader.length;
+ if (el < sizeof(struct ar5416_eeprom))
+ el = sizeof(struct ar5416_eeprom) / sizeof(u_int16_t);
+ else
+ el = el / sizeof(u_int16_t);
+
eepdata = (u_int16_t *) (&ahp->ah_eeprom);
- for (i = 0; i <
- min(el, sizeof(struct ar5416_eeprom)) / sizeof(u_int16_t); i++)
+
+ for (i = 0; i < el; i++)
sum ^= *eepdata++;
if (need_swap) {
AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
}
-enum hal_bool
-ath9k_hw_SetTxPowerLimit(struct ath_hal *ah, u_int32_t limit,
- u_int16_t tpcInDb)
+enum hal_bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u_int32_t limit)
{
struct ath_hal_5416 *ahp = AH5416(ah);
struct hal_channel_internal *ichan = ah->ah_curchan;
case AR5416_DEVID_PCI:
case AR5416_DEVID_PCIE:
return "Atheros 5416";
+ case AR9160_DEVID_PCI:
+ return "Atheros 9160";
case AR9280_DEVID_PCI:
case AR9280_DEVID_PCIE:
return "Atheros 9280";
switch (devid) {
case AR5416_DEVID_PCI:
case AR5416_DEVID_PCIE:
+ case AR9160_DEVID_PCI:
case AR9280_DEVID_PCI:
case AR9280_DEVID_PCIE:
ah = ath9k_hw_do_attach(devid, sc, mem, error);
hchan.channel = curchan->center_freq;
hchan.channelFlags = ath_chan2flags(curchan, sc);
+ sc->sc_config.txpowlimit = 2 * conf->power_level;
/* set h/w channel */
if (ath_set_channel(sc, &hchan) < 0)
}
}
-void ath__update_txpow(struct ath_softc *sc,
- u_int16_t txpowlimit,
- u_int16_t txpowlevel)
-{
-
-}
-
void ath_get_beaconconfig(struct ath_softc *sc,
int if_id,
struct ath_beacon_config *conf)
ath9k_hw_stoppcurecv(ah); /* disable PCU */
ath9k_hw_setrxfilter(ah, 0); /* clear recv filter */
stopped = ath9k_hw_stopdmarecv(ah); /* disable DMA engine */
- udelay(3000); /* 3ms is long enough for 1 frame */
+ mdelay(3); /* 3ms is long enough for 1 frame */
tsf = ath9k_hw_gettsf64(ah);
sc->sc_rxlink = NULL; /* just in case */
return stopped;
* Use skb's entire data area instead.
*/
*pa = pci_map_single(sc->pdev, skb->data,
- skb->end - skb->head, direction);
+ skb_end_pointer(skb) - skb->head, direction);
return *pa;
}
dma_addr_t *pa)
{
/* Unmap skb's entire data area */
- pci_unmap_single(sc->pdev, *pa, skb->end - skb->head, direction);
+ pci_unmap_single(sc->pdev, *pa,
+ skb_end_pointer(skb) - skb->head, direction);
}
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
+#include <linux/kernel.h>
+#include <linux/slab.h>
#include "ath9k.h"
#include "regd.h"
#include "regd_common.h"
DPRINTF(sc, ATH_DEBUG_TX_PROC,
"%s: txq depth = %d\n", __func__, txq->axq_depth);
if (txq->axq_link != NULL) {
- *txq->axq_link = cpu_to_le32(bf->bf_daddr);
+ *txq->axq_link = bf->bf_daddr;
DPRINTF(sc, ATH_DEBUG_XMIT,
"%s: link[%u](%p)=%llx (%p)\n",
__func__,
__func__, txq->axq_qnum,
ito64(bf->bf_daddr), bf->bf_desc);
} else {
- *txq->axq_link = cpu_to_le32(bf->bf_daddr);
+ *txq->axq_link = bf->bf_daddr;
DPRINTF(sc, ATH_DEBUG_XMIT, "%s: link[%u] (%p)=%llx (%p)\n",
__func__,
txq->axq_qnum, txq->axq_link,
AH_TRUE, /* first segment */
(n_sg == 1) ? AH_TRUE : AH_FALSE, /* last segment */
ds); /* first descriptor */
- ath_desc_swap(ds);
bf->bf_lastfrm = bf;
bf->bf_ht = txctl->ht;
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