drm/i915: Be optimistic about future display engines having 7 WM levels

As we're doing throughout the code, being optimistic that platform n + 1
will mostly reuse the same things as platform n allows us to minimize
the enabling work needed.

This time, it's about the number of WM levels.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index af2606098cf9fb042b996a6e252e5cf2dfe7f47d..f08264ca1d302b7af45502de28cba82a1d5061cf 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1946,7 +1946,7 @@ static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
 int ilk_wm_max_level(const struct drm_device *dev)
 {
        /* how many WM levels are we expecting */
-       if (IS_GEN9(dev))
+       if (INTEL_INFO(dev)->gen >= 9)
                return 7;
        else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
                return 4;