--- /dev/null
+From 00e8573d4336a2606339b699881f0e5df7a23850 Mon Sep 17 00:00:00 2001
+From: Luis R. Rodriguez <lrodriguez@atheros.com>
+Date: Thu, 10 Jun 2010 11:45:05 -0700
+Subject: [PATCH 01/24] ath9k_hw: move clock definitions from hw.c to hw.h
+
+These will be used by the ANI code next.
+
+Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
+---
+ drivers/net/wireless/ath/ath9k/hw.c | 5 -----
+ drivers/net/wireless/ath/ath9k/hw.h | 5 +++++
+ 2 files changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
+index 2adc7e7..5f46861 100644
+--- a/drivers/net/wireless/ath/ath9k/hw.c
++++ b/drivers/net/wireless/ath/ath9k/hw.c
+@@ -23,11 +23,6 @@
+ #include "rc.h"
+ #include "ar9003_mac.h"
+
+-#define ATH9K_CLOCK_RATE_CCK 22
+-#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
+-#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
+-#define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
+-
+ static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
+
+ MODULE_AUTHOR("Atheros Communications");
+diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
+index 88bf2fc..3a28cdc 100644
+--- a/drivers/net/wireless/ath/ath9k/hw.h
++++ b/drivers/net/wireless/ath/ath9k/hw.h
+@@ -938,4 +938,9 @@ void ar9003_hw_attach_ops(struct ath_hw *ah);
+ #define ATH_PCIE_CAP_LINK_L0S 1
+ #define ATH_PCIE_CAP_LINK_L1 2
+
++#define ATH9K_CLOCK_RATE_CCK 22
++#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
++#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
++#define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
++
+ #endif
+--
+1.6.3.3
+
--- /dev/null
+From 694b7146213ff7aa3c142a8272fa4b6c4b1680e5 Mon Sep 17 00:00:00 2001
+From: Luis R. Rodriguez <lrodriguez@atheros.com>
+Date: Thu, 10 Jun 2010 13:18:11 -0700
+Subject: [PATCH 02/24] ath9k_hw: fix clock rate calculations for ANI
+
+The clock rate was assumed to be static but it actually
+changes depending on the mode of operation, correct this
+to help improve the calcuation of the listenTime for ANI.
+This change will help adjust ANI more accurately on different
+PHY thresholds.
+
+Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
+---
+ drivers/net/wireless/ath/ath9k/ani.c | 31 ++++++++++++++++++++++++++++++-
+ 1 files changed, 30 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c
+index 3da820f..e879055 100644
+--- a/drivers/net/wireless/ath/ath9k/ani.c
++++ b/drivers/net/wireless/ath/ath9k/ani.c
+@@ -259,6 +259,27 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah)
+ }
+ }
+
++static u8 ath9k_hw_chan_2_clockrate_mhz(struct ath_hw *ah)
++{
++ struct ath9k_channel *chan = ah->curchan;
++ struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
++ u8 clockrate; /* in MHz */
++
++ if (!ah->curchan) /* should really check for CCK instead */
++ clockrate = ATH9K_CLOCK_RATE_CCK;
++ else if (conf->channel->band == IEEE80211_BAND_2GHZ)
++ clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
++ else if (IS_CHAN_A_FAST_CLOCK(ah, chan))
++ clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
++ else
++ clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
++
++ if (conf_is_ht40(conf))
++ return clockrate * 2;
++
++ return clockrate * 2;
++}
++
+ static int32_t ath9k_hw_ani_get_listen_time(struct ath_hw *ah)
+ {
+ struct ar5416AniState *aniState;
+@@ -278,7 +299,15 @@ static int32_t ath9k_hw_ani_get_listen_time(struct ath_hw *ah)
+ int32_t ccdelta = cycleCount - aniState->cycleCount;
+ int32_t rfdelta = rxFrameCount - aniState->rxFrameCount;
+ int32_t tfdelta = txFrameCount - aniState->txFrameCount;
+- listenTime = (ccdelta - rfdelta - tfdelta) / 44000;
++ int32_t clock_rate = ath9k_hw_chan_2_clockrate_mhz(ah) * 1000;;
++
++ /*
++ * convert HW counter values to ms using mode
++ * specifix clock rate
++ */
++ clock_rate = ath9k_hw_chan_2_clockrate_mhz(ah) * 1000;;
++
++ listenTime = (ccdelta - rfdelta - tfdelta) / clock_rate;
+ }
+ aniState->cycleCount = cycleCount;
+ aniState->txFrameCount = txFrameCount;
+--
+1.6.3.3
+
--- /dev/null
+From f1a09b2be14f33e3fff7fdaa723994a910bd92a8 Mon Sep 17 00:00:00 2001
+From: Luis R. Rodriguez <lrodriguez@atheros.com>
+Date: Thu, 10 Jun 2010 16:01:04 -0700
+Subject: [PATCH 03/24] ath9k_hw: clear MIB interrupt causes when skipping ANI adjustments
+
+We get an MIB interrupt when we hit certain PHY error counter
+thresholds. If ANI is disabled but the MIB interrupt is enabled
+we'll keep around the old MIB interrupt causes.
+
+Since ath9k disables the MIB interrupt when ANI is disabled
+this is not a fix, but more of a sanity fix in case we ever
+need the MIB interrupt enabled but disabling ANI.
+
+Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
+---
+ drivers/net/wireless/ath/ath9k/ani.c | 9 ++++++++-
+ 1 files changed, 8 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c
+index e879055..66d0b88 100644
+--- a/drivers/net/wireless/ath/ath9k/ani.c
++++ b/drivers/net/wireless/ath/ath9k/ani.c
+@@ -585,8 +585,15 @@ void ath9k_hw_procmibevent(struct ath_hw *ah)
+ /* Clear the mib counters and save them in the stats */
+ ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
+
+- if (!DO_ANI(ah))
++ if (!DO_ANI(ah)) {
++ /*
++ * We must always clear the interrupt cause by
++ * resetting the phy error regs.
++ */
++ REG_WRITE(ah, AR_PHY_ERR_1, 0);
++ REG_WRITE(ah, AR_PHY_ERR_2, 0);
+ return;
++ }
+
+ /* NB: these are not reset-on-read */
+ phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
+--
+1.6.3.3
+
--- /dev/null
+From 9e4efe136ffbefaddbce8c4cf23fdcd45b872c6e Mon Sep 17 00:00:00 2001
+From: Luis R. Rodriguez <lrodriguez@atheros.com>
+Date: Mon, 7 Jun 2010 16:14:12 -0700
+Subject: [PATCH 04/24] ath9k_hw: allow for spliting up ANI operations by family
+
+The AR9003 hardware family will use a slightly modified ANI
+implementation which has not yet been tested on the other hardware
+families. To allow for this new ANI implementation a few ANI
+calls need to be abstracted away. This patch just allows for
+each hardware family to declare their own ANI ops and annotates
+the current ANI implementation as old.
+
+Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
+---
+ drivers/net/wireless/ath/ath9k/ani.c | 30 +++++++++++++++++++++------
+ drivers/net/wireless/ath/ath9k/ani.h | 4 ---
+ drivers/net/wireless/ath/ath9k/ar9002_hw.c | 2 +
+ drivers/net/wireless/ath/ath9k/ar9003_hw.c | 2 +
+ drivers/net/wireless/ath/ath9k/hw-ops.h | 16 ++++++++++++++
+ drivers/net/wireless/ath/ath9k/hw.h | 29 +++++++++++++++++++++++++++
+ drivers/net/wireless/ath/ath9k/mac.c | 1 +
+ 7 files changed, 73 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c
+index 66d0b88..28a1dc3 100644
+--- a/drivers/net/wireless/ath/ath9k/ani.c
++++ b/drivers/net/wireless/ath/ath9k/ani.c
+@@ -17,6 +17,12 @@
+ #include "hw.h"
+ #include "hw-ops.h"
+
++/* Private to ani.c */
++static inline void ath9k_hw_ani_lower_immunity(struct ath_hw *ah)
++{
++ ath9k_hw_private_ops(ah)->ani_lower_immunity(ah);
++}
++
+ static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
+ struct ath9k_channel *chan)
+ {
+@@ -206,7 +212,7 @@ static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah)
+ }
+ }
+
+-static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah)
++static void ath9k_hw_ani_lower_immunity_old(struct ath_hw *ah)
+ {
+ struct ar5416AniState *aniState;
+ int32_t rssi;
+@@ -316,7 +322,7 @@ static int32_t ath9k_hw_ani_get_listen_time(struct ath_hw *ah)
+ return listenTime;
+ }
+
+-void ath9k_ani_reset(struct ath_hw *ah)
++static void ath9k_ani_reset_old(struct ath_hw *ah)
+ {
+ struct ar5416AniState *aniState;
+ struct ath9k_channel *chan = ah->curchan;
+@@ -402,8 +408,8 @@ void ath9k_ani_reset(struct ath_hw *ah)
+ DISABLE_REGWRITE_BUFFER(ah);
+ }
+
+-void ath9k_hw_ani_monitor(struct ath_hw *ah,
+- struct ath9k_channel *chan)
++static void ath9k_hw_ani_monitor_old(struct ath_hw *ah,
++ struct ath9k_channel *chan)
+ {
+ struct ar5416AniState *aniState;
+ struct ath_common *common = ath9k_hw_common(ah);
+@@ -487,7 +493,6 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
+ }
+ }
+ }
+-EXPORT_SYMBOL(ath9k_hw_ani_monitor);
+
+ void ath9k_enable_mib_counters(struct ath_hw *ah)
+ {
+@@ -572,7 +577,7 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah,
+ * any of the MIB counters overflow/trigger so don't assume we're
+ * here because a PHY error counter triggered.
+ */
+-void ath9k_hw_procmibevent(struct ath_hw *ah)
++static void ath9k_hw_proc_mib_event_old(struct ath_hw *ah)
+ {
+ u32 phyCnt1, phyCnt2;
+
+@@ -628,7 +633,6 @@ void ath9k_hw_procmibevent(struct ath_hw *ah)
+ ath9k_ani_restart(ah);
+ }
+ }
+-EXPORT_SYMBOL(ath9k_hw_procmibevent);
+
+ void ath9k_hw_ani_setup(struct ath_hw *ah)
+ {
+@@ -694,3 +698,15 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
+ if (ah->config.enable_ani)
+ ah->proc_phyerr |= HAL_PROCESS_ANI;
+ }
++
++void ath9k_hw_attach_ani_ops_old(struct ath_hw *ah)
++{
++ struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
++ struct ath_hw_ops *ops = ath9k_hw_ops(ah);
++
++ priv_ops->ani_reset = ath9k_ani_reset_old;
++ priv_ops->ani_lower_immunity = ath9k_hw_ani_lower_immunity_old;
++
++ ops->ani_proc_mib_event = ath9k_hw_proc_mib_event_old;
++ ops->ani_monitor = ath9k_hw_ani_monitor_old;
++}
+diff --git a/drivers/net/wireless/ath/ath9k/ani.h b/drivers/net/wireless/ath/ath9k/ani.h
+index 3356762..4631ab2 100644
+--- a/drivers/net/wireless/ath/ath9k/ani.h
++++ b/drivers/net/wireless/ath/ath9k/ani.h
+@@ -108,14 +108,10 @@ struct ar5416Stats {
+ };
+ #define ah_mibStats stats.ast_mibstats
+
+-void ath9k_ani_reset(struct ath_hw *ah);
+-void ath9k_hw_ani_monitor(struct ath_hw *ah,
+- struct ath9k_channel *chan);
+ void ath9k_enable_mib_counters(struct ath_hw *ah);
+ void ath9k_hw_disable_mib_counters(struct ath_hw *ah);
+ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah, u32 *rxc_pcnt,
+ u32 *rxf_pcnt, u32 *txf_pcnt);
+-void ath9k_hw_procmibevent(struct ath_hw *ah);
+ void ath9k_hw_ani_setup(struct ath_hw *ah);
+ void ath9k_hw_ani_init(struct ath_hw *ah);
+
+diff --git a/drivers/net/wireless/ath/ath9k/ar9002_hw.c b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
+index 7ba9dd6..917eae0 100644
+--- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
++++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
+@@ -636,4 +636,6 @@ void ar9002_hw_attach_ops(struct ath_hw *ah)
+
+ ar9002_hw_attach_calib_ops(ah);
+ ar9002_hw_attach_mac_ops(ah);
++
++ ath9k_hw_attach_ani_ops_old(ah);
+ }
+diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+index 863f61e..b757470 100644
+--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+@@ -313,4 +313,6 @@ void ar9003_hw_attach_ops(struct ath_hw *ah)
+ ar9003_hw_attach_phy_ops(ah);
+ ar9003_hw_attach_calib_ops(ah);
+ ar9003_hw_attach_mac_ops(ah);
++
++ ath9k_hw_attach_ani_ops_old(ah);
+ }
+diff --git a/drivers/net/wireless/ath/ath9k/hw-ops.h b/drivers/net/wireless/ath/ath9k/hw-ops.h
+index 624422a..65d2c66 100644
+--- a/drivers/net/wireless/ath/ath9k/hw-ops.h
++++ b/drivers/net/wireless/ath/ath9k/hw-ops.h
+@@ -128,6 +128,17 @@ static inline void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
+ ath9k_hw_ops(ah)->set11n_virtualmorefrag(ah, ds, vmf);
+ }
+
++static inline void ath9k_hw_procmibevent(struct ath_hw *ah)
++{
++ ath9k_hw_ops(ah)->ani_proc_mib_event(ah);
++}
++
++static inline void ath9k_hw_ani_monitor(struct ath_hw *ah,
++ struct ath9k_channel *chan)
++{
++ ath9k_hw_ops(ah)->ani_monitor(ah, chan);
++}
++
+ /* Private hardware call ops */
+
+ /* PHY ops */
+@@ -277,4 +288,9 @@ static inline bool ath9k_hw_iscal_supported(struct ath_hw *ah,
+ return ath9k_hw_private_ops(ah)->iscal_supported(ah, calType);
+ }
+
++static inline void ath9k_ani_reset(struct ath_hw *ah)
++{
++ ath9k_hw_private_ops(ah)->ani_reset(ah);
++}
++
+ #endif /* ATH9K_HW_OPS_H */
+diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
+index 3a28cdc..a207a70 100644
+--- a/drivers/net/wireless/ath/ath9k/hw.h
++++ b/drivers/net/wireless/ath/ath9k/hw.h
+@@ -511,6 +511,15 @@ struct ath_gen_timer_table {
+ * @setup_calibration: set up calibration
+ * @iscal_supported: used to query if a type of calibration is supported
+ * @loadnf: load noise floor read from each chain on the CCA registers
++ *
++ * @ani_reset: reset ANI parameters to default values
++ * @ani_lower_immunity: lower the noise immunity level. The level controls
++ * the power-based packet detection on hardware. If a power jump is
++ * detected the adapter takes it as an indication that a packet has
++ * arrived. The level ranges from 0-5. Each level corresponds to a
++ * few dB more of noise immunity. If you have a strong time-varying
++ * interference that is causing false detections (OFDM timing errors or
++ * CCK timing errors) the level can be increased.
+ */
+ struct ath_hw_private_ops {
+ /* Calibration ops */
+@@ -554,6 +563,10 @@ struct ath_hw_private_ops {
+ int param);
+ void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
+ void (*loadnf)(struct ath_hw *ah, struct ath9k_channel *chan);
++
++ /* ANI */
++ void (*ani_reset)(struct ath_hw *ah);
++ void (*ani_lower_immunity)(struct ath_hw *ah);
+ };
+
+ /**
+@@ -564,6 +577,11 @@ struct ath_hw_private_ops {
+ *
+ * @config_pci_powersave:
+ * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
++ *
++ * @ani_proc_mib_event: process MIB events, this would happen upon specific ANI
++ * thresholds being reached or having overflowed.
++ * @ani_monitor: called periodically by the core driver to collect
++ * MIB stats and adjust ANI if specific thresholds have been reached.
+ */
+ struct ath_hw_ops {
+ void (*config_pci_powersave)(struct ath_hw *ah,
+@@ -604,6 +622,9 @@ struct ath_hw_ops {
+ u32 burstDuration);
+ void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds,
+ u32 vmf);
++
++ void (*ani_proc_mib_event)(struct ath_hw *ah);
++ void (*ani_monitor)(struct ath_hw *ah, struct ath9k_channel *chan);
+ };
+
+ struct ath_hw {
+@@ -934,6 +955,14 @@ void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
+ void ar9002_hw_attach_ops(struct ath_hw *ah);
+ void ar9003_hw_attach_ops(struct ath_hw *ah);
+
++/*
++ * ANI work can be shared between all families but a next
++ * generation implementation of ANI will be used only for AR9003 only
++ * for now as the other families still need to be tested with the same
++ * next generation ANI.
++ */
++void ath9k_hw_attach_ani_ops_old(struct ath_hw *ah);
++
+ #define ATH_PCIE_CAP_LINK_CTRL 0x70
+ #define ATH_PCIE_CAP_LINK_L0S 1
+ #define ATH_PCIE_CAP_LINK_L1 2
+diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
+index 0e425cb..b4d0198 100644
+--- a/drivers/net/wireless/ath/ath9k/mac.c
++++ b/drivers/net/wireless/ath/ath9k/mac.c
+@@ -15,6 +15,7 @@
+ */
+
+ #include "hw.h"
++#include "hw-ops.h"
+
+ static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
+ struct ath9k_tx_queue_info *qi)
+--
+1.6.3.3
+
--- /dev/null
+From 5d74177cf9491a28c0f4a44ef8d3b9af5a4c098d Mon Sep 17 00:00:00 2001
+From: Luis R. Rodriguez <lrodriguez@atheros.com>
+Date: Tue, 8 Jun 2010 08:03:38 -0700
+Subject: [PATCH 05/24] ath9k_hw: add register definitions for the new ANI
+
+Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
+---
+ drivers/net/wireless/ath/ath9k/ar9002_phy.h | 7 +++++++
+ drivers/net/wireless/ath/ath9k/ar9003_phy.h | 8 ++++++++
+ 2 files changed, 15 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath9k/ar9002_phy.h b/drivers/net/wireless/ath/ath9k/ar9002_phy.h
+index 81bf6e5..ce8bb00 100644
+--- a/drivers/net/wireless/ath/ath9k/ar9002_phy.h
++++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.h
+@@ -114,6 +114,10 @@
+ #define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
+ #define AR_PHY_FIND_SIG_FIRPWR_S 18
+
++#define AR_PHY_FIND_SIG_LOW 0x9840
++#define AR_PHY_FIND_SIG_FIRSTEP_LOW 0x00000FC0L
++#define AR_PHY_FIND_SIG_FIRSTEP_LOW_S 6
++
+ #define AR_PHY_AGC_CTL1 0x985C
+ #define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80
+ #define AR_PHY_AGC_CTL1_COARSE_LOW_S 7
+@@ -325,6 +329,9 @@
+ #define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9
+ #define AR_PHY_EXT_CCA_THRESH62 0x007F0000
+ #define AR_PHY_EXT_CCA_THRESH62_S 16
++#define AR_PHY_EXT_TIMING5_CYCPWR_THR1 0x0000FE00L
++#define AR_PHY_EXT_TIMING5_CYCPWR_THR1_S 9
++
+ #define AR_PHY_EXT_MINCCA_PWR 0xFF800000
+ #define AR_PHY_EXT_MINCCA_PWR_S 23
+ #define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000
+diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
+index 676d3f1..265f59f 100644
+--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
++++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
+@@ -149,6 +149,8 @@
+ #define AR_PHY_EXT_CCA_THRESH62_S 16
+ #define AR_PHY_EXT_MINCCA_PWR 0x01FF0000
+ #define AR_PHY_EXT_MINCCA_PWR_S 16
++#define AR_PHY_EXT_CYCPWR_THR1 0x0000FE00L
++#define AR_PHY_EXT_CYCPWR_THR1_S 9
+ #define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
+ #define AR_PHY_TIMING5_CYCPWR_THR1_S 1
+ #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE 0x00000001
+@@ -283,6 +285,12 @@
+ #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ 0x1ffffe00
+ #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S 9
+
++#define AR_PHY_MRC_CCK_CTRL (AR_AGC_BASE + 0x1d0)
++#define AR_PHY_MRC_CCK_ENABLE 0x00000001
++#define AR_PHY_MRC_CCK_ENABLE_S 0
++#define AR_PHY_MRC_CCK_MUX_REG 0x00000002
++#define AR_PHY_MRC_CCK_MUX_REG_S 1
++
+ #define AR_PHY_RX_OCGAIN (AR_AGC_BASE + 0x200)
+
+ #define AR_PHY_CCA_NOM_VAL_9300_2GHZ -110
+--
+1.6.3.3
+
--- /dev/null
+From 2f000255f616118e349b428cf323ce98980ab0fd Mon Sep 17 00:00:00 2001
+From: Luis R. Rodriguez <lrodriguez@atheros.com>
+Date: Tue, 8 Jun 2010 08:03:38 -0700
+Subject: [PATCH 06/24] ath9k_hw: inform ANI calibration when scanning
+
+The new ANI implementation will use this to skip ANI
+calibration upon a scan. This cannot be ported to the
+older ANI implementation unless default ANI values from
+the ANI are also used upon a scan. This is essentially
+what one of the things thenew ANI does.
+
+Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
+---
+ drivers/net/wireless/ath/ath9k/ani.c | 2 +-
+ drivers/net/wireless/ath/ath9k/htc_drv_txrx.c | 2 +-
+ drivers/net/wireless/ath/ath9k/hw-ops.h | 4 ++--
+ drivers/net/wireless/ath/ath9k/hw.h | 2 +-
+ drivers/net/wireless/ath/ath9k/mac.c | 4 ++--
+ drivers/net/wireless/ath/ath9k/mac.h | 2 +-
+ drivers/net/wireless/ath/ath9k/recv.c | 4 ++--
+ 7 files changed, 10 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c
+index 28a1dc3..f5b9719 100644
+--- a/drivers/net/wireless/ath/ath9k/ani.c
++++ b/drivers/net/wireless/ath/ath9k/ani.c
+@@ -322,7 +322,7 @@ static int32_t ath9k_hw_ani_get_listen_time(struct ath_hw *ah)
+ return listenTime;
+ }
+
+-static void ath9k_ani_reset_old(struct ath_hw *ah)
++static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
+ {
+ struct ar5416AniState *aniState;
+ struct ath9k_channel *chan = ah->curchan;
+diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
+index f0cca4e..ffebd5a 100644
+--- a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
++++ b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
+@@ -416,7 +416,7 @@ void ath9k_host_rx_init(struct ath9k_htc_priv *priv)
+ {
+ ath9k_hw_rxena(priv->ah);
+ ath9k_htc_opmode_init(priv);
+- ath9k_hw_startpcureceive(priv->ah);
++ ath9k_hw_startpcureceive(priv->ah, (priv->op_flags & OP_SCANNING));
+ priv->rx.last_rssi = ATH_RSSI_DUMMY_MARKER;
+ }
+
+diff --git a/drivers/net/wireless/ath/ath9k/hw-ops.h b/drivers/net/wireless/ath/ath9k/hw-ops.h
+index 65d2c66..381da6c 100644
+--- a/drivers/net/wireless/ath/ath9k/hw-ops.h
++++ b/drivers/net/wireless/ath/ath9k/hw-ops.h
+@@ -288,9 +288,9 @@ static inline bool ath9k_hw_iscal_supported(struct ath_hw *ah,
+ return ath9k_hw_private_ops(ah)->iscal_supported(ah, calType);
+ }
+
+-static inline void ath9k_ani_reset(struct ath_hw *ah)
++static inline void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
+ {
+- ath9k_hw_private_ops(ah)->ani_reset(ah);
++ ath9k_hw_private_ops(ah)->ani_reset(ah, is_scanning);
+ }
+
+ #endif /* ATH9K_HW_OPS_H */
+diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
+index a207a70..790a457 100644
+--- a/drivers/net/wireless/ath/ath9k/hw.h
++++ b/drivers/net/wireless/ath/ath9k/hw.h
+@@ -565,7 +565,7 @@ struct ath_hw_private_ops {
+ void (*loadnf)(struct ath_hw *ah, struct ath9k_channel *chan);
+
+ /* ANI */
+- void (*ani_reset)(struct ath_hw *ah);
++ void (*ani_reset)(struct ath_hw *ah, bool is_scanning);
+ void (*ani_lower_immunity)(struct ath_hw *ah);
+ };
+
+diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
+index b4d0198..1550591 100644
+--- a/drivers/net/wireless/ath/ath9k/mac.c
++++ b/drivers/net/wireless/ath/ath9k/mac.c
+@@ -757,11 +757,11 @@ void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp)
+ }
+ EXPORT_SYMBOL(ath9k_hw_putrxbuf);
+
+-void ath9k_hw_startpcureceive(struct ath_hw *ah)
++void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning)
+ {
+ ath9k_enable_mib_counters(ah);
+
+- ath9k_ani_reset(ah);
++ ath9k_ani_reset(ah, is_scanning);
+
+ REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
+ }
+diff --git a/drivers/net/wireless/ath/ath9k/mac.h b/drivers/net/wireless/ath/ath9k/mac.h
+index 00f3e0c..3c65c91 100644
+--- a/drivers/net/wireless/ath/ath9k/mac.h
++++ b/drivers/net/wireless/ath/ath9k/mac.h
+@@ -715,7 +715,7 @@ void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
+ u32 size, u32 flags);
+ bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set);
+ void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp);
+-void ath9k_hw_startpcureceive(struct ath_hw *ah);
++void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning);
+ void ath9k_hw_stoppcurecv(struct ath_hw *ah);
+ void ath9k_hw_abortpcurecv(struct ath_hw *ah);
+ bool ath9k_hw_stopdmarecv(struct ath_hw *ah);
+diff --git a/drivers/net/wireless/ath/ath9k/recv.c b/drivers/net/wireless/ath/ath9k/recv.c
+index d373364..5141cd8 100644
+--- a/drivers/net/wireless/ath/ath9k/recv.c
++++ b/drivers/net/wireless/ath/ath9k/recv.c
+@@ -295,7 +295,7 @@ static void ath_edma_start_recv(struct ath_softc *sc)
+
+ ath_opmode_init(sc);
+
+- ath9k_hw_startpcureceive(sc->sc_ah);
++ ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_SCANNING));
+ }
+
+ static void ath_edma_stop_recv(struct ath_softc *sc)
+@@ -501,7 +501,7 @@ int ath_startrecv(struct ath_softc *sc)
+ start_recv:
+ spin_unlock_bh(&sc->rx.rxbuflock);
+ ath_opmode_init(sc);
+- ath9k_hw_startpcureceive(ah);
++ ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_SCANNING));
+
+ return 0;
+ }
+--
+1.6.3.3
+
--- /dev/null
+From 2ef01607265eae16645a29d7a46774ab1239cc77 Mon Sep 17 00:00:00 2001
+From: Luis R. Rodriguez <lrodriguez@atheros.com>
+Date: Tue, 8 Jun 2010 08:03:38 -0700
+Subject: [PATCH 07/24] ath9k: add new ANI implementation for AR9003
+
+This adds support for ANI for AR9003. The implementation for
+ANI for AR9003 is slightly different than the one used for
+the older chipset families. It can technically be used for
+the older families as well but this is not yet fully tested
+so we only enable the new ANI for the AR5008, AR9001 and AR9002
+families with a module parameter, force_new_ani.
+
+The old ANI implementation is left intact.
+
+Details of the new ANI implemention:
+
+ * ANI adjustment logic is now table driven so that each ANI level
+ setting is parameterized. This makes adjustments much more
+ deterministic than the old procedure based logic and allows
+ adjustments to be made incrementally to several parameters per
+ level.
+
+ * ANI register settings are now relative to INI values; so ANI
+ param zero level == INI value. Appropriate floor and ceiling
+ values are obeyed when adjustments are combined with INI values.
+
+ * ANI processing is done once per second rather that every 100ms.
+ The poll interval is now a set upon hardware initialization and
+ can be picked up by the core driver.
+
+ * OFDM error and CCK error processing are made in a round robin
+ fashion rather than allowing all OFDM adjustments to be made
+ before CCK adjustments.
+
+ * ANI adjusts MRC CCK off in the presence of high CCK errors
+
+ * When adjusting spur immunity (SI) and OFDM weak signal detection,
+ ANI now sets register values for the extension channel too
+
+ * When adjusting FIR step (ST), ANI now sets register for FIR step
+ low too
+
+ * FIR step adjustments now allow for an extra level of immunity for
+ extremely noisy environments
+
+ * The old Noise immunity setting (NI), which changes coarse low, size
+ desired, etc have been removed. Changing these settings could affect
+ up RIFS RX as well.
+
+ * CCK weak signal adjustment is no longer used
+
+ * ANI no longer enables phy error interrupts; in all cases phy hw
+ counting registers are used instead
+
+ * The phy error count (overflow) interrupts are also no longer used
+ for ANI adjustments. All ANI adjustments are made via the polling
+ routine and no adjustments are possible in the ISR context anymore
+
+ * A history settings buffer is now correctly used for each channel;
+ channel settings are initialized with the defaults but later
+ changes are restored when returning back to that channel
+
+ * When scanning, ANI is disabled settings are returned to (INI) defaults.
+
+ * OFDM phy error thresholds are now 400 & 1000 (errors/second units) for
+ low/high water marks, providing increased stability/hysteresis when
+ changing levels.
+
+ * Similarly CCK phy error thresholds are now 300 & 600 (errors/second)
+
+Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
+---
+ drivers/net/wireless/ath/ath9k/ani.c | 676 +++++++++++++++++++++++++--
+ drivers/net/wireless/ath/ath9k/ani.h | 74 +++-
+ drivers/net/wireless/ath/ath9k/ar5008_phy.c | 361 ++++++++++++++-
+ drivers/net/wireless/ath/ath9k/ar9002_hw.c | 9 +-
+ drivers/net/wireless/ath/ath9k/ar9003_hw.c | 2 +-
+ drivers/net/wireless/ath/ath9k/ar9003_phy.c | 386 ++++++++++++----
+ drivers/net/wireless/ath/ath9k/ath9k.h | 3 +-
+ drivers/net/wireless/ath/ath9k/hw.c | 12 +
+ drivers/net/wireless/ath/ath9k/hw.h | 9 +-
+ drivers/net/wireless/ath/ath9k/main.c | 10 +-
+ 10 files changed, 1391 insertions(+), 151 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c
+index f5b9719..cc648b6 100644
+--- a/drivers/net/wireless/ath/ath9k/ani.c
++++ b/drivers/net/wireless/ath/ath9k/ani.c
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (c) 2008-2009 Atheros Communications Inc.
++ * Copyright (c) 2008-2010 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+@@ -17,14 +17,99 @@
+ #include "hw.h"
+ #include "hw-ops.h"
+
++struct ani_ofdm_level_entry {
++ int spur_immunity_level;
++ int fir_step_level;
++ int ofdm_weak_signal_on;
++};
++
++/* values here are relative to the INI */
++
++/*
++ * Legend:
++ *
++ * SI: Spur immunity
++ * FS: FIR Step
++ * WS: OFDM / CCK Weak Signal detection
++ * MRC-CCK: Maximal Ratio Combining for CCK
++ */
++
++static const struct ani_ofdm_level_entry ofdm_level_table[] = {
++ /* SI FS WS */
++ { 0, 0, 1 }, /* lvl 0 */
++ { 1, 1, 1 }, /* lvl 1 */
++ { 2, 2, 1 }, /* lvl 2 */
++ { 3, 2, 1 }, /* lvl 3 (default) */
++ { 4, 3, 1 }, /* lvl 4 */
++ { 5, 4, 1 }, /* lvl 5 */
++ { 6, 5, 1 }, /* lvl 6 */
++ { 7, 6, 1 }, /* lvl 7 */
++ { 7, 7, 1 }, /* lvl 8 */
++ { 7, 8, 0 } /* lvl 9 */
++};
++#define ATH9K_ANI_OFDM_NUM_LEVEL \
++ (sizeof(ofdm_level_table)/sizeof(ofdm_level_table[0]))
++#define ATH9K_ANI_OFDM_MAX_LEVEL \
++ (ATH9K_ANI_OFDM_NUM_LEVEL-1)
++#define ATH9K_ANI_OFDM_DEF_LEVEL \
++ 3 /* default level - matches the INI settings */
++
++/*
++ * MRC (Maximal Ratio Combining) has always been used with multi-antenna ofdm.
++ * With OFDM for single stream you just add up all antenna inputs, you're
++ * only interested in what you get after FFT. Signal aligment is also not
++ * required for OFDM because any phase difference adds up in the frequency
++ * domain.
++ *
++ * MRC requires extra work for use with CCK. You need to align the antenna
++ * signals from the different antenna before you can add the signals together.
++ * You need aligment of signals as CCK is in time domain, so addition can cancel
++ * your signal completely if phase is 180 degrees (think of adding sine waves).
++ * You also need to remove noise before the addition and this is where ANI
++ * MRC CCK comes into play. One of the antenna inputs may be stronger but
++ * lower SNR, so just adding after alignment can be dangerous.
++ *
++ * Regardless of alignment in time, the antenna signals add constructively after
++ * FFT and improve your reception. For more information:
++ *
++ * http://en.wikipedia.org/wiki/Maximal-ratio_combining
++ */
++
++struct ani_cck_level_entry {
++ int fir_step_level;
++ int mrc_cck_on;
++};
++
++static const struct ani_cck_level_entry cck_level_table[] = {
++ /* FS MRC-CCK */
++ { 0, 1 }, /* lvl 0 */
++ { 1, 1 }, /* lvl 1 */
++ { 2, 1 }, /* lvl 2 (default) */
++ { 3, 1 }, /* lvl 3 */
++ { 4, 0 }, /* lvl 4 */
++ { 5, 0 }, /* lvl 5 */
++ { 6, 0 }, /* lvl 6 */
++ { 7, 0 }, /* lvl 7 (only for high rssi) */
++ { 8, 0 } /* lvl 8 (only for high rssi) */
++};
++
++#define ATH9K_ANI_CCK_NUM_LEVEL \
++ (sizeof(cck_level_table)/sizeof(cck_level_table[0]))
++#define ATH9K_ANI_CCK_MAX_LEVEL \
++ (ATH9K_ANI_CCK_NUM_LEVEL-1)
++#define ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI \
++ (ATH9K_ANI_CCK_NUM_LEVEL-3)
++#define ATH9K_ANI_CCK_DEF_LEVEL \
++ 2 /* default level - matches the INI settings */
++
+ /* Private to ani.c */
+-static inline void ath9k_hw_ani_lower_immunity(struct ath_hw *ah)
++static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah)
+ {
+ ath9k_hw_private_ops(ah)->ani_lower_immunity(ah);
+ }
+
+-static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
+- struct ath9k_channel *chan)
++int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
++ struct ath9k_channel *chan)
+ {
+ int i;
+
+@@ -54,7 +139,7 @@ static void ath9k_hw_update_mibstats(struct ath_hw *ah,
+ stats->beacons += REG_READ(ah, AR_BEACON_CNT);
+ }
+
+-static void ath9k_ani_restart(struct ath_hw *ah)
++static void ath9k_ani_restart_old(struct ath_hw *ah)
+ {
+ struct ar5416AniState *aniState;
+ struct ath_common *common = ath9k_hw_common(ah);
+@@ -102,7 +187,42 @@ static void ath9k_ani_restart(struct ath_hw *ah)
+ aniState->cckPhyErrCount = 0;
+ }
+
+-static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah)
++static void ath9k_ani_restart_new(struct ath_hw *ah)
++{
++ struct ar5416AniState *aniState;
++ struct ath_common *common = ath9k_hw_common(ah);
++
++ if (!DO_ANI(ah))
++ return;
++
++ aniState = ah->curani;
++ aniState->listenTime = 0;
++
++ aniState->ofdmPhyErrBase = 0;
++ aniState->cckPhyErrBase = 0;
++
++ ath_print(common, ATH_DBG_ANI,
++ "Writing ofdmbase=%08x cckbase=%08x\n",
++ aniState->ofdmPhyErrBase,
++ aniState->cckPhyErrBase);
++
++ ENABLE_REGWRITE_BUFFER(ah);
++
++ REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
++ REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
++ REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
++ REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
++
++ REGWRITE_BUFFER_FLUSH(ah);
++ DISABLE_REGWRITE_BUFFER(ah);
++
++ ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
++
++ aniState->ofdmPhyErrCount = 0;
++ aniState->cckPhyErrCount = 0;
++}
++
++static void ath9k_hw_ani_ofdm_err_trigger_old(struct ath_hw *ah)
+ {
+ struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
+ struct ar5416AniState *aniState;
+@@ -174,7 +294,7 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah)
+ }
+ }
+
+-static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah)
++static void ath9k_hw_ani_cck_err_trigger_old(struct ath_hw *ah)
+ {
+ struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
+ struct ar5416AniState *aniState;
+@@ -212,6 +332,124 @@ static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah)
+ }
+ }
+
++/* Adjust the OFDM Noise Immunity Level */
++static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel)
++{
++ struct ar5416AniState *aniState = ah->curani;
++ struct ath_common *common = ath9k_hw_common(ah);
++ const struct ani_ofdm_level_entry *entry_ofdm;
++ const struct ani_cck_level_entry *entry_cck;
++
++ aniState->noiseFloor = BEACON_RSSI(ah);
++
++ ath_print(common, ATH_DBG_ANI,
++ "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
++ aniState->ofdmNoiseImmunityLevel,
++ immunityLevel, aniState->noiseFloor,
++ aniState->rssiThrLow, aniState->rssiThrHigh);
++
++ aniState->ofdmNoiseImmunityLevel = immunityLevel;
++
++ entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel];
++ entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel];
++
++ if (aniState->spurImmunityLevel != entry_ofdm->spur_immunity_level)
++ ath9k_hw_ani_control(ah,
++ ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
++ entry_ofdm->spur_immunity_level);
++
++ if (aniState->firstepLevel != entry_ofdm->fir_step_level &&
++ entry_ofdm->fir_step_level >= entry_cck->fir_step_level)
++ ath9k_hw_ani_control(ah,
++ ATH9K_ANI_FIRSTEP_LEVEL,
++ entry_ofdm->fir_step_level);
++
++ if ((ah->opmode != NL80211_IFTYPE_STATION &&
++ ah->opmode != NL80211_IFTYPE_ADHOC) ||
++ aniState->noiseFloor <= aniState->rssiThrHigh) {
++ if (aniState->ofdmWeakSigDetectOff)
++ /* force on ofdm weak sig detect */
++ ath9k_hw_ani_control(ah,
++ ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
++ true);
++ else if (aniState->ofdmWeakSigDetectOff ==
++ entry_ofdm->ofdm_weak_signal_on)
++ ath9k_hw_ani_control(ah,
++ ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
++ entry_ofdm->ofdm_weak_signal_on);
++ }
++}
++
++static void ath9k_hw_ani_ofdm_err_trigger_new(struct ath_hw *ah)
++{
++ struct ar5416AniState *aniState;
++
++ if (!DO_ANI(ah))
++ return;
++
++ aniState = ah->curani;
++
++ if (aniState->ofdmNoiseImmunityLevel < ATH9K_ANI_OFDM_MAX_LEVEL)
++ ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel + 1);
++}
++
++/*
++ * Set the ANI settings to match an CCK level.
++ */
++static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel)
++{
++ struct ar5416AniState *aniState = ah->curani;
++ struct ath_common *common = ath9k_hw_common(ah);
++ const struct ani_ofdm_level_entry *entry_ofdm;
++ const struct ani_cck_level_entry *entry_cck;
++
++ aniState->noiseFloor = BEACON_RSSI(ah);
++ ath_print(common, ATH_DBG_ANI,
++ "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
++ aniState->cckNoiseImmunityLevel, immunityLevel,
++ aniState->noiseFloor, aniState->rssiThrLow,
++ aniState->rssiThrHigh);
++
++ if ((ah->opmode == NL80211_IFTYPE_STATION ||
++ ah->opmode == NL80211_IFTYPE_ADHOC) &&
++ aniState->noiseFloor <= aniState->rssiThrLow &&
++ immunityLevel > ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI)
++ immunityLevel = ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI;
++
++ aniState->cckNoiseImmunityLevel = immunityLevel;
++
++ entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel];
++ entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel];
++
++ if (aniState->firstepLevel != entry_cck->fir_step_level &&
++ entry_cck->fir_step_level >= entry_ofdm->fir_step_level)
++ ath9k_hw_ani_control(ah,
++ ATH9K_ANI_FIRSTEP_LEVEL,
++ entry_cck->fir_step_level);
++
++ /* Skip MRC CCK for pre AR9003 families */
++ if (!AR_SREV_9300_20_OR_LATER(ah))
++ return;
++
++ if (aniState->mrcCCKOff == entry_cck->mrc_cck_on)
++ ath9k_hw_ani_control(ah,
++ ATH9K_ANI_MRC_CCK,
++ entry_cck->mrc_cck_on);
++}
++
++static void ath9k_hw_ani_cck_err_trigger_new(struct ath_hw *ah)
++{
++ struct ar5416AniState *aniState;
++
++ if (!DO_ANI(ah))
++ return;
++
++ aniState = ah->curani;
++
++ if (aniState->cckNoiseImmunityLevel < ATH9K_ANI_CCK_MAX_LEVEL)
++ ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel + 1);
++}
++
+ static void ath9k_hw_ani_lower_immunity_old(struct ath_hw *ah)
+ {
+ struct ar5416AniState *aniState;
+@@ -265,6 +503,28 @@ static void ath9k_hw_ani_lower_immunity_old(struct ath_hw *ah)
+ }
+ }
+
++/*
++ * only lower either OFDM or CCK errors per turn
++ * we lower the other one next time
++ */
++static void ath9k_hw_ani_lower_immunity_new(struct ath_hw *ah)
++{
++ struct ar5416AniState *aniState;
++
++ aniState = ah->curani;
++
++ /* lower OFDM noise immunity */
++ if (aniState->ofdmNoiseImmunityLevel > 0 &&
++ (aniState->ofdmsTurn || aniState->cckNoiseImmunityLevel == 0)) {
++ ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel - 1);
++ return;
++ }
++
++ /* lower CCK noise immunity */
++ if (aniState->cckNoiseImmunityLevel > 0)
++ ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel - 1);
++}
++
+ static u8 ath9k_hw_chan_2_clockrate_mhz(struct ath_hw *ah)
+ {
+ struct ath9k_channel *chan = ah->curchan;
+@@ -289,6 +549,7 @@ static u8 ath9k_hw_chan_2_clockrate_mhz(struct ath_hw *ah)
+ static int32_t ath9k_hw_ani_get_listen_time(struct ath_hw *ah)
+ {
+ struct ar5416AniState *aniState;
++ struct ath_common *common = ath9k_hw_common(ah);
+ u32 txFrameCount, rxFrameCount, cycleCount;
+ int32_t listenTime;
+
+@@ -298,14 +559,16 @@ static int32_t ath9k_hw_ani_get_listen_time(struct ath_hw *ah)
+
+ aniState = ah->curani;
+ if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) {
+-
+ listenTime = 0;
+ ah->stats.ast_ani_lzero++;
++ ath_print(common, ATH_DBG_ANI,
++ "1st call: aniState->cycleCount=%d\n",
++ aniState->cycleCount);
+ } else {
+ int32_t ccdelta = cycleCount - aniState->cycleCount;
+ int32_t rfdelta = rxFrameCount - aniState->rxFrameCount;
+ int32_t tfdelta = txFrameCount - aniState->txFrameCount;
+- int32_t clock_rate = ath9k_hw_chan_2_clockrate_mhz(ah) * 1000;;
++ int32_t clock_rate;
+
+ /*
+ * convert HW counter values to ms using mode
+@@ -314,7 +577,13 @@ static int32_t ath9k_hw_ani_get_listen_time(struct ath_hw *ah)
+ clock_rate = ath9k_hw_chan_2_clockrate_mhz(ah) * 1000;;
+
+ listenTime = (ccdelta - rfdelta - tfdelta) / clock_rate;
++
++ ath_print(common, ATH_DBG_ANI,
++ "cyclecount=%d, rfcount=%d, "
++ "tfcount=%d, listenTime=%d CLOCK_RATE=%d\n",
++ ccdelta, rfdelta, tfdelta, listenTime, clock_rate);
+ }
++
+ aniState->cycleCount = cycleCount;
+ aniState->txFrameCount = txFrameCount;
+ aniState->rxFrameCount = rxFrameCount;
+@@ -375,7 +644,7 @@ static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
+ ah->curani->cckTrigLow =
+ ah->config.cck_trig_low;
+ }
+- ath9k_ani_restart(ah);
++ ath9k_ani_restart_old(ah);
+ return;
+ }
+
+@@ -397,7 +666,101 @@ static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
+
+ ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) &
+ ~ATH9K_RX_FILTER_PHYERR);
+- ath9k_ani_restart(ah);
++ ath9k_ani_restart_old(ah);
++
++ ENABLE_REGWRITE_BUFFER(ah);
++
++ REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
++ REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
++
++ REGWRITE_BUFFER_FLUSH(ah);
++ DISABLE_REGWRITE_BUFFER(ah);
++}
++
++/*
++ * Restore the ANI parameters in the HAL and reset the statistics.
++ * This routine should be called for every hardware reset and for
++ * every channel change.
++ */
++static void ath9k_ani_reset_new(struct ath_hw *ah, bool is_scanning)
++{
++ struct ar5416AniState *aniState = ah->curani;
++ struct ath9k_channel *chan = ah->curchan;
++ struct ath_common *common = ath9k_hw_common(ah);
++
++ if (!DO_ANI(ah))
++ return;
++
++ BUG_ON(aniState == NULL);
++ ah->stats.ast_ani_reset++;
++
++ /* only allow a subset of functions in AP mode */
++ if (ah->opmode == NL80211_IFTYPE_AP) {
++ if (IS_CHAN_2GHZ(chan)) {
++ ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
++ ATH9K_ANI_FIRSTEP_LEVEL);
++ if (AR_SREV_9300_20_OR_LATER(ah))
++ ah->ani_function |= ATH9K_ANI_MRC_CCK;
++ } else
++ ah->ani_function = 0;
++ }
++
++ /* always allow mode (on/off) to be controlled */
++ ah->ani_function |= ATH9K_ANI_MODE;
++
++ if (is_scanning ||
++ (ah->opmode != NL80211_IFTYPE_STATION &&
++ ah->opmode != NL80211_IFTYPE_ADHOC)) {
++ /*
++ * If we're scanning or in AP mode, the defaults (ini)
++ * should be in place. For an AP we assume the historical
++ * levels for this channel are probably outdated so start
++ * from defaults instead.
++ */
++ if (aniState->ofdmNoiseImmunityLevel !=
++ ATH9K_ANI_OFDM_DEF_LEVEL ||
++ aniState->cckNoiseImmunityLevel !=
++ ATH9K_ANI_CCK_DEF_LEVEL) {
++ ath_print(common, ATH_DBG_ANI,
++ "Restore defaults: opmode %u "
++ "chan %d Mhz/0x%x is_scanning=%d "
++ "ofdm:%d cck:%d\n",
++ ah->opmode,
++ chan->channel,
++ chan->channelFlags,
++ is_scanning,
++ aniState->ofdmNoiseImmunityLevel,
++ aniState->cckNoiseImmunityLevel);
++
++ ath9k_hw_set_ofdm_nil(ah, ATH9K_ANI_OFDM_DEF_LEVEL);
++ ath9k_hw_set_cck_nil(ah, ATH9K_ANI_CCK_DEF_LEVEL);
++ }
++ } else {
++ /*
++ * restore historical levels for this channel
++ */
++ ath_print(common, ATH_DBG_ANI,
++ "Restore history: opmode %u "
++ "chan %d Mhz/0x%x is_scanning=%d "
++ "ofdm:%d cck:%d\n",
++ ah->opmode,
++ chan->channel,
++ chan->channelFlags,
++ is_scanning,
++ aniState->ofdmNoiseImmunityLevel,
++ aniState->cckNoiseImmunityLevel);
++
++ ath9k_hw_set_ofdm_nil(ah,
++ aniState->ofdmNoiseImmunityLevel);
++ ath9k_hw_set_cck_nil(ah,
++ aniState->cckNoiseImmunityLevel);
++ }
++
++ /*
++ * enable phy counters if hw supports or if not, enable phy
++ * interrupts (so we can count each one)
++ */
++ ath9k_ani_restart_new(ah);
+
+ ENABLE_REGWRITE_BUFFER(ah);
+
+@@ -425,7 +788,7 @@ static void ath9k_hw_ani_monitor_old(struct ath_hw *ah,
+ listenTime = ath9k_hw_ani_get_listen_time(ah);
+ if (listenTime < 0) {
+ ah->stats.ast_ani_lneg++;
+- ath9k_ani_restart(ah);
++ ath9k_ani_restart_old(ah);
+ return;
+ }
+
+@@ -479,17 +842,163 @@ static void ath9k_hw_ani_monitor_old(struct ath_hw *ah,
+ aniState->cckPhyErrCount <= aniState->listenTime *
+ aniState->cckTrigLow / 1000)
+ ath9k_hw_ani_lower_immunity(ah);
+- ath9k_ani_restart(ah);
++ ath9k_ani_restart_old(ah);
+ } else if (aniState->listenTime > ah->aniperiod) {
+ if (aniState->ofdmPhyErrCount > aniState->listenTime *
+ aniState->ofdmTrigHigh / 1000) {
+- ath9k_hw_ani_ofdm_err_trigger(ah);
+- ath9k_ani_restart(ah);
++ ath9k_hw_ani_ofdm_err_trigger_old(ah);
++ ath9k_ani_restart_old(ah);
+ } else if (aniState->cckPhyErrCount >
+ aniState->listenTime * aniState->cckTrigHigh /
+ 1000) {
+- ath9k_hw_ani_cck_err_trigger(ah);
+- ath9k_ani_restart(ah);
++ ath9k_hw_ani_cck_err_trigger_old(ah);
++ ath9k_ani_restart_old(ah);
++ }
++ }
++}
++
++static void ath9k_hw_ani_monitor_new(struct ath_hw *ah,
++ struct ath9k_channel *chan)
++{
++ struct ar5416AniState *aniState;
++ struct ath_common *common = ath9k_hw_common(ah);
++ int32_t listenTime;
++ u32 phyCnt1, phyCnt2;
++ u32 ofdmPhyErrCnt, cckPhyErrCnt;
++ u32 ofdmPhyErrRate, cckPhyErrRate;
++
++ if (!DO_ANI(ah))
++ return;
++
++ aniState = ah->curani;
++ if (WARN_ON(!aniState))
++ return;
++
++ listenTime = ath9k_hw_ani_get_listen_time(ah);
++ if (listenTime <= 0) {
++ ah->stats.ast_ani_lneg++;
++ /* restart ANI period if listenTime is invalid */
++ ath_print(common, ATH_DBG_ANI,
++ "listenTime=%d - on new ani monitor\n",
++ listenTime);
++ ath9k_ani_restart_new(ah);
++ return;
++ }
++
++ aniState->listenTime += listenTime;
++
++ ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
++
++ phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
++ phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
++
++ if (phyCnt1 < aniState->ofdmPhyErrBase ||
++ phyCnt2 < aniState->cckPhyErrBase) {
++ if (phyCnt1 < aniState->ofdmPhyErrBase) {
++ ath_print(common, ATH_DBG_ANI,
++ "phyCnt1 0x%x, resetting "
++ "counter value to 0x%x\n",
++ phyCnt1,
++ aniState->ofdmPhyErrBase);
++ REG_WRITE(ah, AR_PHY_ERR_1,
++ aniState->ofdmPhyErrBase);
++ REG_WRITE(ah, AR_PHY_ERR_MASK_1,
++ AR_PHY_ERR_OFDM_TIMING);
++ }
++ if (phyCnt2 < aniState->cckPhyErrBase) {
++ ath_print(common, ATH_DBG_ANI,
++ "phyCnt2 0x%x, resetting "
++ "counter value to 0x%x\n",
++ phyCnt2,
++ aniState->cckPhyErrBase);
++ REG_WRITE(ah, AR_PHY_ERR_2,
++ aniState->cckPhyErrBase);
++ REG_WRITE(ah, AR_PHY_ERR_MASK_2,
++ AR_PHY_ERR_CCK_TIMING);
++ }
++ return;
++ }
++
++ ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
++ ah->stats.ast_ani_ofdmerrs +=
++ ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
++ aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
++
++ cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
++ ah->stats.ast_ani_cckerrs +=
++ cckPhyErrCnt - aniState->cckPhyErrCount;
++ aniState->cckPhyErrCount = cckPhyErrCnt;
++
++ ath_print(common, ATH_DBG_ANI,
++ "Errors: OFDM=0x%08x-0x%08x=%d "
++ "CCK=0x%08x-0x%08x=%d\n",
++ phyCnt1,
++ aniState->ofdmPhyErrBase,
++ ofdmPhyErrCnt,
++ phyCnt2,
++ aniState->cckPhyErrBase,
++ cckPhyErrCnt);
++
++ ofdmPhyErrRate = aniState->ofdmPhyErrCount * 1000 /
++ aniState->listenTime;
++ cckPhyErrRate = aniState->cckPhyErrCount * 1000 /
++ aniState->listenTime;
++
++ ath_print(common, ATH_DBG_ANI,
++ "listenTime=%d OFDM:%d errs=%d/s CCK:%d "
++ "errs=%d/s ofdm_turn=%d\n",
++ listenTime, aniState->ofdmNoiseImmunityLevel,
++ ofdmPhyErrRate, aniState->cckNoiseImmunityLevel,
++ cckPhyErrRate, aniState->ofdmsTurn);
++
++ if (aniState->listenTime > 5 * ah->aniperiod) {
++ if (ofdmPhyErrRate <= aniState->ofdmTrigLow &&
++ cckPhyErrRate <= aniState->cckTrigLow) {
++ ath_print(common, ATH_DBG_ANI,
++ "1. listenTime=%d OFDM:%d errs=%d/s(<%d) "
++ "CCK:%d errs=%d/s(<%d) -> "
++ "ath9k_hw_ani_lower_immunity()\n",
++ aniState->listenTime,
++ aniState->ofdmNoiseImmunityLevel,
++ ofdmPhyErrRate,
++ aniState->ofdmTrigLow,
++ aniState->cckNoiseImmunityLevel,
++ cckPhyErrRate,
++ aniState->cckTrigLow);
++ ath9k_hw_ani_lower_immunity(ah);
++ aniState->ofdmsTurn = !aniState->ofdmsTurn;
++ }
++ ath_print(common, ATH_DBG_ANI,
++ "1 listenTime=%d ofdm=%d/s cck=%d/s - "
++ "calling ath9k_ani_restart_new()\n",
++ aniState->listenTime, ofdmPhyErrRate, cckPhyErrRate);
++ ath9k_ani_restart_new(ah);
++ } else if (aniState->listenTime > ah->aniperiod) {
++ /* check to see if need to raise immunity */
++ if (ofdmPhyErrRate > aniState->ofdmTrigHigh &&
++ (cckPhyErrRate <= aniState->cckTrigHigh ||
++ aniState->ofdmsTurn)) {
++ ath_print(common, ATH_DBG_ANI,
++ "2 listenTime=%d OFDM:%d errs=%d/s(>%d) -> "
++ "ath9k_hw_ani_ofdm_err_trigger_new()\n",
++ aniState->listenTime,
++ aniState->ofdmNoiseImmunityLevel,
++ ofdmPhyErrRate,
++ aniState->ofdmTrigHigh);
++ ath9k_hw_ani_ofdm_err_trigger_new(ah);
++ ath9k_ani_restart_new(ah);
++ aniState->ofdmsTurn = false;
++ } else if (cckPhyErrRate > aniState->cckTrigHigh) {
++ ath_print(common, ATH_DBG_ANI,
++ "3 listenTime=%d CCK:%d errs=%d/s(>%d) -> "
++ "ath9k_hw_ani_cck_err_trigger_new()\n",
++ aniState->listenTime,
++ aniState->cckNoiseImmunityLevel,
++ cckPhyErrRate,
++ aniState->cckTrigHigh);
++ ath9k_hw_ani_cck_err_trigger_new(ah);
++ ath9k_ani_restart_new(ah);
++ aniState->ofdmsTurn = true;
+ }
+ }
+ }
+@@ -626,14 +1135,52 @@ static void ath9k_hw_proc_mib_event_old(struct ath_hw *ah)
+ * check will never be true.
+ */
+ if (aniState->ofdmPhyErrCount > aniState->ofdmTrigHigh)
+- ath9k_hw_ani_ofdm_err_trigger(ah);
++ ath9k_hw_ani_ofdm_err_trigger_new(ah);
+ if (aniState->cckPhyErrCount > aniState->cckTrigHigh)
+- ath9k_hw_ani_cck_err_trigger(ah);
++ ath9k_hw_ani_cck_err_trigger_old(ah);
+ /* NB: always restart to insure the h/w counters are reset */
+- ath9k_ani_restart(ah);
++ ath9k_ani_restart_old(ah);
+ }
+ }
+
++/*
++ * Process a MIB interrupt. We may potentially be invoked because
++ * any of the MIB counters overflow/trigger so don't assume we're
++ * here because a PHY error counter triggered.
++ */
++static void ath9k_hw_proc_mib_event_new(struct ath_hw *ah)
++{
++ u32 phyCnt1, phyCnt2;
++
++ /* Reset these counters regardless */
++ REG_WRITE(ah, AR_FILT_OFDM, 0);
++ REG_WRITE(ah, AR_FILT_CCK, 0);
++ if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING))
++ REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
++
++ /* Clear the mib counters and save them in the stats */
++ ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
++
++ if (!DO_ANI(ah)) {
++ /*
++ * We must always clear the interrupt cause by
++ * resetting the phy error regs.
++ */
++ REG_WRITE(ah, AR_PHY_ERR_1, 0);
++ REG_WRITE(ah, AR_PHY_ERR_2, 0);
++ return;
++ }
++
++ /* NB: these are not reset-on-read */
++ phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
++ phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
++
++ /* NB: always restart to insure the h/w counters are reset */
++ if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
++ ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK))
++ ath9k_ani_restart_new(ah);
++}
++
+ void ath9k_hw_ani_setup(struct ath_hw *ah)
+ {
+ int i;
+@@ -660,22 +1207,70 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
+
+ memset(ah->ani, 0, sizeof(ah->ani));
+ for (i = 0; i < ARRAY_SIZE(ah->ani); i++) {
+- ah->ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH;
+- ah->ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW;
+- ah->ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH;
+- ah->ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW;
++ if (AR_SREV_9300_20_OR_LATER(ah) || modparam_force_new_ani) {
++ ah->ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH_NEW;
++ ah->ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW_NEW;
++
++ ah->ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH_NEW;
++ ah->ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW_NEW;
++
++ ah->ani[i].spurImmunityLevel =
++ ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
++
++ ah->ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
++
++ ah->ani[i].ofdmPhyErrBase = 0;
++ ah->ani[i].cckPhyErrBase = 0;
++
++ if (AR_SREV_9300_20_OR_LATER(ah))
++ ah->ani[i].mrcCCKOff =
++ !ATH9K_ANI_ENABLE_MRC_CCK;
++ else
++ ah->ani[i].mrcCCKOff = true;
++
++ ah->ani[i].ofdmsTurn = true;
++ } else {
++ ah->ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH_OLD;
++ ah->ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW_OLD;
++
++ ah->ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH_OLD;
++ ah->ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW_OLD;
++
++ ah->ani[i].spurImmunityLevel =
++ ATH9K_ANI_SPUR_IMMUNE_LVL_OLD;
++ ah->ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL_OLD;
++
++ ah->ani[i].ofdmPhyErrBase =
++ AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH_OLD;
++ ah->ani[i].cckPhyErrBase =
++ AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH_OLD;
++ ah->ani[i].cckWeakSigThreshold =
++ ATH9K_ANI_CCK_WEAK_SIG_THR;
++ }
++
+ ah->ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
+ ah->ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
+ ah->ani[i].ofdmWeakSigDetectOff =
+ !ATH9K_ANI_USE_OFDM_WEAK_SIG;
+- ah->ani[i].cckWeakSigThreshold =
+- ATH9K_ANI_CCK_WEAK_SIG_THR;
+- ah->ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
+- ah->ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
+- ah->ani[i].ofdmPhyErrBase =
+- AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH;
+- ah->ani[i].cckPhyErrBase =
+- AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH;
++ ah->ani[i].cckNoiseImmunityLevel = ATH9K_ANI_CCK_DEF_LEVEL;
++ }
++
++ /*
++ * since we expect some ongoing maintenance on the tables, let's sanity
++ * check here default level should not modify INI setting.
++ */
++ if (AR_SREV_9300_20_OR_LATER(ah) || modparam_force_new_ani) {
++ const struct ani_ofdm_level_entry *entry_ofdm;
++ const struct ani_cck_level_entry *entry_cck;
++
++ entry_ofdm = &ofdm_level_table[ATH9K_ANI_OFDM_DEF_LEVEL];
++ entry_cck = &cck_level_table[ATH9K_ANI_CCK_DEF_LEVEL];
++
++ ah->aniperiod = ATH9K_ANI_PERIOD_NEW;
++ ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL_NEW;
++ } else {
++ ah->aniperiod = ATH9K_ANI_PERIOD_OLD;
++ ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL_OLD;
+ }
+
+ ath_print(common, ATH_DBG_ANI,
+@@ -694,7 +1289,6 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
+
+ ath9k_enable_mib_counters(ah);
+
+- ah->aniperiod = ATH9K_ANI_PERIOD;
+ if (ah->config.enable_ani)
+ ah->proc_phyerr |= HAL_PROCESS_ANI;
+ }
+@@ -709,4 +1303,20 @@ void ath9k_hw_attach_ani_ops_old(struct ath_hw *ah)
+
+ ops->ani_proc_mib_event = ath9k_hw_proc_mib_event_old;
+ ops->ani_monitor = ath9k_hw_ani_monitor_old;
++
++ ath_print(ath9k_hw_common(ah), ATH_DBG_ANY, "Using ANI v1\n");
++}
++
++void ath9k_hw_attach_ani_ops_new(struct ath_hw *ah)
++{
++ struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
++ struct ath_hw_ops *ops = ath9k_hw_ops(ah);
++
++ priv_ops->ani_reset = ath9k_ani_reset_new;
++ priv_ops->ani_lower_immunity = ath9k_hw_ani_lower_immunity_new;
++
++ ops->ani_proc_mib_event = ath9k_hw_proc_mib_event_new;
++ ops->ani_monitor = ath9k_hw_ani_monitor_new;
++
++ ath_print(ath9k_hw_common(ah), ATH_DBG_ANY, "Using ANI v2\n");
+ }
+diff --git a/drivers/net/wireless/ath/ath9k/ani.h b/drivers/net/wireless/ath/ath9k/ani.h
+index 4631ab2..f4d0a4d 100644
+--- a/drivers/net/wireless/ath/ath9k/ani.h
++++ b/drivers/net/wireless/ath/ath9k/ani.h
+@@ -23,23 +23,55 @@
+
+ #define BEACON_RSSI(ahp) (ahp->stats.avgbrssi)
+
+-#define ATH9K_ANI_OFDM_TRIG_HIGH 500
+-#define ATH9K_ANI_OFDM_TRIG_LOW 200
+-#define ATH9K_ANI_CCK_TRIG_HIGH 200
+-#define ATH9K_ANI_CCK_TRIG_LOW 100
++/* units are errors per second */
++#define ATH9K_ANI_OFDM_TRIG_HIGH_OLD 500
++#define ATH9K_ANI_OFDM_TRIG_HIGH_NEW 1000
++
++/* units are errors per second */
++#define ATH9K_ANI_OFDM_TRIG_LOW_OLD 200
++#define ATH9K_ANI_OFDM_TRIG_LOW_NEW 400
++
++/* units are errors per second */
++#define ATH9K_ANI_CCK_TRIG_HIGH_OLD 200
++#define ATH9K_ANI_CCK_TRIG_HIGH_NEW 600
++
++/* units are errors per second */
++#define ATH9K_ANI_CCK_TRIG_LOW_OLD 100
++#define ATH9K_ANI_CCK_TRIG_LOW_NEW 300
++
+ #define ATH9K_ANI_NOISE_IMMUNE_LVL 4
+ #define ATH9K_ANI_USE_OFDM_WEAK_SIG true
+ #define ATH9K_ANI_CCK_WEAK_SIG_THR false
+-#define ATH9K_ANI_SPUR_IMMUNE_LVL 7
+-#define ATH9K_ANI_FIRSTEP_LVL 0
++
++#define ATH9K_ANI_SPUR_IMMUNE_LVL_OLD 7
++#define ATH9K_ANI_SPUR_IMMUNE_LVL_NEW 3
++
++#define ATH9K_ANI_FIRSTEP_LVL_OLD 0
++#define ATH9K_ANI_FIRSTEP_LVL_NEW 2
++
+ #define ATH9K_ANI_RSSI_THR_HIGH 40
+ #define ATH9K_ANI_RSSI_THR_LOW 7
+-#define ATH9K_ANI_PERIOD 100
++
++#define ATH9K_ANI_PERIOD_OLD 100
++#define ATH9K_ANI_PERIOD_NEW 1000
++
++/* in ms */
++#define ATH9K_ANI_POLLINTERVAL_OLD 100
++#define ATH9K_ANI_POLLINTERVAL_NEW 1000
+
+ #define HAL_NOISE_IMMUNE_MAX 4
+ #define HAL_SPUR_IMMUNE_MAX 7
+ #define HAL_FIRST_STEP_MAX 2
+
++#define ATH9K_SIG_FIRSTEP_SETTING_MIN 0
++#define ATH9K_SIG_FIRSTEP_SETTING_MAX 20
++#define ATH9K_SIG_SPUR_IMM_SETTING_MIN 0
++#define ATH9K_SIG_SPUR_IMM_SETTING_MAX 22
++
++#define ATH9K_ANI_ENABLE_MRC_CCK true
++
++/* values here are relative to the INI */
++
+ enum ath9k_ani_cmd {
+ ATH9K_ANI_PRESENT = 0x1,
+ ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2,
+@@ -49,7 +81,8 @@ enum ath9k_ani_cmd {
+ ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20,
+ ATH9K_ANI_MODE = 0x40,
+ ATH9K_ANI_PHYERR_RESET = 0x80,
+- ATH9K_ANI_ALL = 0xff
++ ATH9K_ANI_MRC_CCK = 0x100,
++ ATH9K_ANI_ALL = 0xfff
+ };
+
+ struct ath9k_mib_stats {
+@@ -60,9 +93,31 @@ struct ath9k_mib_stats {
+ u32 beacons;
+ };
+
++/* INI default values for ANI registers */
++struct ath9k_ani_default {
++ u16 m1ThreshLow;
++ u16 m2ThreshLow;
++ u16 m1Thresh;
++ u16 m2Thresh;
++ u16 m2CountThr;
++ u16 m2CountThrLow;
++ u16 m1ThreshLowExt;
++ u16 m2ThreshLowExt;
++ u16 m1ThreshExt;
++ u16 m2ThreshExt;
++ u16 firstep;
++ u16 firstepLow;
++ u16 cycpwrThr1;
++ u16 cycpwrThr1Ext;
++};
++
+ struct ar5416AniState {
+ struct ath9k_channel *c;
+ u8 noiseImmunityLevel;
++ u8 ofdmNoiseImmunityLevel;
++ u8 cckNoiseImmunityLevel;
++ bool ofdmsTurn;
++ u8 mrcCCKOff;
+ u8 spurImmunityLevel;
+ u8 firstepLevel;
+ u8 ofdmWeakSigDetectOff;
+@@ -85,6 +140,7 @@ struct ar5416AniState {
+ int16_t pktRssi[2];
+ int16_t ofdmErrRssi[2];
+ int16_t cckErrRssi[2];
++ struct ath9k_ani_default iniDef;
+ };
+
+ struct ar5416Stats {
+@@ -114,5 +170,7 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah, u32 *rxc_pcnt,
+ u32 *rxf_pcnt, u32 *txf_pcnt);
+ void ath9k_hw_ani_setup(struct ath_hw *ah);
+ void ath9k_hw_ani_init(struct ath_hw *ah);
++int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
++ struct ath9k_channel *chan);
+
+ #endif /* ANI_H */
+diff --git a/drivers/net/wireless/ath/ath9k/ar5008_phy.c b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
+index cde411c..004cddd 100644
+--- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
++++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
+@@ -21,7 +21,30 @@
+ #include "../regd.h"
+ #include "ar9002_phy.h"
+
+-/* All code below is for non single-chip solutions */
++/* All code below is for AR5008, AR9001, AR9002 */
++
++static const int firstep_table[] =
++/* level: 0 1 2 3 4 5 6 7 8 */
++ { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
++
++static const int cycpwrThr1_table[] =
++/* level: 0 1 2 3 4 5 6 7 8 */
++ { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
++
++/*
++ * register values to turn OFDM weak signal detection OFF
++ */
++static const int m1ThreshLow_off = 127;
++static const int m2ThreshLow_off = 127;
++static const int m1Thresh_off = 127;
++static const int m2Thresh_off = 127;
++static const int m2CountThr_off = 31;
++static const int m2CountThrLow_off = 63;
++static const int m1ThreshLowExt_off = 127;
++static const int m2ThreshLowExt_off = 127;
++static const int m1ThreshExt_off = 127;
++static const int m2ThreshExt_off = 127;
++
+
+ /**
+ * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
+@@ -1028,8 +1051,9 @@ static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah,
+ return pll;
+ }
+
+-static bool ar5008_hw_ani_control(struct ath_hw *ah,
+- enum ath9k_ani_cmd cmd, int param)
++static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
++ enum ath9k_ani_cmd cmd,
++ int param)
+ {
+ struct ar5416AniState *aniState = ah->curani;
+ struct ath_common *common = ath9k_hw_common(ah);
+@@ -1211,6 +1235,265 @@ static bool ar5008_hw_ani_control(struct ath_hw *ah,
+ return true;
+ }
+
++static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
++ enum ath9k_ani_cmd cmd,
++ int param)
++{
++ struct ar5416AniState *aniState = ah->curani;
++ struct ath_common *common = ath9k_hw_common(ah);
++ struct ath9k_channel *chan = ah->curchan;
++ s32 value, value2;
++
++ switch (cmd & ah->ani_function) {
++ case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
++ /*
++ * on == 1 means ofdm weak signal detection is ON
++ * on == 1 is the default, for less noise immunity
++ *
++ * on == 0 means ofdm weak signal detection is OFF
++ * on == 0 means more noise imm
++ */
++ u32 on = param ? 1 : 0;
++ /*
++ * make register setting for default
++ * (weak sig detect ON) come from INI file
++ */
++ int m1ThreshLow = on ?
++ aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
++ int m2ThreshLow = on ?
++ aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
++ int m1Thresh = on ?
++ aniState->iniDef.m1Thresh : m1Thresh_off;
++ int m2Thresh = on ?
++ aniState->iniDef.m2Thresh : m2Thresh_off;
++ int m2CountThr = on ?
++ aniState->iniDef.m2CountThr : m2CountThr_off;
++ int m2CountThrLow = on ?
++ aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
++ int m1ThreshLowExt = on ?
++ aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
++ int m2ThreshLowExt = on ?
++ aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
++ int m1ThreshExt = on ?
++ aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
++ int m2ThreshExt = on ?
++ aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
++
++ REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
++ AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
++ m1ThreshLow);
++ REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
++ AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
++ m2ThreshLow);
++ REG_RMW_FIELD(ah, AR_PHY_SFCORR,
++ AR_PHY_SFCORR_M1_THRESH, m1Thresh);
++ REG_RMW_FIELD(ah, AR_PHY_SFCORR,
++ AR_PHY_SFCORR_M2_THRESH, m2Thresh);
++ REG_RMW_FIELD(ah, AR_PHY_SFCORR,
++ AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
++ REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
++ AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
++ m2CountThrLow);
++
++ REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
++ AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
++ REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
++ AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
++ REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
++ AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
++ REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
++ AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
++
++ if (on)
++ REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
++ AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
++ else
++ REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
++ AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
++
++ if (!on != aniState->ofdmWeakSigDetectOff) {
++ ath_print(common, ATH_DBG_ANI,
++ "** ch %d: ofdm weak signal: %s=>%s\n",
++ chan->channel,
++ !aniState->ofdmWeakSigDetectOff ?
++ "on" : "off",
++ on ? "on" : "off");
++ if (on)
++ ah->stats.ast_ani_ofdmon++;
++ else
++ ah->stats.ast_ani_ofdmoff++;
++ aniState->ofdmWeakSigDetectOff = !on;
++ }
++ break;
++ }
++ case ATH9K_ANI_FIRSTEP_LEVEL:{
++ u32 level = param;
++
++ if (level >= ARRAY_SIZE(firstep_table)) {
++ ath_print(common, ATH_DBG_ANI,
++ "ATH9K_ANI_FIRSTEP_LEVEL: level "
++ "out of range (%u > %u)\n",
++ level,
++ (unsigned) ARRAY_SIZE(firstep_table));
++ return false;
++ }
++
++ /*
++ * make register setting relative to default
++ * from INI file & cap value
++ */
++ value = firstep_table[level] -
++ firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
++ aniState->iniDef.firstep;
++ if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
++ value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
++ if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
++ value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
++ REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
++ AR_PHY_FIND_SIG_FIRSTEP,
++ value);
++ /*
++ * we need to set first step low register too
++ * make register setting relative to default
++ * from INI file & cap value
++ */
++ value2 = firstep_table[level] -
++ firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
++ aniState->iniDef.firstepLow;
++ if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
++ value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
++ if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
++ value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
++
++ REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
++ AR_PHY_FIND_SIG_FIRSTEP_LOW, value2);
++
++ if (level != aniState->firstepLevel) {
++ ath_print(common, ATH_DBG_ANI,
++ "** ch %d: level %d=>%d[def:%d] "
++ "firstep[level]=%d ini=%d\n",
++ chan->channel,
++ aniState->firstepLevel,
++ level,
++ ATH9K_ANI_FIRSTEP_LVL_NEW,
++ value,
++ aniState->iniDef.firstep);
++ ath_print(common, ATH_DBG_ANI,
++ "** ch %d: level %d=>%d[def:%d] "
++ "firstep_low[level]=%d ini=%d\n",
++ chan->channel,
++ aniState->firstepLevel,
++ level,
++ ATH9K_ANI_FIRSTEP_LVL_NEW,
++ value2,
++ aniState->iniDef.firstepLow);
++ if (level > aniState->firstepLevel)
++ ah->stats.ast_ani_stepup++;
++ else if (level < aniState->firstepLevel)
++ ah->stats.ast_ani_stepdown++;
++ aniState->firstepLevel = level;
++ }
++ break;
++ }
++ case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
++ u32 level = param;
++
++ if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
++ ath_print(common, ATH_DBG_ANI,
++ "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level "
++ "out of range (%u > %u)\n",
++ level,
++ (unsigned) ARRAY_SIZE(cycpwrThr1_table));
++ return false;
++ }
++ /*
++ * make register setting relative to default
++ * from INI file & cap value
++ */
++ value = cycpwrThr1_table[level] -
++ cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
++ aniState->iniDef.cycpwrThr1;
++ if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
++ value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
++ if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
++ value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
++ REG_RMW_FIELD(ah, AR_PHY_TIMING5,
++ AR_PHY_TIMING5_CYCPWR_THR1,
++ value);
++
++ /*
++ * set AR_PHY_EXT_CCA for extension channel
++ * make register setting relative to default
++ * from INI file & cap value
++ */
++ value2 = cycpwrThr1_table[level] -
++ cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
++ aniState->iniDef.cycpwrThr1Ext;
++ if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
++ value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
++ if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
++ value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
++ REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
++ AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2);
++
++ if (level != aniState->spurImmunityLevel) {
++ ath_print(common, ATH_DBG_ANI,
++ "** ch %d: level %d=>%d[def:%d] "
++ "cycpwrThr1[level]=%d ini=%d\n",
++ chan->channel,
++ aniState->spurImmunityLevel,
++ level,
++ ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
++ value,
++ aniState->iniDef.cycpwrThr1);
++ ath_print(common, ATH_DBG_ANI,
++ "** ch %d: level %d=>%d[def:%d] "
++ "cycpwrThr1Ext[level]=%d ini=%d\n",
++ chan->channel,
++ aniState->spurImmunityLevel,
++ level,
++ ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
++ value2,
++ aniState->iniDef.cycpwrThr1Ext);
++ if (level > aniState->spurImmunityLevel)
++ ah->stats.ast_ani_spurup++;
++ else if (level < aniState->spurImmunityLevel)
++ ah->stats.ast_ani_spurdown++;
++ aniState->spurImmunityLevel = level;
++ }
++ break;
++ }
++ case ATH9K_ANI_MRC_CCK:
++ /*
++ * You should not see this as AR5008, AR9001, AR9002
++ * does not have hardware support for MRC CCK.
++ */
++ WARN_ON(1);
++ break;
++ case ATH9K_ANI_PRESENT:
++ break;
++ default:
++ ath_print(common, ATH_DBG_ANI,
++ "invalid cmd %u\n", cmd);
++ return false;
++ }
++
++ ath_print(common, ATH_DBG_ANI,
++ "ANI parameters: SI=%d, ofdmWS=%s FS=%d "
++ "MRCcck=%s listenTime=%d CC=%d listen=%d "
++ "ofdmErrs=%d cckErrs=%d\n",
++ aniState->spurImmunityLevel,
++ !aniState->ofdmWeakSigDetectOff ? "on" : "off",
++ aniState->firstepLevel,
++ !aniState->mrcCCKOff ? "on" : "off",
++ aniState->listenTime,
++ aniState->cycleCount,
++ aniState->listenTime,
++ aniState->ofdmPhyErrCount,
++ aniState->cckPhyErrCount);
++ return true;
++}
++
+ static void ar5008_hw_do_getnf(struct ath_hw *ah,
+ int16_t nfarray[NUM_NF_READINGS])
+ {
+@@ -1331,6 +1614,71 @@ static void ar5008_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
+ DISABLE_REGWRITE_BUFFER(ah);
+ }
+
++/*
++ * Initialize the ANI register values with default (ini) values.
++ * This routine is called during a (full) hardware reset after
++ * all the registers are initialised from the INI.
++ */
++static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
++{
++ struct ar5416AniState *aniState;
++ struct ath_common *common = ath9k_hw_common(ah);
++ struct ath9k_channel *chan = ah->curchan;
++ struct ath9k_ani_default *iniDef;
++ int index;
++ u32 val;
++
++ index = ath9k_hw_get_ani_channel_idx(ah, chan);
++ aniState = &ah->ani[index];
++ ah->curani = aniState;
++ iniDef = &aniState->iniDef;
++
++ ath_print(common, ATH_DBG_ANI,
++ "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
++ ah->hw_version.macVersion,
++ ah->hw_version.macRev,
++ ah->opmode,
++ chan->channel,
++ chan->channelFlags);
++
++ val = REG_READ(ah, AR_PHY_SFCORR);
++ iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
++ iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
++ iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
++
++ val = REG_READ(ah, AR_PHY_SFCORR_LOW);
++ iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
++ iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
++ iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
++
++ val = REG_READ(ah, AR_PHY_SFCORR_EXT);
++ iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
++ iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
++ iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
++ iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
++ iniDef->firstep = REG_READ_FIELD(ah,
++ AR_PHY_FIND_SIG,
++ AR_PHY_FIND_SIG_FIRSTEP);
++ iniDef->firstepLow = REG_READ_FIELD(ah,
++ AR_PHY_FIND_SIG_LOW,
++ AR_PHY_FIND_SIG_FIRSTEP_LOW);
++ iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
++ AR_PHY_TIMING5,
++ AR_PHY_TIMING5_CYCPWR_THR1);
++ iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
++ AR_PHY_EXT_CCA,
++ AR_PHY_EXT_TIMING5_CYCPWR_THR1);
++
++ /* these levels just got reset to defaults by the INI */
++ aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
++ aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
++ aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
++ aniState->mrcCCKOff = true; /* not available on pre AR9003 */
++
++ aniState->cycleCount = 0;
++}
++
++
+ void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
+ {
+ struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
+@@ -1352,10 +1700,15 @@ void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
+ priv_ops->enable_rfkill = ar5008_hw_enable_rfkill;
+ priv_ops->restore_chainmask = ar5008_restore_chainmask;
+ priv_ops->set_diversity = ar5008_set_diversity;
+- priv_ops->ani_control = ar5008_hw_ani_control;
+ priv_ops->do_getnf = ar5008_hw_do_getnf;
+ priv_ops->loadnf = ar5008_hw_loadnf;
+
++ if (modparam_force_new_ani) {
++ priv_ops->ani_control = ar5008_hw_ani_control_new;
++ priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs;
++ } else
++ priv_ops->ani_control = ar5008_hw_ani_control_old;
++
+ if (AR_SREV_9100(ah))
+ priv_ops->compute_pll_control = ar9100_hw_compute_pll_control;
+ else if (AR_SREV_9160_10_OR_LATER(ah))
+diff --git a/drivers/net/wireless/ath/ath9k/ar9002_hw.c b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
+index 917eae0..0317ac9 100644
+--- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
++++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
+@@ -20,6 +20,10 @@
+ #include "ar9002_initvals.h"
+ #include "ar9002_phy.h"
+
++int modparam_force_new_ani;
++module_param_named(force_new_ani, modparam_force_new_ani, int, 0444);
++MODULE_PARM_DESC(nohwcrypt, "Force new ANI for AR5008, AR9001, AR9002");
++
+ /* General hardware code for the A5008/AR9001/AR9002 hadware families */
+
+ static bool ar9002_hw_macversion_supported(u32 macversion)
+@@ -637,5 +641,8 @@ void ar9002_hw_attach_ops(struct ath_hw *ah)
+ ar9002_hw_attach_calib_ops(ah);
+ ar9002_hw_attach_mac_ops(ah);
+
+- ath9k_hw_attach_ani_ops_old(ah);
++ if (modparam_force_new_ani)
++ ath9k_hw_attach_ani_ops_new(ah);
++ else
++ ath9k_hw_attach_ani_ops_old(ah);
+ }
+diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+index b757470..82c3ab7 100644
+--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+@@ -314,5 +314,5 @@ void ar9003_hw_attach_ops(struct ath_hw *ah)
+ ar9003_hw_attach_calib_ops(ah);
+ ar9003_hw_attach_mac_ops(ah);
+
+- ath9k_hw_attach_ani_ops_old(ah);
++ ath9k_hw_attach_ani_ops_new(ah);
+ }
+diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+index c714579..d5e6b08 100644
+--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+@@ -17,6 +17,28 @@
+ #include "hw.h"
+ #include "ar9003_phy.h"
+
++static const int firstep_table[] =
++/* level: 0 1 2 3 4 5 6 7 8 */
++ { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
++
++static const int cycpwrThr1_table[] =
++/* level: 0 1 2 3 4 5 6 7 8 */
++ { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
++
++/*
++ * register values to turn OFDM weak signal detection OFF
++ */
++static const int m1ThreshLow_off = 127;
++static const int m2ThreshLow_off = 127;
++static const int m1Thresh_off = 127;
++static const int m2Thresh_off = 127;
++static const int m2CountThr_off = 31;
++static const int m2CountThrLow_off = 63;
++static const int m1ThreshLowExt_off = 127;
++static const int m2ThreshLowExt_off = 127;
++static const int m1ThreshExt_off = 127;
++static const int m2ThreshExt_off = 127;
++
+ /**
+ * ar9003_hw_set_channel - set channel on single-chip device
+ * @ah: atheros hardware structure
+@@ -94,7 +116,7 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
+ }
+
+ /**
+- * ar9003_hw_spur_mitigate - convert baseband spur frequency
++ * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
+ * @ah: atheros hardware structure
+ * @chan:
+ *
+@@ -732,71 +754,68 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
+ {
+ struct ar5416AniState *aniState = ah->curani;
+ struct ath_common *common = ath9k_hw_common(ah);
++ struct ath9k_channel *chan = ah->curchan;
++ s32 value, value2;
+
+ switch (cmd & ah->ani_function) {
+- case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
+- u32 level = param;
+-
+- if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
+- ath_print(common, ATH_DBG_ANI,
+- "level out of range (%u > %u)\n",
+- level,
+- (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
+- return false;
+- }
+-
+- REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
+- AR_PHY_DESIRED_SZ_TOT_DES,
+- ah->totalSizeDesired[level]);
+- REG_RMW_FIELD(ah, AR_PHY_AGC,
+- AR_PHY_AGC_COARSE_LOW,
+- ah->coarse_low[level]);
+- REG_RMW_FIELD(ah, AR_PHY_AGC,
+- AR_PHY_AGC_COARSE_HIGH,
+- ah->coarse_high[level]);
+- REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
+- AR_PHY_FIND_SIG_FIRPWR, ah->firpwr[level]);
+-
+- if (level > aniState->noiseImmunityLevel)
+- ah->stats.ast_ani_niup++;
+- else if (level < aniState->noiseImmunityLevel)
+- ah->stats.ast_ani_nidown++;
+- aniState->noiseImmunityLevel = level;
+- break;
+- }
+ case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
+- const int m1ThreshLow[] = { 127, 50 };
+- const int m2ThreshLow[] = { 127, 40 };
+- const int m1Thresh[] = { 127, 0x4d };
+- const int m2Thresh[] = { 127, 0x40 };
+- const int m2CountThr[] = { 31, 16 };
+- const int m2CountThrLow[] = { 63, 48 };
++ /*
++ * on == 1 means ofdm weak signal detection is ON
++ * on == 1 is the default, for less noise immunity
++ *
++ * on == 0 means ofdm weak signal detection is OFF
++ * on == 0 means more noise imm
++ */
+ u32 on = param ? 1 : 0;
++ /*
++ * make register setting for default
++ * (weak sig detect ON) come from INI file
++ */
++ int m1ThreshLow = on ?
++ aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
++ int m2ThreshLow = on ?
++ aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
++ int m1Thresh = on ?
++ aniState->iniDef.m1Thresh : m1Thresh_off;
++ int m2Thresh = on ?
++ aniState->iniDef.m2Thresh : m2Thresh_off;
++ int m2CountThr = on ?
++ aniState->iniDef.m2CountThr : m2CountThr_off;
++ int m2CountThrLow = on ?
++ aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
++ int m1ThreshLowExt = on ?
++ aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
++ int m2ThreshLowExt = on ?
++ aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
++ int m1ThreshExt = on ?
++ aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
++ int m2ThreshExt = on ?
++ aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
+
+ REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
+ AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
+- m1ThreshLow[on]);
++ m1ThreshLow);
+ REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
+ AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
+- m2ThreshLow[on]);
++ m2ThreshLow);
+ REG_RMW_FIELD(ah, AR_PHY_SFCORR,
+- AR_PHY_SFCORR_M1_THRESH, m1Thresh[on]);
++ AR_PHY_SFCORR_M1_THRESH, m1Thresh);
+ REG_RMW_FIELD(ah, AR_PHY_SFCORR,
+- AR_PHY_SFCORR_M2_THRESH, m2Thresh[on]);
++ AR_PHY_SFCORR_M2_THRESH, m2Thresh);
+ REG_RMW_FIELD(ah, AR_PHY_SFCORR,
+- AR_PHY_SFCORR_M2COUNT_THR, m2CountThr[on]);
++ AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
+ REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
+ AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
+- m2CountThrLow[on]);
++ m2CountThrLow);
+
+ REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
+- AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLow[on]);
++ AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
+ REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
+- AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLow[on]);
++ AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
+ REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
+- AR_PHY_SFCORR_EXT_M1_THRESH, m1Thresh[on]);
++ AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
+ REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
+- AR_PHY_SFCORR_EXT_M2_THRESH, m2Thresh[on]);
++ AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
+
+ if (on)
+ REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
+@@ -806,6 +825,12 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
+ AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
+
+ if (!on != aniState->ofdmWeakSigDetectOff) {
++ ath_print(common, ATH_DBG_ANI,
++ "** ch %d: ofdm weak signal: %s=>%s\n",
++ chan->channel,
++ !aniState->ofdmWeakSigDetectOff ?
++ "on" : "off",
++ on ? "on" : "off");
+ if (on)
+ ah->stats.ast_ani_ofdmon++;
+ else
+@@ -814,64 +839,167 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
+ }
+ break;
+ }
+- case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
+- const int weakSigThrCck[] = { 8, 6 };
+- u32 high = param ? 1 : 0;
+-
+- REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
+- AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
+- weakSigThrCck[high]);
+- if (high != aniState->cckWeakSigThreshold) {
+- if (high)
+- ah->stats.ast_ani_cckhigh++;
+- else
+- ah->stats.ast_ani_ccklow++;
+- aniState->cckWeakSigThreshold = high;
+- }
+- break;
+- }
+ case ATH9K_ANI_FIRSTEP_LEVEL:{
+- const int firstep[] = { 0, 4, 8 };
+ u32 level = param;
+
+- if (level >= ARRAY_SIZE(firstep)) {
++ if (level >= ARRAY_SIZE(firstep_table)) {
+ ath_print(common, ATH_DBG_ANI,
+- "level out of range (%u > %u)\n",
++ "ATH9K_ANI_FIRSTEP_LEVEL: level "
++ "out of range (%u > %u)\n",
+ level,
+- (unsigned) ARRAY_SIZE(firstep));
++ (unsigned) ARRAY_SIZE(firstep_table));
+ return false;
+ }
++
++ /*
++ * make register setting relative to default
++ * from INI file & cap value
++ */
++ value = firstep_table[level] -
++ firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
++ aniState->iniDef.firstep;
++ if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
++ value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
++ if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
++ value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
+ REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
+ AR_PHY_FIND_SIG_FIRSTEP,
+- firstep[level]);
+- if (level > aniState->firstepLevel)
+- ah->stats.ast_ani_stepup++;
+- else if (level < aniState->firstepLevel)
+- ah->stats.ast_ani_stepdown++;
+- aniState->firstepLevel = level;
++ value);
++ /*
++ * we need to set first step low register too
++ * make register setting relative to default
++ * from INI file & cap value
++ */
++ value2 = firstep_table[level] -
++ firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
++ aniState->iniDef.firstepLow;
++ if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
++ value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
++ if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
++ value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
++
++ REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
++ AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
++
++ if (level != aniState->firstepLevel) {
++ ath_print(common, ATH_DBG_ANI,
++ "** ch %d: level %d=>%d[def:%d] "
++ "firstep[level]=%d ini=%d\n",
++ chan->channel,
++ aniState->firstepLevel,
++ level,
++ ATH9K_ANI_FIRSTEP_LVL_NEW,
++ value,
++ aniState->iniDef.firstep);
++ ath_print(common, ATH_DBG_ANI,
++ "** ch %d: level %d=>%d[def:%d] "
++ "firstep_low[level]=%d ini=%d\n",
++ chan->channel,
++ aniState->firstepLevel,
++ level,
++ ATH9K_ANI_FIRSTEP_LVL_NEW,
++ value2,
++ aniState->iniDef.firstepLow);
++ if (level > aniState->firstepLevel)
++ ah->stats.ast_ani_stepup++;
++ else if (level < aniState->firstepLevel)
++ ah->stats.ast_ani_stepdown++;
++ aniState->firstepLevel = level;
++ }
+ break;
+ }
+ case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
+- const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
+ u32 level = param;
+
+- if (level >= ARRAY_SIZE(cycpwrThr1)) {
++ if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
+ ath_print(common, ATH_DBG_ANI,
+- "level out of range (%u > %u)\n",
++ "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level "
++ "out of range (%u > %u)\n",
+ level,
+- (unsigned) ARRAY_SIZE(cycpwrThr1));
++ (unsigned) ARRAY_SIZE(cycpwrThr1_table));
+ return false;
+ }
++ /*
++ * make register setting relative to default
++ * from INI file & cap value
++ */
++ value = cycpwrThr1_table[level] -
++ cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
++ aniState->iniDef.cycpwrThr1;
++ if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
++ value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
++ if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
++ value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
+ REG_RMW_FIELD(ah, AR_PHY_TIMING5,
+ AR_PHY_TIMING5_CYCPWR_THR1,
+- cycpwrThr1[level]);
+- if (level > aniState->spurImmunityLevel)
+- ah->stats.ast_ani_spurup++;
+- else if (level < aniState->spurImmunityLevel)
+- ah->stats.ast_ani_spurdown++;
+- aniState->spurImmunityLevel = level;
++ value);
++
++ /*
++ * set AR_PHY_EXT_CCA for extension channel
++ * make register setting relative to default
++ * from INI file & cap value
++ */
++ value2 = cycpwrThr1_table[level] -
++ cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
++ aniState->iniDef.cycpwrThr1Ext;
++ if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
++ value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
++ if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
++ value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
++ REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
++ AR_PHY_EXT_CYCPWR_THR1, value2);
++
++ if (level != aniState->spurImmunityLevel) {
++ ath_print(common, ATH_DBG_ANI,
++ "** ch %d: level %d=>%d[def:%d] "
++ "cycpwrThr1[level]=%d ini=%d\n",
++ chan->channel,
++ aniState->spurImmunityLevel,
++ level,
++ ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
++ value,
++ aniState->iniDef.cycpwrThr1);
++ ath_print(common, ATH_DBG_ANI,
++ "** ch %d: level %d=>%d[def:%d] "
++ "cycpwrThr1Ext[level]=%d ini=%d\n",
++ chan->channel,
++ aniState->spurImmunityLevel,
++ level,
++ ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
++ value2,
++ aniState->iniDef.cycpwrThr1Ext);
++ if (level > aniState->spurImmunityLevel)
++ ah->stats.ast_ani_spurup++;
++ else if (level < aniState->spurImmunityLevel)
++ ah->stats.ast_ani_spurdown++;
++ aniState->spurImmunityLevel = level;
++ }
+ break;
+ }
++ case ATH9K_ANI_MRC_CCK:{
++ /*
++ * is_on == 1 means MRC CCK ON (default, less noise imm)
++ * is_on == 0 means MRC CCK is OFF (more noise imm)
++ */
++ bool is_on = param ? 1 : 0;
++ REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
++ AR_PHY_MRC_CCK_ENABLE, is_on);
++ REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
++ AR_PHY_MRC_CCK_MUX_REG, is_on);
++ if (!is_on != aniState->mrcCCKOff) {
++ ath_print(common, ATH_DBG_ANI,
++ "** ch %d: MRC CCK: %s=>%s\n",
++ chan->channel,
++ !aniState->mrcCCKOff ? "on" : "off",
++ is_on ? "on" : "off");
++ if (is_on)
++ ah->stats.ast_ani_ccklow++;
++ else
++ ah->stats.ast_ani_cckhigh++;
++ aniState->mrcCCKOff = !is_on;
++ }
++ break;
++ }
+ case ATH9K_ANI_PRESENT:
+ break;
+ default:
+@@ -880,25 +1008,19 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
+ return false;
+ }
+
+- ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
+ ath_print(common, ATH_DBG_ANI,
+- "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
+- "ofdmWeakSigDetectOff=%d\n",
+- aniState->noiseImmunityLevel,
++ "ANI parameters: SI=%d, ofdmWS=%s FS=%d "
++ "MRCcck=%s listenTime=%d CC=%d listen=%d "
++ "ofdmErrs=%d cckErrs=%d\n",
+ aniState->spurImmunityLevel,
+- !aniState->ofdmWeakSigDetectOff);
+- ath_print(common, ATH_DBG_ANI,
+- "cckWeakSigThreshold=%d, "
+- "firstepLevel=%d, listenTime=%d\n",
+- aniState->cckWeakSigThreshold,
++ !aniState->ofdmWeakSigDetectOff ? "on" : "off",
+ aniState->firstepLevel,
+- aniState->listenTime);
+- ath_print(common, ATH_DBG_ANI,
+- "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
+- aniState->cycleCount,
+- aniState->ofdmPhyErrCount,
+- aniState->cckPhyErrCount);
+-
++ !aniState->mrcCCKOff ? "on" : "off",
++ aniState->listenTime,
++ aniState->cycleCount,
++ aniState->listenTime,
++ aniState->ofdmPhyErrCount,
++ aniState->cckPhyErrCount);
+ return true;
+ }
+
+@@ -1111,6 +1233,70 @@ static void ar9003_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
+ }
+ }
+
++/*
++ * Initialize the ANI register values with default (ini) values.
++ * This routine is called during a (full) hardware reset after
++ * all the registers are initialised from the INI.
++ */
++static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
++{
++ struct ar5416AniState *aniState;
++ struct ath_common *common = ath9k_hw_common(ah);
++ struct ath9k_channel *chan = ah->curchan;
++ struct ath9k_ani_default *iniDef;
++ int index;
++ u32 val;
++
++ index = ath9k_hw_get_ani_channel_idx(ah, chan);
++ aniState = &ah->ani[index];
++ ah->curani = aniState;
++ iniDef = &aniState->iniDef;
++
++ ath_print(common, ATH_DBG_ANI,
++ "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
++ ah->hw_version.macVersion,
++ ah->hw_version.macRev,
++ ah->opmode,
++ chan->channel,
++ chan->channelFlags);
++
++ val = REG_READ(ah, AR_PHY_SFCORR);
++ iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
++ iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
++ iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
++
++ val = REG_READ(ah, AR_PHY_SFCORR_LOW);
++ iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
++ iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
++ iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
++
++ val = REG_READ(ah, AR_PHY_SFCORR_EXT);
++ iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
++ iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
++ iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
++ iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
++ iniDef->firstep = REG_READ_FIELD(ah,
++ AR_PHY_FIND_SIG,
++ AR_PHY_FIND_SIG_FIRSTEP);
++ iniDef->firstepLow = REG_READ_FIELD(ah,
++ AR_PHY_FIND_SIG_LOW,
++ AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
++ iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
++ AR_PHY_TIMING5,
++ AR_PHY_TIMING5_CYCPWR_THR1);
++ iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
++ AR_PHY_EXT_CCA,
++ AR_PHY_EXT_CYCPWR_THR1);
++
++ /* these levels just got reset to defaults by the INI */
++ aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
++ aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
++ aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
++ aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
++
++ aniState->cycleCount = 0;
++}
++
+ void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
+ {
+ struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
+@@ -1131,6 +1317,7 @@ void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
+ priv_ops->ani_control = ar9003_hw_ani_control;
+ priv_ops->do_getnf = ar9003_hw_do_getnf;
+ priv_ops->loadnf = ar9003_hw_loadnf;
++ priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
+ }
+
+ void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
+@@ -1251,3 +1438,4 @@ void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
+ "==== BB update: done ====\n\n");
+ }
+ EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
++
+diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
+index 82aca4b..c00946d 100644
+--- a/drivers/net/wireless/ath/ath9k/ath9k.h
++++ b/drivers/net/wireless/ath/ath9k/ath9k.h
+@@ -417,7 +417,8 @@ int ath_beaconq_config(struct ath_softc *sc);
+
+ #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */
+ #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */
+-#define ATH_ANI_POLLINTERVAL 100 /* 100 ms */
++#define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */
++#define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */
+ #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */
+ #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
+
+diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
+index 5f46861..739be8f 100644
+--- a/drivers/net/wireless/ath/ath9k/hw.c
++++ b/drivers/net/wireless/ath/ath9k/hw.c
+@@ -75,6 +75,15 @@ static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
+ ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
+ }
+
++static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
++{
++ /* You will not have this callback if using the old ANI */
++ if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
++ return;
++
++ ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
++}
++
+ /********************/
+ /* Helper Functions */
+ /********************/
+@@ -560,6 +569,8 @@ static int __ath9k_hw_init(struct ath_hw *ah)
+ ah->ani_function = ATH9K_ANI_ALL;
+ if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
+ ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
++ if (!AR_SREV_9300_20_OR_LATER(ah))
++ ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
+
+ ath9k_hw_init_mode_regs(ah);
+
+@@ -1360,6 +1371,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
+ ath9k_hw_resettxqueue(ah, i);
+
+ ath9k_hw_init_interrupt_masks(ah, ah->opmode);
++ ath9k_hw_ani_cache_ini_regs(ah);
+ ath9k_hw_init_qos(ah);
+
+ if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
+diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
+index 790a457..009f0fa 100644
+--- a/drivers/net/wireless/ath/ath9k/hw.h
++++ b/drivers/net/wireless/ath/ath9k/hw.h
+@@ -266,6 +266,7 @@ struct ath9k_ops_config {
+ int spurmode;
+ u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
+ u8 max_txtrig_level;
++ u16 ani_poll_interval; /* ANI poll interval in ms */
+ };
+
+ enum ath9k_int {
+@@ -520,6 +521,8 @@ struct ath_gen_timer_table {
+ * few dB more of noise immunity. If you have a strong time-varying
+ * interference that is causing false detections (OFDM timing errors or
+ * CCK timing errors) the level can be increased.
++ * @ani_cache_ini_regs: cache the values for ANI from the initial
++ * register settings through the register initialization.
+ */
+ struct ath_hw_private_ops {
+ /* Calibration ops */
+@@ -567,6 +570,7 @@ struct ath_hw_private_ops {
+ /* ANI */
+ void (*ani_reset)(struct ath_hw *ah, bool is_scanning);
+ void (*ani_lower_immunity)(struct ath_hw *ah);
++ void (*ani_cache_ini_regs)(struct ath_hw *ah);
+ };
+
+ /**
+@@ -959,9 +963,12 @@ void ar9003_hw_attach_ops(struct ath_hw *ah);
+ * ANI work can be shared between all families but a next
+ * generation implementation of ANI will be used only for AR9003 only
+ * for now as the other families still need to be tested with the same
+- * next generation ANI.
++ * next generation ANI. Feel free to start testing it though for the
++ * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
+ */
++extern int modparam_force_new_ani;
+ void ath9k_hw_attach_ani_ops_old(struct ath_hw *ah);
++void ath9k_hw_attach_ani_ops_new(struct ath_hw *ah);
+
+ #define ATH_PCIE_CAP_LINK_CTRL 0x70
+ #define ATH_PCIE_CAP_LINK_L0S 1
+diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
+index b8b76dd..846107c 100644
+--- a/drivers/net/wireless/ath/ath9k/main.c
++++ b/drivers/net/wireless/ath/ath9k/main.c
+@@ -285,7 +285,8 @@ void ath_ani_calibrate(unsigned long data)
+ }
+
+ /* Verify whether we must check ANI */
+- if ((timestamp - common->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
++ if ((timestamp - common->ani.checkani_timer) >=
++ ah->config.ani_poll_interval) {
+ aniflag = true;
+ common->ani.checkani_timer = timestamp;
+ }
+@@ -326,7 +327,8 @@ set_timer:
+ */
+ cal_interval = ATH_LONG_CALINTERVAL;
+ if (sc->sc_ah->config.enable_ani)
+- cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
++ cal_interval = min(cal_interval,
++ (u32)ah->config.ani_poll_interval);
+ if (!common->ani.caldone)
+ cal_interval = min(cal_interval, (u32)short_cal_interval);
+
+@@ -335,6 +337,7 @@ set_timer:
+
+ static void ath_start_ani(struct ath_common *common)
+ {
++ struct ath_hw *ah = common->ah;
+ unsigned long timestamp = jiffies_to_msecs(jiffies);
+
+ common->ani.longcal_timer = timestamp;
+@@ -342,7 +345,8 @@ static void ath_start_ani(struct ath_common *common)
+ common->ani.checkani_timer = timestamp;
+
+ mod_timer(&common->ani.timer,
+- jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
++ jiffies +
++ msecs_to_jiffies((u32)ah->config.ani_poll_interval));
+ }
+
+ /*
+--
+1.6.3.3
+
--- /dev/null
+From 8e23cc14343e68a8ba0db1f18ab9ee05cd17af4d Mon Sep 17 00:00:00 2001
+From: Luis R. Rodriguez <lrodriguez@atheros.com>
+Date: Thu, 10 Jun 2010 11:49:13 -0700
+Subject: [PATCH 08/24] ath9k_hw: enable ANI for AR9003
+
+AR9003 has been tested with the new ANI implementation
+and so ANI can now be enabled for that family.
+
+Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
+---
+ drivers/net/wireless/ath/ath9k/hw.c | 8 +-------
+ 1 files changed, 1 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
+index 739be8f..874c4e9 100644
+--- a/drivers/net/wireless/ath/ath9k/hw.c
++++ b/drivers/net/wireless/ath/ath9k/hw.c
+@@ -375,13 +375,7 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
+ ah->config.ofdm_trig_high = 500;
+ ah->config.cck_trig_high = 200;
+ ah->config.cck_trig_low = 100;
+-
+- /*
+- * For now ANI is disabled for AR9003, it is still
+- * being tested.
+- */
+- if (!AR_SREV_9300_20_OR_LATER(ah))
+- ah->config.enable_ani = 1;
++ ah->config.enable_ani = true;
+
+ for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
+ ah->config.spurchans[i][0] = AR_NO_SPUR;
+--
+1.6.3.3
+
--- /dev/null
+From e355a06db3ccfe85c9de2fae2a87603a5c242ee3 Mon Sep 17 00:00:00 2001
+From: Luis R. Rodriguez <lrodriguez@atheros.com>
+Date: Fri, 11 Jun 2010 10:42:07 -0700
+Subject: [PATCH 09/24] ath9k_hw: reduce delay on programming INI on AR9003
+
+All AR9003 devices are PCI-E only, the extra delay here
+is not required and only reduces the delay for loading
+the initial register values by at least 14ms.
+
+Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
+---
+ drivers/net/wireless/ath/ath9k/ar9003_phy.c | 9 ---------
+ 1 files changed, 0 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+index d5e6b08..27feb08 100644
+--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+@@ -543,15 +543,6 @@ static void ar9003_hw_prog_ini(struct ath_hw *ah,
+ u32 val = INI_RA(iniArr, i, column);
+
+ REG_WRITE(ah, reg, val);
+-
+- /*
+- * Determine if this is a shift register value, and insert the
+- * configured delay if so.
+- */
+- if (reg >= 0x16000 && reg < 0x17000
+- && ah->config.analog_shiftreg)
+- udelay(100);
+-
+ DO_DELAY(regWrites);
+ }
+ }
+--
+1.6.3.3
+
--- /dev/null
+From ac819e010d8f2fa03880e93fb98351b5a66a3886 Mon Sep 17 00:00:00 2001
+From: Luis R. Rodriguez <lrodriguez@atheros.com>
+Date: Fri, 11 Jun 2010 10:03:03 -0700
+Subject: [PATCH 10/24] ath9k_hw: update 5 GHz tx gain tables for femless and high power PA
+
+This updates the initvals for AR9003 to adjust the 5 GHz tx gain
+tables for femless and high power PA.
+
+References:
+
+ Osprey 2.0 header file ver 72
+ Osprey 2.2 header file ver 20
+
+Checksums:
+
+$ ./initvals -f ar9003-2p0
+0x00000000c2bfa7d5 ar9300_2p0_radio_postamble
+0x00000000ada2b114 ar9300Modes_lowest_ob_db_tx_gain_table_2p0
+0x00000000e0bc2c84 ar9300Modes_fast_clock_2p0
+0x00000000056eaf74 ar9300_2p0_radio_core
+0x0000000000000000 ar9300Common_rx_gain_table_merlin_2p0
+0x0000000078658fb5 ar9300_2p0_mac_postamble
+0x0000000023235333 ar9300_2p0_soc_postamble
+0x0000000054d41904 ar9200_merlin_2p0_radio_core
+0x00000000748572cf ar9300_2p0_baseband_postamble
+0x000000009aa5a0a4 ar9300_2p0_baseband_core
+0x000000003dffa526 ar9300Modes_high_power_tx_gain_table_2p0
+0x000000001cfda724 ar9300Modes_high_ob_db_tx_gain_table_2p0
+0x0000000011302700 ar9300Common_rx_gain_table_2p0
+0x00000000e3eab114 ar9300Modes_low_ob_db_tx_gain_table_2p0
+0x00000000c9d66d40 ar9300_2p0_mac_core
+0x000000001e1d0800 ar9300Common_wo_xlna_rx_gain_table_2p0
+0x00000000a0c54980 ar9300_2p0_soc_preamble
+0x00000000292e2544 ar9300PciePhy_pll_on_clkreq_disable_L1_2p0
+0x000000002d3e2544 ar9300PciePhy_clkreq_enable_L1_2p0
+0x00000000293e2544 ar9300PciePhy_clkreq_disable_L1_2p0
+
+$ ./initvals -f ar9003-2p2
+0x00000000c2bfa7d5 ar9300_2p2_radio_postamble
+0x00000000ada2b114 ar9300Modes_lowest_ob_db_tx_gain_table_2p2
+0x00000000e0bc2c84 ar9300Modes_fast_clock_2p2
+0x00000000056eaf74 ar9300_2p2_radio_core
+0x0000000000000000 ar9300Common_rx_gain_table_merlin_2p2
+0x0000000078658fb5 ar9300_2p2_mac_postamble
+0x0000000023235333 ar9300_2p2_soc_postamble
+0x0000000054d41904 ar9200_merlin_2p2_radio_core
+0x000000008475a084 ar9300_2p2_baseband_postamble
+0x000000009aaafd90 ar9300_2p2_baseband_core
+0x000000003dffa526 ar9300Modes_high_power_tx_gain_table_2p2
+0x000000001cfda724 ar9300Modes_high_ob_db_tx_gain_table_2p2
+0x0000000011302700 ar9300Common_rx_gain_table_2p2
+0x00000000a9a2b114 ar9300Modes_low_ob_db_tx_gain_table_2p2
+0x00000000a9d66d40 ar9300_2p2_mac_core
+0x000000001e1d0800 ar9300Common_wo_xlna_rx_gain_table_2p2
+0x00000000a0c531c8 ar9300_2p2_soc_preamble
+0x00000000292e2544 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2
+0x000000002d3e2544 ar9300PciePhy_clkreq_enable_L1_2p2
+0x00000000293e2544 ar9300PciePhy_clkreq_disable_L1_2p2
+
+Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
+---
+ .../net/wireless/ath/ath9k/ar9003_2p0_initvals.h | 248 ++++++++++----------
+ .../net/wireless/ath/ath9k/ar9003_2p2_initvals.h | 248 ++++++++++----------
+ 2 files changed, 248 insertions(+), 248 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath9k/ar9003_2p0_initvals.h b/drivers/net/wireless/ath/ath9k/ar9003_2p0_initvals.h
+index f82a00d..d3375fc 100644
+--- a/drivers/net/wireless/ath/ath9k/ar9003_2p0_initvals.h
++++ b/drivers/net/wireless/ath/ath9k/ar9003_2p0_initvals.h
+@@ -835,71 +835,71 @@ static const u32 ar9300_2p0_baseband_core[][2] = {
+
+ static const u32 ar9300Modes_high_power_tx_gain_table_2p0[][5] = {
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
++ {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
+ {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
+- {0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002},
+- {0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004},
+- {0x0000a50c, 0x0f022223, 0x0f022223, 0x0b000200, 0x0b000200},
+- {0x0000a510, 0x14022620, 0x14022620, 0x0f000202, 0x0f000202},
+- {0x0000a514, 0x18022622, 0x18022622, 0x11000400, 0x11000400},
+- {0x0000a518, 0x1b022822, 0x1b022822, 0x15000402, 0x15000402},
+- {0x0000a51c, 0x20022842, 0x20022842, 0x19000404, 0x19000404},
+- {0x0000a520, 0x22022c41, 0x22022c41, 0x1b000603, 0x1b000603},
+- {0x0000a524, 0x28023042, 0x28023042, 0x1f000a02, 0x1f000a02},
+- {0x0000a528, 0x2c023044, 0x2c023044, 0x23000a04, 0x23000a04},
+- {0x0000a52c, 0x2f023644, 0x2f023644, 0x26000a20, 0x26000a20},
+- {0x0000a530, 0x34025643, 0x34025643, 0x2a000e20, 0x2a000e20},
+- {0x0000a534, 0x38025a44, 0x38025a44, 0x2e000e22, 0x2e000e22},
+- {0x0000a538, 0x3b025e45, 0x3b025e45, 0x31000e24, 0x31000e24},
+- {0x0000a53c, 0x41025e4a, 0x41025e4a, 0x34001640, 0x34001640},
+- {0x0000a540, 0x48025e6c, 0x48025e6c, 0x38001660, 0x38001660},
+- {0x0000a544, 0x4e025e8e, 0x4e025e8e, 0x3b001861, 0x3b001861},
+- {0x0000a548, 0x53025eb2, 0x53025eb2, 0x3e001a81, 0x3e001a81},
++ {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
++ {0x0000a508, 0x09002421, 0x09002421, 0x08000004, 0x08000004},
++ {0x0000a50c, 0x0d002621, 0x0d002621, 0x0b000200, 0x0b000200},
++ {0x0000a510, 0x13004620, 0x13004620, 0x0f000202, 0x0f000202},
++ {0x0000a514, 0x19004a20, 0x19004a20, 0x11000400, 0x11000400},
++ {0x0000a518, 0x1d004e20, 0x1d004e20, 0x15000402, 0x15000402},
++ {0x0000a51c, 0x21005420, 0x21005420, 0x19000404, 0x19000404},
++ {0x0000a520, 0x26005e20, 0x26005e20, 0x1b000603, 0x1b000603},
++ {0x0000a524, 0x2b005e40, 0x2b005e40, 0x1f000a02, 0x1f000a02},
++ {0x0000a528, 0x2f005e42, 0x2f005e42, 0x23000a04, 0x23000a04},
++ {0x0000a52c, 0x33005e44, 0x33005e44, 0x26000a20, 0x26000a20},
++ {0x0000a530, 0x38005e65, 0x38005e65, 0x2a000e20, 0x2a000e20},
++ {0x0000a534, 0x3c005e69, 0x3c005e69, 0x2e000e22, 0x2e000e22},
++ {0x0000a538, 0x40005e6b, 0x40005e6b, 0x31000e24, 0x31000e24},
++ {0x0000a53c, 0x44005e6d, 0x44005e6d, 0x34001640, 0x34001640},
++ {0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660},
++ {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861},
++ {0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81},
+ {0x0000a54c, 0x59025eb5, 0x59025eb5, 0x42001a83, 0x42001a83},
+- {0x0000a550, 0x5f025ef6, 0x5f025ef6, 0x44001c84, 0x44001c84},
+- {0x0000a554, 0x62025f56, 0x62025f56, 0x48001ce3, 0x48001ce3},
+- {0x0000a558, 0x66027f56, 0x66027f56, 0x4c001ce5, 0x4c001ce5},
+- {0x0000a55c, 0x6a029f56, 0x6a029f56, 0x50001ce9, 0x50001ce9},
+- {0x0000a560, 0x70049f56, 0x70049f56, 0x54001ceb, 0x54001ceb},
+- {0x0000a564, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
+- {0x0000a568, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
+- {0x0000a56c, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
+- {0x0000a570, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
+- {0x0000a574, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
+- {0x0000a578, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
+- {0x0000a57c, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
++ {0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84},
++ {0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3},
++ {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5},
++ {0x0000a55c, 0x6b02bf14, 0x6b02bf14, 0x50001ce9, 0x50001ce9},
++ {0x0000a560, 0x6f02bf16, 0x6f02bf16, 0x54001ceb, 0x54001ceb},
++ {0x0000a564, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a568, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a56c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a570, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a574, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a578, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a57c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
+ {0x0000a580, 0x00802220, 0x00802220, 0x00800000, 0x00800000},
+- {0x0000a584, 0x06802223, 0x06802223, 0x04800002, 0x04800002},
+- {0x0000a588, 0x0a822220, 0x0a822220, 0x08800004, 0x08800004},
+- {0x0000a58c, 0x0f822223, 0x0f822223, 0x0b800200, 0x0b800200},
+- {0x0000a590, 0x14822620, 0x14822620, 0x0f800202, 0x0f800202},
+- {0x0000a594, 0x18822622, 0x18822622, 0x11800400, 0x11800400},
+- {0x0000a598, 0x1b822822, 0x1b822822, 0x15800402, 0x15800402},
+- {0x0000a59c, 0x20822842, 0x20822842, 0x19800404, 0x19800404},
+- {0x0000a5a0, 0x22822c41, 0x22822c41, 0x1b800603, 0x1b800603},
+- {0x0000a5a4, 0x28823042, 0x28823042, 0x1f800a02, 0x1f800a02},
+- {0x0000a5a8, 0x2c823044, 0x2c823044, 0x23800a04, 0x23800a04},
+- {0x0000a5ac, 0x2f823644, 0x2f823644, 0x26800a20, 0x26800a20},
+- {0x0000a5b0, 0x34825643, 0x34825643, 0x2a800e20, 0x2a800e20},
+- {0x0000a5b4, 0x38825a44, 0x38825a44, 0x2e800e22, 0x2e800e22},
+- {0x0000a5b8, 0x3b825e45, 0x3b825e45, 0x31800e24, 0x31800e24},
+- {0x0000a5bc, 0x41825e4a, 0x41825e4a, 0x34801640, 0x34801640},
+- {0x0000a5c0, 0x48825e6c, 0x48825e6c, 0x38801660, 0x38801660},
+- {0x0000a5c4, 0x4e825e8e, 0x4e825e8e, 0x3b801861, 0x3b801861},
+- {0x0000a5c8, 0x53825eb2, 0x53825eb2, 0x3e801a81, 0x3e801a81},
+- {0x0000a5cc, 0x59825eb5, 0x59825eb5, 0x42801a83, 0x42801a83},
+- {0x0000a5d0, 0x5f825ef6, 0x5f825ef6, 0x44801c84, 0x44801c84},
+- {0x0000a5d4, 0x62825f56, 0x62825f56, 0x48801ce3, 0x48801ce3},
+- {0x0000a5d8, 0x66827f56, 0x66827f56, 0x4c801ce5, 0x4c801ce5},
+- {0x0000a5dc, 0x6a829f56, 0x6a829f56, 0x50801ce9, 0x50801ce9},
+- {0x0000a5e0, 0x70849f56, 0x70849f56, 0x54801ceb, 0x54801ceb},
+- {0x0000a5e4, 0x7584ff56, 0x7584ff56, 0x56801eec, 0x56801eec},
+- {0x0000a5e8, 0x7584ff56, 0x7584ff56, 0x56801eec, 0x56801eec},
+- {0x0000a5ec, 0x7584ff56, 0x7584ff56, 0x56801eec, 0x56801eec},
+- {0x0000a5f0, 0x7584ff56, 0x7584ff56, 0x56801eec, 0x56801eec},
+- {0x0000a5f4, 0x7584ff56, 0x7584ff56, 0x56801eec, 0x56801eec},
+- {0x0000a5f8, 0x7584ff56, 0x7584ff56, 0x56801eec, 0x56801eec},
+- {0x0000a5fc, 0x7584ff56, 0x7584ff56, 0x56801eec, 0x56801eec},
++ {0x0000a584, 0x04802222, 0x04802222, 0x04800002, 0x04800002},
++ {0x0000a588, 0x09802421, 0x09802421, 0x08800004, 0x08800004},
++ {0x0000a58c, 0x0d802621, 0x0d802621, 0x0b800200, 0x0b800200},
++ {0x0000a590, 0x13804620, 0x13804620, 0x0f800202, 0x0f800202},
++ {0x0000a594, 0x19804a20, 0x19804a20, 0x11800400, 0x11800400},
++ {0x0000a598, 0x1d804e20, 0x1d804e20, 0x15800402, 0x15800402},
++ {0x0000a59c, 0x21805420, 0x21805420, 0x19800404, 0x19800404},
++ {0x0000a5a0, 0x26805e20, 0x26805e20, 0x1b800603, 0x1b800603},
++ {0x0000a5a4, 0x2b805e40, 0x2b805e40, 0x1f800a02, 0x1f800a02},
++ {0x0000a5a8, 0x2f805e42, 0x2f805e42, 0x23800a04, 0x23800a04},
++ {0x0000a5ac, 0x33805e44, 0x33805e44, 0x26800a20, 0x26800a20},
++ {0x0000a5b0, 0x38805e65, 0x38805e65, 0x2a800e20, 0x2a800e20},
++ {0x0000a5b4, 0x3c805e69, 0x3c805e69, 0x2e800e22, 0x2e800e22},
++ {0x0000a5b8, 0x40805e6b, 0x40805e6b, 0x31800e24, 0x31800e24},
++ {0x0000a5bc, 0x44805e6d, 0x44805e6d, 0x34801640, 0x34801640},
++ {0x0000a5c0, 0x49805e72, 0x49805e72, 0x38801660, 0x38801660},
++ {0x0000a5c4, 0x4e805eb2, 0x4e805eb2, 0x3b801861, 0x3b801861},
++ {0x0000a5c8, 0x53805f12, 0x53805f12, 0x3e801a81, 0x3e801a81},
++ {0x0000a5cc, 0x59825eb2, 0x59825eb2, 0x42801a83, 0x42801a83},
++ {0x0000a5d0, 0x5e825f12, 0x5e825f12, 0x44801c84, 0x44801c84},
++ {0x0000a5d4, 0x61827f12, 0x61827f12, 0x48801ce3, 0x48801ce3},
++ {0x0000a5d8, 0x6782bf12, 0x6782bf12, 0x4c801ce5, 0x4c801ce5},
++ {0x0000a5dc, 0x6b82bf14, 0x6b82bf14, 0x50801ce9, 0x50801ce9},
++ {0x0000a5e0, 0x6f82bf16, 0x6f82bf16, 0x54801ceb, 0x54801ceb},
++ {0x0000a5e4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5e8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5ec, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5f0, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
+ {0x00016044, 0x056db2e6, 0x056db2e6, 0x056db2e6, 0x056db2e6},
+ {0x00016048, 0xae480001, 0xae480001, 0xae480001, 0xae480001},
+ {0x00016068, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c},
+@@ -913,71 +913,71 @@ static const u32 ar9300Modes_high_power_tx_gain_table_2p0[][5] = {
+
+ static const u32 ar9300Modes_high_ob_db_tx_gain_table_2p0[][5] = {
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
++ {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
+ {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
+- {0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002},
+- {0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004},
+- {0x0000a50c, 0x0f022223, 0x0f022223, 0x0b000200, 0x0b000200},
+- {0x0000a510, 0x14022620, 0x14022620, 0x0f000202, 0x0f000202},
+- {0x0000a514, 0x18022622, 0x18022622, 0x11000400, 0x11000400},
+- {0x0000a518, 0x1b022822, 0x1b022822, 0x15000402, 0x15000402},
+- {0x0000a51c, 0x20022842, 0x20022842, 0x19000404, 0x19000404},
+- {0x0000a520, 0x22022c41, 0x22022c41, 0x1b000603, 0x1b000603},
+- {0x0000a524, 0x28023042, 0x28023042, 0x1f000a02, 0x1f000a02},
+- {0x0000a528, 0x2c023044, 0x2c023044, 0x23000a04, 0x23000a04},
+- {0x0000a52c, 0x2f023644, 0x2f023644, 0x26000a20, 0x26000a20},
+- {0x0000a530, 0x34025643, 0x34025643, 0x2a000e20, 0x2a000e20},
+- {0x0000a534, 0x38025a44, 0x38025a44, 0x2e000e22, 0x2e000e22},
+- {0x0000a538, 0x3b025e45, 0x3b025e45, 0x31000e24, 0x31000e24},
+- {0x0000a53c, 0x41025e4a, 0x41025e4a, 0x34001640, 0x34001640},
+- {0x0000a540, 0x48025e6c, 0x48025e6c, 0x38001660, 0x38001660},
+- {0x0000a544, 0x4e025e8e, 0x4e025e8e, 0x3b001861, 0x3b001861},
+- {0x0000a548, 0x53025eb2, 0x53025eb2, 0x3e001a81, 0x3e001a81},
++ {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
++ {0x0000a508, 0x09002421, 0x09002421, 0x08000004, 0x08000004},
++ {0x0000a50c, 0x0d002621, 0x0d002621, 0x0b000200, 0x0b000200},
++ {0x0000a510, 0x13004620, 0x13004620, 0x0f000202, 0x0f000202},
++ {0x0000a514, 0x19004a20, 0x19004a20, 0x11000400, 0x11000400},
++ {0x0000a518, 0x1d004e20, 0x1d004e20, 0x15000402, 0x15000402},
++ {0x0000a51c, 0x21005420, 0x21005420, 0x19000404, 0x19000404},
++ {0x0000a520, 0x26005e20, 0x26005e20, 0x1b000603, 0x1b000603},
++ {0x0000a524, 0x2b005e40, 0x2b005e40, 0x1f000a02, 0x1f000a02},
++ {0x0000a528, 0x2f005e42, 0x2f005e42, 0x23000a04, 0x23000a04},
++ {0x0000a52c, 0x33005e44, 0x33005e44, 0x26000a20, 0x26000a20},
++ {0x0000a530, 0x38005e65, 0x38005e65, 0x2a000e20, 0x2a000e20},
++ {0x0000a534, 0x3c005e69, 0x3c005e69, 0x2e000e22, 0x2e000e22},
++ {0x0000a538, 0x40005e6b, 0x40005e6b, 0x31000e24, 0x31000e24},
++ {0x0000a53c, 0x44005e6d, 0x44005e6d, 0x34001640, 0x34001640},
++ {0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660},
++ {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861},
++ {0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81},
+ {0x0000a54c, 0x59025eb5, 0x59025eb5, 0x42001a83, 0x42001a83},
+- {0x0000a550, 0x5f025ef6, 0x5f025ef6, 0x44001c84, 0x44001c84},
+- {0x0000a554, 0x62025f56, 0x62025f56, 0x48001ce3, 0x48001ce3},
+- {0x0000a558, 0x66027f56, 0x66027f56, 0x4c001ce5, 0x4c001ce5},
+- {0x0000a55c, 0x6a029f56, 0x6a029f56, 0x50001ce9, 0x50001ce9},
+- {0x0000a560, 0x70049f56, 0x70049f56, 0x54001ceb, 0x54001ceb},
+- {0x0000a564, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
+- {0x0000a568, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
+- {0x0000a56c, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
+- {0x0000a570, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
+- {0x0000a574, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
+- {0x0000a578, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
+- {0x0000a57c, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
++ {0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84},
++ {0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3},
++ {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5},
++ {0x0000a55c, 0x6b02bf14, 0x6b02bf14, 0x50001ce9, 0x50001ce9},
++ {0x0000a560, 0x6f02bf16, 0x6f02bf16, 0x54001ceb, 0x54001ceb},
++ {0x0000a564, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a568, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a56c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a570, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a574, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a578, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a57c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
+ {0x0000a580, 0x00802220, 0x00802220, 0x00800000, 0x00800000},
+- {0x0000a584, 0x06802223, 0x06802223, 0x04800002, 0x04800002},
+- {0x0000a588, 0x0a822220, 0x0a822220, 0x08800004, 0x08800004},
+- {0x0000a58c, 0x0f822223, 0x0f822223, 0x0b800200, 0x0b800200},
+- {0x0000a590, 0x14822620, 0x14822620, 0x0f800202, 0x0f800202},
+- {0x0000a594, 0x18822622, 0x18822622, 0x11800400, 0x11800400},
+- {0x0000a598, 0x1b822822, 0x1b822822, 0x15800402, 0x15800402},
+- {0x0000a59c, 0x20822842, 0x20822842, 0x19800404, 0x19800404},
+- {0x0000a5a0, 0x22822c41, 0x22822c41, 0x1b800603, 0x1b800603},
+- {0x0000a5a4, 0x28823042, 0x28823042, 0x1f800a02, 0x1f800a02},
+- {0x0000a5a8, 0x2c823044, 0x2c823044, 0x23800a04, 0x23800a04},
+- {0x0000a5ac, 0x2f823644, 0x2f823644, 0x26800a20, 0x26800a20},
+- {0x0000a5b0, 0x34825643, 0x34825643, 0x2a800e20, 0x2a800e20},
+- {0x0000a5b4, 0x38825a44, 0x38825a44, 0x2e800e22, 0x2e800e22},
+- {0x0000a5b8, 0x3b825e45, 0x3b825e45, 0x31800e24, 0x31800e24},
+- {0x0000a5bc, 0x41825e4a, 0x41825e4a, 0x34801640, 0x34801640},
+- {0x0000a5c0, 0x48825e6c, 0x48825e6c, 0x38801660, 0x38801660},
+- {0x0000a5c4, 0x4e825e8e, 0x4e825e8e, 0x3b801861, 0x3b801861},
+- {0x0000a5c8, 0x53825eb2, 0x53825eb2, 0x3e801a81, 0x3e801a81},
+- {0x0000a5cc, 0x59825eb5, 0x59825eb5, 0x42801a83, 0x42801a83},
+- {0x0000a5d0, 0x5f825ef6, 0x5f825ef6, 0x44801c84, 0x44801c84},
+- {0x0000a5d4, 0x62825f56, 0x62825f56, 0x48801ce3, 0x48801ce3},
+- {0x0000a5d8, 0x66827f56, 0x66827f56, 0x4c801ce5, 0x4c801ce5},
+- {0x0000a5dc, 0x6a829f56, 0x6a829f56, 0x50801ce9, 0x50801ce9},
+- {0x0000a5e0, 0x70849f56, 0x70849f56, 0x54801ceb, 0x54801ceb},
+- {0x0000a5e4, 0x7584ff56, 0x7584ff56, 0x56801eec, 0x56801eec},
+- {0x0000a5e8, 0x7584ff56, 0x7584ff56, 0x56801eec, 0x56801eec},
+- {0x0000a5ec, 0x7584ff56, 0x7584ff56, 0x56801eec, 0x56801eec},
+- {0x0000a5f0, 0x7584ff56, 0x7584ff56, 0x56801eec, 0x56801eec},
+- {0x0000a5f4, 0x7584ff56, 0x7584ff56, 0x56801eec, 0x56801eec},
+- {0x0000a5f8, 0x7584ff56, 0x7584ff56, 0x56801eec, 0x56801eec},
+- {0x0000a5fc, 0x7584ff56, 0x7584ff56, 0x56801eec, 0x56801eec},
++ {0x0000a584, 0x04802222, 0x04802222, 0x04800002, 0x04800002},
++ {0x0000a588, 0x09802421, 0x09802421, 0x08800004, 0x08800004},
++ {0x0000a58c, 0x0d802621, 0x0d802621, 0x0b800200, 0x0b800200},
++ {0x0000a590, 0x13804620, 0x13804620, 0x0f800202, 0x0f800202},
++ {0x0000a594, 0x19804a20, 0x19804a20, 0x11800400, 0x11800400},
++ {0x0000a598, 0x1d804e20, 0x1d804e20, 0x15800402, 0x15800402},
++ {0x0000a59c, 0x21805420, 0x21805420, 0x19800404, 0x19800404},
++ {0x0000a5a0, 0x26805e20, 0x26805e20, 0x1b800603, 0x1b800603},
++ {0x0000a5a4, 0x2b805e40, 0x2b805e40, 0x1f800a02, 0x1f800a02},
++ {0x0000a5a8, 0x2f805e42, 0x2f805e42, 0x23800a04, 0x23800a04},
++ {0x0000a5ac, 0x33805e44, 0x33805e44, 0x26800a20, 0x26800a20},
++ {0x0000a5b0, 0x38805e65, 0x38805e65, 0x2a800e20, 0x2a800e20},
++ {0x0000a5b4, 0x3c805e69, 0x3c805e69, 0x2e800e22, 0x2e800e22},
++ {0x0000a5b8, 0x40805e6b, 0x40805e6b, 0x31800e24, 0x31800e24},
++ {0x0000a5bc, 0x44805e6d, 0x44805e6d, 0x34801640, 0x34801640},
++ {0x0000a5c0, 0x49805e72, 0x49805e72, 0x38801660, 0x38801660},
++ {0x0000a5c4, 0x4e805eb2, 0x4e805eb2, 0x3b801861, 0x3b801861},
++ {0x0000a5c8, 0x53805f12, 0x53805f12, 0x3e801a81, 0x3e801a81},
++ {0x0000a5cc, 0x59825eb2, 0x59825eb2, 0x42801a83, 0x42801a83},
++ {0x0000a5d0, 0x5e825f12, 0x5e825f12, 0x44801c84, 0x44801c84},
++ {0x0000a5d4, 0x61827f12, 0x61827f12, 0x48801ce3, 0x48801ce3},
++ {0x0000a5d8, 0x6782bf12, 0x6782bf12, 0x4c801ce5, 0x4c801ce5},
++ {0x0000a5dc, 0x6b82bf14, 0x6b82bf14, 0x50801ce9, 0x50801ce9},
++ {0x0000a5e0, 0x6f82bf16, 0x6f82bf16, 0x54801ceb, 0x54801ceb},
++ {0x0000a5e4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5e8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5ec, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5f0, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
+ {0x00016044, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
+ {0x00016048, 0x8e480001, 0x8e480001, 0x8e480001, 0x8e480001},
+ {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
+diff --git a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
+index 7451505..ec98ab5 100644
+--- a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
++++ b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
+@@ -835,71 +835,71 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
+
+ static const u32 ar9300Modes_high_power_tx_gain_table_2p2[][5] = {
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
++ {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
+ {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
+- {0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002},
+- {0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004},
+- {0x0000a50c, 0x0f022223, 0x0f022223, 0x0b000200, 0x0b000200},
+- {0x0000a510, 0x14022620, 0x14022620, 0x0f000202, 0x0f000202},
+- {0x0000a514, 0x18022622, 0x18022622, 0x11000400, 0x11000400},
+- {0x0000a518, 0x1b022822, 0x1b022822, 0x15000402, 0x15000402},
+- {0x0000a51c, 0x20022842, 0x20022842, 0x19000404, 0x19000404},
+- {0x0000a520, 0x22022c41, 0x22022c41, 0x1b000603, 0x1b000603},
+- {0x0000a524, 0x28023042, 0x28023042, 0x1f000a02, 0x1f000a02},
+- {0x0000a528, 0x2c023044, 0x2c023044, 0x23000a04, 0x23000a04},
+- {0x0000a52c, 0x2f023644, 0x2f023644, 0x26000a20, 0x26000a20},
+- {0x0000a530, 0x34025643, 0x34025643, 0x2a000e20, 0x2a000e20},
+- {0x0000a534, 0x38025a44, 0x38025a44, 0x2e000e22, 0x2e000e22},
+- {0x0000a538, 0x3b025e45, 0x3b025e45, 0x31000e24, 0x31000e24},
+- {0x0000a53c, 0x41025e4a, 0x41025e4a, 0x34001640, 0x34001640},
+- {0x0000a540, 0x48025e6c, 0x48025e6c, 0x38001660, 0x38001660},
+- {0x0000a544, 0x4e025e8e, 0x4e025e8e, 0x3b001861, 0x3b001861},
+- {0x0000a548, 0x53025eb2, 0x53025eb2, 0x3e001a81, 0x3e001a81},
++ {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
++ {0x0000a508, 0x09002421, 0x09002421, 0x08000004, 0x08000004},
++ {0x0000a50c, 0x0d002621, 0x0d002621, 0x0b000200, 0x0b000200},
++ {0x0000a510, 0x13004620, 0x13004620, 0x0f000202, 0x0f000202},
++ {0x0000a514, 0x19004a20, 0x19004a20, 0x11000400, 0x11000400},
++ {0x0000a518, 0x1d004e20, 0x1d004e20, 0x15000402, 0x15000402},
++ {0x0000a51c, 0x21005420, 0x21005420, 0x19000404, 0x19000404},
++ {0x0000a520, 0x26005e20, 0x26005e20, 0x1b000603, 0x1b000603},
++ {0x0000a524, 0x2b005e40, 0x2b005e40, 0x1f000a02, 0x1f000a02},
++ {0x0000a528, 0x2f005e42, 0x2f005e42, 0x23000a04, 0x23000a04},
++ {0x0000a52c, 0x33005e44, 0x33005e44, 0x26000a20, 0x26000a20},
++ {0x0000a530, 0x38005e65, 0x38005e65, 0x2a000e20, 0x2a000e20},
++ {0x0000a534, 0x3c005e69, 0x3c005e69, 0x2e000e22, 0x2e000e22},
++ {0x0000a538, 0x40005e6b, 0x40005e6b, 0x31000e24, 0x31000e24},
++ {0x0000a53c, 0x44005e6d, 0x44005e6d, 0x34001640, 0x34001640},
++ {0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660},
++ {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861},
++ {0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81},
+ {0x0000a54c, 0x59025eb5, 0x59025eb5, 0x42001a83, 0x42001a83},
+- {0x0000a550, 0x5f025ef6, 0x5f025ef6, 0x44001c84, 0x44001c84},
+- {0x0000a554, 0x62025f56, 0x62025f56, 0x48001ce3, 0x48001ce3},
+- {0x0000a558, 0x66027f56, 0x66027f56, 0x4c001ce5, 0x4c001ce5},
+- {0x0000a55c, 0x6a029f56, 0x6a029f56, 0x50001ce9, 0x50001ce9},
+- {0x0000a560, 0x70049f56, 0x70049f56, 0x54001ceb, 0x54001ceb},
+- {0x0000a564, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
+- {0x0000a568, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
+- {0x0000a56c, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
+- {0x0000a570, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
+- {0x0000a574, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
+- {0x0000a578, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
+- {0x0000a57c, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
++ {0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84},
++ {0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3},
++ {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5},
++ {0x0000a55c, 0x6b02bf14, 0x6b02bf14, 0x50001ce9, 0x50001ce9},
++ {0x0000a560, 0x6f02bf16, 0x6f02bf16, 0x54001ceb, 0x54001ceb},
++ {0x0000a564, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a568, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a56c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a570, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a574, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a578, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a57c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
+ {0x0000a580, 0x00802220, 0x00802220, 0x00800000, 0x00800000},
+- {0x0000a584, 0x06802223, 0x06802223, 0x04800002, 0x04800002},
+- {0x0000a588, 0x0a822220, 0x0a822220, 0x08800004, 0x08800004},
+- {0x0000a58c, 0x0f822223, 0x0f822223, 0x0b800200, 0x0b800200},
+- {0x0000a590, 0x14822620, 0x14822620, 0x0f800202, 0x0f800202},
+- {0x0000a594, 0x18822622, 0x18822622, 0x11800400, 0x11800400},
+- {0x0000a598, 0x1b822822, 0x1b822822, 0x15800402, 0x15800402},
+- {0x0000a59c, 0x20822842, 0x20822842, 0x19800404, 0x19800404},
+- {0x0000a5a0, 0x22822c41, 0x22822c41, 0x1b800603, 0x1b800603},
+- {0x0000a5a4, 0x28823042, 0x28823042, 0x1f800a02, 0x1f800a02},
+- {0x0000a5a8, 0x2c823044, 0x2c823044, 0x23800a04, 0x23800a04},
+- {0x0000a5ac, 0x2f823644, 0x2f823644, 0x26800a20, 0x26800a20},
+- {0x0000a5b0, 0x34825643, 0x34825643, 0x2a800e20, 0x2a800e20},
+- {0x0000a5b4, 0x38825a44, 0x38825a44, 0x2e800e22, 0x2e800e22},
+- {0x0000a5b8, 0x3b825e45, 0x3b825e45, 0x31800e24, 0x31800e24},
+- {0x0000a5bc, 0x41825e4a, 0x41825e4a, 0x34801640, 0x34801640},
+- {0x0000a5c0, 0x48825e6c, 0x48825e6c, 0x38801660, 0x38801660},
+- {0x0000a5c4, 0x4e825e8e, 0x4e825e8e, 0x3b801861, 0x3b801861},
+- {0x0000a5c8, 0x53825eb2, 0x53825eb2, 0x3e801a81, 0x3e801a81},
+- {0x0000a5cc, 0x59825eb5, 0x59825eb5, 0x42801a83, 0x42801a83},
+- {0x0000a5d0, 0x5f825ef6, 0x5f825ef6, 0x44801c84, 0x44801c84},
+- {0x0000a5d4, 0x62825f56, 0x62825f56, 0x48801ce3, 0x48801ce3},
+- {0x0000a5d8, 0x66827f56, 0x66827f56, 0x4c801ce5, 0x4c801ce5},
+- {0x0000a5dc, 0x6a829f56, 0x6a829f56, 0x50801ce9, 0x50801ce9},
+- {0x0000a5e0, 0x70849f56, 0x70849f56, 0x54801ceb, 0x54801ceb},
+- {0x0000a5e4, 0x7584ff56, 0x7584ff56, 0x56801eec, 0x56801eec},
+- {0x0000a5e8, 0x7584ff56, 0x7584ff56, 0x56801eec, 0x56801eec},
+- {0x0000a5ec, 0x7584ff56, 0x7584ff56, 0x56801eec, 0x56801eec},
+- {0x0000a5f0, 0x7584ff56, 0x7584ff56, 0x56801eec, 0x56801eec},
+- {0x0000a5f4, 0x7584ff56, 0x7584ff56, 0x56801eec, 0x56801eec},
+- {0x0000a5f8, 0x7584ff56, 0x7584ff56, 0x56801eec, 0x56801eec},
+- {0x0000a5fc, 0x7584ff56, 0x7584ff56, 0x56801eec, 0x56801eec},
++ {0x0000a584, 0x04802222, 0x04802222, 0x04800002, 0x04800002},
++ {0x0000a588, 0x09802421, 0x09802421, 0x08800004, 0x08800004},
++ {0x0000a58c, 0x0d802621, 0x0d802621, 0x0b800200, 0x0b800200},
++ {0x0000a590, 0x13804620, 0x13804620, 0x0f800202, 0x0f800202},
++ {0x0000a594, 0x19804a20, 0x19804a20, 0x11800400, 0x11800400},
++ {0x0000a598, 0x1d804e20, 0x1d804e20, 0x15800402, 0x15800402},
++ {0x0000a59c, 0x21805420, 0x21805420, 0x19800404, 0x19800404},
++ {0x0000a5a0, 0x26805e20, 0x26805e20, 0x1b800603, 0x1b800603},
++ {0x0000a5a4, 0x2b805e40, 0x2b805e40, 0x1f800a02, 0x1f800a02},
++ {0x0000a5a8, 0x2f805e42, 0x2f805e42, 0x23800a04, 0x23800a04},
++ {0x0000a5ac, 0x33805e44, 0x33805e44, 0x26800a20, 0x26800a20},
++ {0x0000a5b0, 0x38805e65, 0x38805e65, 0x2a800e20, 0x2a800e20},
++ {0x0000a5b4, 0x3c805e69, 0x3c805e69, 0x2e800e22, 0x2e800e22},
++ {0x0000a5b8, 0x40805e6b, 0x40805e6b, 0x31800e24, 0x31800e24},
++ {0x0000a5bc, 0x44805e6d, 0x44805e6d, 0x34801640, 0x34801640},
++ {0x0000a5c0, 0x49805e72, 0x49805e72, 0x38801660, 0x38801660},
++ {0x0000a5c4, 0x4e805eb2, 0x4e805eb2, 0x3b801861, 0x3b801861},
++ {0x0000a5c8, 0x53805f12, 0x53805f12, 0x3e801a81, 0x3e801a81},
++ {0x0000a5cc, 0x59825eb2, 0x59825eb2, 0x42801a83, 0x42801a83},
++ {0x0000a5d0, 0x5e825f12, 0x5e825f12, 0x44801c84, 0x44801c84},
++ {0x0000a5d4, 0x61827f12, 0x61827f12, 0x48801ce3, 0x48801ce3},
++ {0x0000a5d8, 0x6782bf12, 0x6782bf12, 0x4c801ce5, 0x4c801ce5},
++ {0x0000a5dc, 0x6b82bf14, 0x6b82bf14, 0x50801ce9, 0x50801ce9},
++ {0x0000a5e0, 0x6f82bf16, 0x6f82bf16, 0x54801ceb, 0x54801ceb},
++ {0x0000a5e4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5e8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5ec, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5f0, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
+ {0x00016044, 0x056db2e6, 0x056db2e6, 0x056db2e6, 0x056db2e6},
+ {0x00016048, 0xae480001, 0xae480001, 0xae480001, 0xae480001},
+ {0x00016068, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c},
+@@ -913,71 +913,71 @@ static const u32 ar9300Modes_high_power_tx_gain_table_2p2[][5] = {
+
+ static const u32 ar9300Modes_high_ob_db_tx_gain_table_2p2[][5] = {
+ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
+- {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
++ {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
+ {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
+- {0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002},
+- {0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004},
+- {0x0000a50c, 0x0f022223, 0x0f022223, 0x0b000200, 0x0b000200},
+- {0x0000a510, 0x14022620, 0x14022620, 0x0f000202, 0x0f000202},
+- {0x0000a514, 0x18022622, 0x18022622, 0x11000400, 0x11000400},
+- {0x0000a518, 0x1b022822, 0x1b022822, 0x15000402, 0x15000402},
+- {0x0000a51c, 0x20022842, 0x20022842, 0x19000404, 0x19000404},
+- {0x0000a520, 0x22022c41, 0x22022c41, 0x1b000603, 0x1b000603},
+- {0x0000a524, 0x28023042, 0x28023042, 0x1f000a02, 0x1f000a02},
+- {0x0000a528, 0x2c023044, 0x2c023044, 0x23000a04, 0x23000a04},
+- {0x0000a52c, 0x2f023644, 0x2f023644, 0x26000a20, 0x26000a20},
+- {0x0000a530, 0x34025643, 0x34025643, 0x2a000e20, 0x2a000e20},
+- {0x0000a534, 0x38025a44, 0x38025a44, 0x2e000e22, 0x2e000e22},
+- {0x0000a538, 0x3b025e45, 0x3b025e45, 0x31000e24, 0x31000e24},
+- {0x0000a53c, 0x41025e4a, 0x41025e4a, 0x34001640, 0x34001640},
+- {0x0000a540, 0x48025e6c, 0x48025e6c, 0x38001660, 0x38001660},
+- {0x0000a544, 0x4e025e8e, 0x4e025e8e, 0x3b001861, 0x3b001861},
+- {0x0000a548, 0x53025eb2, 0x53025eb2, 0x3e001a81, 0x3e001a81},
++ {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
++ {0x0000a508, 0x09002421, 0x09002421, 0x08000004, 0x08000004},
++ {0x0000a50c, 0x0d002621, 0x0d002621, 0x0b000200, 0x0b000200},
++ {0x0000a510, 0x13004620, 0x13004620, 0x0f000202, 0x0f000202},
++ {0x0000a514, 0x19004a20, 0x19004a20, 0x11000400, 0x11000400},
++ {0x0000a518, 0x1d004e20, 0x1d004e20, 0x15000402, 0x15000402},
++ {0x0000a51c, 0x21005420, 0x21005420, 0x19000404, 0x19000404},
++ {0x0000a520, 0x26005e20, 0x26005e20, 0x1b000603, 0x1b000603},
++ {0x0000a524, 0x2b005e40, 0x2b005e40, 0x1f000a02, 0x1f000a02},
++ {0x0000a528, 0x2f005e42, 0x2f005e42, 0x23000a04, 0x23000a04},
++ {0x0000a52c, 0x33005e44, 0x33005e44, 0x26000a20, 0x26000a20},
++ {0x0000a530, 0x38005e65, 0x38005e65, 0x2a000e20, 0x2a000e20},
++ {0x0000a534, 0x3c005e69, 0x3c005e69, 0x2e000e22, 0x2e000e22},
++ {0x0000a538, 0x40005e6b, 0x40005e6b, 0x31000e24, 0x31000e24},
++ {0x0000a53c, 0x44005e6d, 0x44005e6d, 0x34001640, 0x34001640},
++ {0x0000a540, 0x49005e72, 0x49005e72, 0x38001660, 0x38001660},
++ {0x0000a544, 0x4e005eb2, 0x4e005eb2, 0x3b001861, 0x3b001861},
++ {0x0000a548, 0x53005f12, 0x53005f12, 0x3e001a81, 0x3e001a81},
+ {0x0000a54c, 0x59025eb5, 0x59025eb5, 0x42001a83, 0x42001a83},
+- {0x0000a550, 0x5f025ef6, 0x5f025ef6, 0x44001c84, 0x44001c84},
+- {0x0000a554, 0x62025f56, 0x62025f56, 0x48001ce3, 0x48001ce3},
+- {0x0000a558, 0x66027f56, 0x66027f56, 0x4c001ce5, 0x4c001ce5},
+- {0x0000a55c, 0x6a029f56, 0x6a029f56, 0x50001ce9, 0x50001ce9},
+- {0x0000a560, 0x70049f56, 0x70049f56, 0x54001ceb, 0x54001ceb},
+- {0x0000a564, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
+- {0x0000a568, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
+- {0x0000a56c, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
+- {0x0000a570, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
+- {0x0000a574, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
+- {0x0000a578, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
+- {0x0000a57c, 0x7504ff56, 0x7504ff56, 0x56001eec, 0x56001eec},
++ {0x0000a550, 0x5e025f12, 0x5e025f12, 0x44001c84, 0x44001c84},
++ {0x0000a554, 0x61027f12, 0x61027f12, 0x48001ce3, 0x48001ce3},
++ {0x0000a558, 0x6702bf12, 0x6702bf12, 0x4c001ce5, 0x4c001ce5},
++ {0x0000a55c, 0x6b02bf14, 0x6b02bf14, 0x50001ce9, 0x50001ce9},
++ {0x0000a560, 0x6f02bf16, 0x6f02bf16, 0x54001ceb, 0x54001ceb},
++ {0x0000a564, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a568, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a56c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a570, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a574, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a578, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
++ {0x0000a57c, 0x6f02bf16, 0x6f02bf16, 0x56001eec, 0x56001eec},
+ {0x0000a580, 0x00802220, 0x00802220, 0x00800000, 0x00800000},
+- {0x0000a584, 0x06802223, 0x06802223, 0x04800002, 0x04800002},
+- {0x0000a588, 0x0a822220, 0x0a822220, 0x08800004, 0x08800004},
+- {0x0000a58c, 0x0f822223, 0x0f822223, 0x0b800200, 0x0b800200},
+- {0x0000a590, 0x14822620, 0x14822620, 0x0f800202, 0x0f800202},
+- {0x0000a594, 0x18822622, 0x18822622, 0x11800400, 0x11800400},
+- {0x0000a598, 0x1b822822, 0x1b822822, 0x15800402, 0x15800402},
+- {0x0000a59c, 0x20822842, 0x20822842, 0x19800404, 0x19800404},
+- {0x0000a5a0, 0x22822c41, 0x22822c41, 0x1b800603, 0x1b800603},
+- {0x0000a5a4, 0x28823042, 0x28823042, 0x1f800a02, 0x1f800a02},
+- {0x0000a5a8, 0x2c823044, 0x2c823044, 0x23800a04, 0x23800a04},
+- {0x0000a5ac, 0x2f823644, 0x2f823644, 0x26800a20, 0x26800a20},
+- {0x0000a5b0, 0x34825643, 0x34825643, 0x2a800e20, 0x2a800e20},
+- {0x0000a5b4, 0x38825a44, 0x38825a44, 0x2e800e22, 0x2e800e22},
+- {0x0000a5b8, 0x3b825e45, 0x3b825e45, 0x31800e24, 0x31800e24},
+- {0x0000a5bc, 0x41825e4a, 0x41825e4a, 0x34801640, 0x34801640},
+- {0x0000a5c0, 0x48825e6c, 0x48825e6c, 0x38801660, 0x38801660},
+- {0x0000a5c4, 0x4e825e8e, 0x4e825e8e, 0x3b801861, 0x3b801861},
+- {0x0000a5c8, 0x53825eb2, 0x53825eb2, 0x3e801a81, 0x3e801a81},
+- {0x0000a5cc, 0x59825eb5, 0x59825eb5, 0x42801a83, 0x42801a83},
+- {0x0000a5d0, 0x5f825ef6, 0x5f825ef6, 0x44801c84, 0x44801c84},
+- {0x0000a5d4, 0x62825f56, 0x62825f56, 0x48801ce3, 0x48801ce3},
+- {0x0000a5d8, 0x66827f56, 0x66827f56, 0x4c801ce5, 0x4c801ce5},
+- {0x0000a5dc, 0x6a829f56, 0x6a829f56, 0x50801ce9, 0x50801ce9},
+- {0x0000a5e0, 0x70849f56, 0x70849f56, 0x54801ceb, 0x54801ceb},
+- {0x0000a5e4, 0x7584ff56, 0x7584ff56, 0x56801eec, 0x56801eec},
+- {0x0000a5e8, 0x7584ff56, 0x7584ff56, 0x56801eec, 0x56801eec},
+- {0x0000a5ec, 0x7584ff56, 0x7584ff56, 0x56801eec, 0x56801eec},
+- {0x0000a5f0, 0x7584ff56, 0x7584ff56, 0x56801eec, 0x56801eec},
+- {0x0000a5f4, 0x7584ff56, 0x7584ff56, 0x56801eec, 0x56801eec},
+- {0x0000a5f8, 0x7584ff56, 0x7584ff56, 0x56801eec, 0x56801eec},
+- {0x0000a5fc, 0x7584ff56, 0x7584ff56, 0x56801eec, 0x56801eec},
++ {0x0000a584, 0x04802222, 0x04802222, 0x04800002, 0x04800002},
++ {0x0000a588, 0x09802421, 0x09802421, 0x08800004, 0x08800004},
++ {0x0000a58c, 0x0d802621, 0x0d802621, 0x0b800200, 0x0b800200},
++ {0x0000a590, 0x13804620, 0x13804620, 0x0f800202, 0x0f800202},
++ {0x0000a594, 0x19804a20, 0x19804a20, 0x11800400, 0x11800400},
++ {0x0000a598, 0x1d804e20, 0x1d804e20, 0x15800402, 0x15800402},
++ {0x0000a59c, 0x21805420, 0x21805420, 0x19800404, 0x19800404},
++ {0x0000a5a0, 0x26805e20, 0x26805e20, 0x1b800603, 0x1b800603},
++ {0x0000a5a4, 0x2b805e40, 0x2b805e40, 0x1f800a02, 0x1f800a02},
++ {0x0000a5a8, 0x2f805e42, 0x2f805e42, 0x23800a04, 0x23800a04},
++ {0x0000a5ac, 0x33805e44, 0x33805e44, 0x26800a20, 0x26800a20},
++ {0x0000a5b0, 0x38805e65, 0x38805e65, 0x2a800e20, 0x2a800e20},
++ {0x0000a5b4, 0x3c805e69, 0x3c805e69, 0x2e800e22, 0x2e800e22},
++ {0x0000a5b8, 0x40805e6b, 0x40805e6b, 0x31800e24, 0x31800e24},
++ {0x0000a5bc, 0x44805e6d, 0x44805e6d, 0x34801640, 0x34801640},
++ {0x0000a5c0, 0x49805e72, 0x49805e72, 0x38801660, 0x38801660},
++ {0x0000a5c4, 0x4e805eb2, 0x4e805eb2, 0x3b801861, 0x3b801861},
++ {0x0000a5c8, 0x53805f12, 0x53805f12, 0x3e801a81, 0x3e801a81},
++ {0x0000a5cc, 0x59825eb2, 0x59825eb2, 0x42801a83, 0x42801a83},
++ {0x0000a5d0, 0x5e825f12, 0x5e825f12, 0x44801c84, 0x44801c84},
++ {0x0000a5d4, 0x61827f12, 0x61827f12, 0x48801ce3, 0x48801ce3},
++ {0x0000a5d8, 0x6782bf12, 0x6782bf12, 0x4c801ce5, 0x4c801ce5},
++ {0x0000a5dc, 0x6b82bf14, 0x6b82bf14, 0x50801ce9, 0x50801ce9},
++ {0x0000a5e0, 0x6f82bf16, 0x6f82bf16, 0x54801ceb, 0x54801ceb},
++ {0x0000a5e4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5e8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5ec, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5f0, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5f4, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5f8, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
++ {0x0000a5fc, 0x6f82bf16, 0x6f82bf16, 0x56801eec, 0x56801eec},
+ {0x00016044, 0x056db2e4, 0x056db2e4, 0x056db2e4, 0x056db2e4},
+ {0x00016048, 0x8e480001, 0x8e480001, 0x8e480001, 0x8e480001},
+ {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
+--
+1.6.3.3
+
--- /dev/null
+From 9e40641690f0f140bf4c4793c95ad65aba16f9db Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@openwrt.org>
+Date: Thu, 10 Jun 2010 23:58:38 +0200
+Subject: [PATCH 11/24] ath9k: fix mac80211 queue lookup for waking up queues
+
+ath_get_mac80211_qnum() expects the queue 'subtype'
+(internal ID for the WMM AC) as argument when looking up
+the mac80211 queue, however ath_wake_mac80211_queue provides
+txq->axq_qnum instead, which contains the hardware queue
+number. Fix this by keeping track of the WMM class ID in
+the txq data structure.
+
+Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+Cc: stable@kernel.org
+---
+ drivers/net/wireless/ath/ath9k/ath9k.h | 1 +
+ drivers/net/wireless/ath/ath9k/xmit.c | 3 ++-
+ 2 files changed, 3 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
+index c00946d..c5c6629 100644
+--- a/drivers/net/wireless/ath/ath9k/ath9k.h
++++ b/drivers/net/wireless/ath/ath9k/ath9k.h
+@@ -194,6 +194,7 @@ enum ATH_AGGR_STATUS {
+
+ #define ATH_TXFIFO_DEPTH 8
+ struct ath_txq {
++ int axq_class;
+ u32 axq_qnum;
+ u32 *axq_link;
+ struct list_head axq_q;
+diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
+index 7547c8f..ec124fb 100644
+--- a/drivers/net/wireless/ath/ath9k/xmit.c
++++ b/drivers/net/wireless/ath/ath9k/xmit.c
+@@ -941,6 +941,7 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
+ if (!ATH_TXQ_SETUP(sc, qnum)) {
+ struct ath_txq *txq = &sc->tx.txq[qnum];
+
++ txq->axq_class = subtype;
+ txq->axq_qnum = qnum;
+ txq->axq_link = NULL;
+ INIT_LIST_HEAD(&txq->axq_q);
+@@ -2047,7 +2048,7 @@ static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
+
+ spin_lock_bh(&txq->axq_lock);
+ if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
+- qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
++ qnum = ath_get_mac80211_qnum(txq->axq_class, sc);
+ if (qnum != -1) {
+ ath_mac80211_start_queue(sc, qnum);
+ txq->stopped = 0;
+--
+1.6.3.3
+
--- /dev/null
+From 70e4cc4634f21d946d09e8f1ba960016e65f3501 Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@openwrt.org>
+Date: Tue, 1 Jun 2010 23:48:34 +0200
+Subject: [PATCH 12/24] ath9k_htc: use common WMM AC definitions instead of ath9k ones
+
+Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+---
+ drivers/net/wireless/ath/ath9k/htc.h | 5 ++---
+ drivers/net/wireless/ath/ath9k/htc_drv_beacon.c | 2 +-
+ drivers/net/wireless/ath/ath9k/htc_drv_init.c | 8 ++++----
+ drivers/net/wireless/ath/ath9k/htc_drv_main.c | 2 +-
+ drivers/net/wireless/ath/ath9k/htc_drv_txrx.c | 13 ++++++-------
+ 5 files changed, 14 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath9k/htc.h b/drivers/net/wireless/ath/ath9k/htc.h
+index 051b8d8..c584fbd 100644
+--- a/drivers/net/wireless/ath/ath9k/htc.h
++++ b/drivers/net/wireless/ath/ath9k/htc.h
+@@ -398,7 +398,7 @@ struct ath9k_htc_priv {
+
+ int beaconq;
+ int cabq;
+- int hwq_map[ATH9K_WME_AC_VO+1];
++ int hwq_map[WME_NUM_AC];
+
+ #ifdef CONFIG_ATH9K_HTC_DEBUGFS
+ struct ath9k_debug debug;
+@@ -431,8 +431,7 @@ int ath9k_tx_init(struct ath9k_htc_priv *priv);
+ void ath9k_tx_tasklet(unsigned long data);
+ int ath9k_htc_tx_start(struct ath9k_htc_priv *priv, struct sk_buff *skb);
+ void ath9k_tx_cleanup(struct ath9k_htc_priv *priv);
+-bool ath9k_htc_txq_setup(struct ath9k_htc_priv *priv,
+- enum ath9k_tx_queue_subtype qtype);
++bool ath9k_htc_txq_setup(struct ath9k_htc_priv *priv, int subtype);
+ int ath9k_htc_cabq_setup(struct ath9k_htc_priv *priv);
+ int get_hw_qnum(u16 queue, int *hwq_map);
+ int ath_htc_txq_update(struct ath9k_htc_priv *priv, int qnum,
+diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
+index 12a3bb0..bd1506e 100644
+--- a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
++++ b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
+@@ -227,7 +227,7 @@ void ath9k_htc_beaconq_config(struct ath9k_htc_priv *priv)
+ {
+ struct ath_hw *ah = priv->ah;
+ struct ath9k_tx_queue_info qi, qi_be;
+- int qnum = priv->hwq_map[ATH9K_WME_AC_BE];
++ int qnum = priv->hwq_map[WME_AC_BE];
+
+ memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
+ memset(&qi_be, 0, sizeof(struct ath9k_tx_queue_info));
+diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_init.c b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
+index 7339439..947de70 100644
+--- a/drivers/net/wireless/ath/ath9k/htc_drv_init.c
++++ b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
+@@ -521,23 +521,23 @@ static int ath9k_init_queues(struct ath9k_htc_priv *priv)
+ goto err;
+ }
+
+- if (!ath9k_htc_txq_setup(priv, ATH9K_WME_AC_BE)) {
++ if (!ath9k_htc_txq_setup(priv, WME_AC_BE)) {
+ ath_print(common, ATH_DBG_FATAL,
+ "Unable to setup xmit queue for BE traffic\n");
+ goto err;
+ }
+
+- if (!ath9k_htc_txq_setup(priv, ATH9K_WME_AC_BK)) {
++ if (!ath9k_htc_txq_setup(priv, WME_AC_BK)) {
+ ath_print(common, ATH_DBG_FATAL,
+ "Unable to setup xmit queue for BK traffic\n");
+ goto err;
+ }
+- if (!ath9k_htc_txq_setup(priv, ATH9K_WME_AC_VI)) {
++ if (!ath9k_htc_txq_setup(priv, WME_AC_VI)) {
+ ath_print(common, ATH_DBG_FATAL,
+ "Unable to setup xmit queue for VI traffic\n");
+ goto err;
+ }
+- if (!ath9k_htc_txq_setup(priv, ATH9K_WME_AC_VO)) {
++ if (!ath9k_htc_txq_setup(priv, WME_AC_VO)) {
+ ath_print(common, ATH_DBG_FATAL,
+ "Unable to setup xmit queue for VO traffic\n");
+ goto err;
+diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_main.c b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
+index 7aefbc6..c4d022a 100644
+--- a/drivers/net/wireless/ath/ath9k/htc_drv_main.c
++++ b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
+@@ -1590,7 +1590,7 @@ static int ath9k_htc_conf_tx(struct ieee80211_hw *hw, u16 queue,
+ }
+
+ if ((priv->ah->opmode == NL80211_IFTYPE_ADHOC) &&
+- (qnum == priv->hwq_map[ATH9K_WME_AC_BE]))
++ (qnum == priv->hwq_map[WME_AC_BE]))
+ ath9k_htc_beaconq_config(priv);
+ out:
+ ath9k_htc_ps_restore(priv);
+diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
+index ffebd5a..89d81ab 100644
+--- a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
++++ b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
+@@ -34,15 +34,15 @@ int get_hw_qnum(u16 queue, int *hwq_map)
+ {
+ switch (queue) {
+ case 0:
+- return hwq_map[ATH9K_WME_AC_VO];
++ return hwq_map[WME_AC_VO];
+ case 1:
+- return hwq_map[ATH9K_WME_AC_VI];
++ return hwq_map[WME_AC_VI];
+ case 2:
+- return hwq_map[ATH9K_WME_AC_BE];
++ return hwq_map[WME_AC_BE];
+ case 3:
+- return hwq_map[ATH9K_WME_AC_BK];
++ return hwq_map[WME_AC_BK];
+ default:
+- return hwq_map[ATH9K_WME_AC_BE];
++ return hwq_map[WME_AC_BE];
+ }
+ }
+
+@@ -297,8 +297,7 @@ void ath9k_tx_cleanup(struct ath9k_htc_priv *priv)
+
+ }
+
+-bool ath9k_htc_txq_setup(struct ath9k_htc_priv *priv,
+- enum ath9k_tx_queue_subtype subtype)
++bool ath9k_htc_txq_setup(struct ath9k_htc_priv *priv, int subtype)
+ {
+ struct ath_hw *ah = priv->ah;
+ struct ath_common *common = ath9k_hw_common(ah);
+--
+1.6.3.3
+
--- /dev/null
+From 7524638b4b5740a9bd8fea768a4541ffb782cd1b Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@openwrt.org>
+Date: Tue, 1 Jun 2010 23:48:12 +0200
+Subject: [PATCH 13/24] ath9k: remove duplicate WMM AC definitions
+
+Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+---
+ drivers/net/wireless/ath/ath9k/ath9k.h | 4 +--
+ drivers/net/wireless/ath/ath9k/beacon.c | 3 +-
+ drivers/net/wireless/ath/ath9k/debug.c | 8 ++--
+ drivers/net/wireless/ath/ath9k/init.c | 10 +++---
+ drivers/net/wireless/ath/ath9k/mac.h | 11 ++-----
+ drivers/net/wireless/ath/ath9k/main.c | 20 ++++++------
+ drivers/net/wireless/ath/ath9k/virtual.c | 2 +-
+ drivers/net/wireless/ath/ath9k/xmit.c | 46 +-----------------------------
+ 8 files changed, 26 insertions(+), 78 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
+index c5c6629..a0f1567 100644
+--- a/drivers/net/wireless/ath/ath9k/ath9k.h
++++ b/drivers/net/wireless/ath/ath9k/ath9k.h
+@@ -291,7 +291,7 @@ struct ath_tx_control {
+ struct ath_tx {
+ u16 seq_no;
+ u32 txqsetup;
+- int hwq_map[ATH9K_WME_AC_VO+1];
++ int hwq_map[WME_NUM_AC];
+ spinlock_t txbuflock;
+ struct list_head txbuf;
+ struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
+@@ -680,8 +680,6 @@ void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle);
+ void ath_mac80211_stop_queue(struct ath_softc *sc, u16 skb_queue);
+ void ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue);
+
+-int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
+-
+ void ath_start_rfkill_poll(struct ath_softc *sc);
+ extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
+
+diff --git a/drivers/net/wireless/ath/ath9k/beacon.c b/drivers/net/wireless/ath/ath9k/beacon.c
+index f43d85a..4d4b22d 100644
+--- a/drivers/net/wireless/ath/ath9k/beacon.c
++++ b/drivers/net/wireless/ath/ath9k/beacon.c
+@@ -38,8 +38,7 @@ int ath_beaconq_config(struct ath_softc *sc)
+ qi.tqi_cwmax = 0;
+ } else {
+ /* Adhoc mode; important thing is to use 2x cwmin. */
+- qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA,
+- ATH9K_WME_AC_BE);
++ qnum = sc->tx.hwq_map[WME_AC_BE];
+ ath9k_hw_get_txq_props(ah, qnum, &qi_be);
+ qi.tqi_aifs = qi_be.tqi_aifs;
+ qi.tqi_cwmin = 4*qi_be.tqi_cwmin;
+diff --git a/drivers/net/wireless/ath/ath9k/debug.c b/drivers/net/wireless/ath/ath9k/debug.c
+index a127bdb..a6cb48d 100644
+--- a/drivers/net/wireless/ath/ath9k/debug.c
++++ b/drivers/net/wireless/ath/ath9k/debug.c
+@@ -630,10 +630,10 @@ static const struct file_operations fops_wiphy = {
+ do { \
+ len += snprintf(buf + len, size - len, \
+ "%s%13u%11u%10u%10u\n", str, \
+- sc->debug.stats.txstats[sc->tx.hwq_map[ATH9K_WME_AC_BE]].elem, \
+- sc->debug.stats.txstats[sc->tx.hwq_map[ATH9K_WME_AC_BK]].elem, \
+- sc->debug.stats.txstats[sc->tx.hwq_map[ATH9K_WME_AC_VI]].elem, \
+- sc->debug.stats.txstats[sc->tx.hwq_map[ATH9K_WME_AC_VO]].elem); \
++ sc->debug.stats.txstats[sc->tx.hwq_map[WME_AC_BE]].elem, \
++ sc->debug.stats.txstats[sc->tx.hwq_map[WME_AC_BK]].elem, \
++ sc->debug.stats.txstats[sc->tx.hwq_map[WME_AC_VI]].elem, \
++ sc->debug.stats.txstats[sc->tx.hwq_map[WME_AC_VO]].elem); \
+ } while(0)
+
+ static ssize_t read_file_xmit(struct file *file, char __user *user_buf,
+diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
+index 18d76ed..4e07830 100644
+--- a/drivers/net/wireless/ath/ath9k/init.c
++++ b/drivers/net/wireless/ath/ath9k/init.c
+@@ -426,7 +426,7 @@ static int ath9k_init_btcoex(struct ath_softc *sc)
+ r = ath_init_btcoex_timer(sc);
+ if (r)
+ return -1;
+- qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
++ qnum = sc->tx.hwq_map[WME_AC_BE];
+ ath9k_hw_init_btcoex_hw(sc->sc_ah, qnum);
+ sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
+ break;
+@@ -463,23 +463,23 @@ static int ath9k_init_queues(struct ath_softc *sc)
+ sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
+ ath_cabq_update(sc);
+
+- if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
++ if (!ath_tx_setup(sc, WME_AC_BK)) {
+ ath_print(common, ATH_DBG_FATAL,
+ "Unable to setup xmit queue for BK traffic\n");
+ goto err;
+ }
+
+- if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
++ if (!ath_tx_setup(sc, WME_AC_BE)) {
+ ath_print(common, ATH_DBG_FATAL,
+ "Unable to setup xmit queue for BE traffic\n");
+ goto err;
+ }
+- if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
++ if (!ath_tx_setup(sc, WME_AC_VI)) {
+ ath_print(common, ATH_DBG_FATAL,
+ "Unable to setup xmit queue for VI traffic\n");
+ goto err;
+ }
+- if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
++ if (!ath_tx_setup(sc, WME_AC_VO)) {
+ ath_print(common, ATH_DBG_FATAL,
+ "Unable to setup xmit queue for VO traffic\n");
+ goto err;
+diff --git a/drivers/net/wireless/ath/ath9k/mac.h b/drivers/net/wireless/ath/ath9k/mac.h
+index 3c65c91..7559fb2 100644
+--- a/drivers/net/wireless/ath/ath9k/mac.h
++++ b/drivers/net/wireless/ath/ath9k/mac.h
+@@ -577,13 +577,8 @@ enum ath9k_tx_queue {
+
+ #define ATH9K_NUM_TX_QUEUES 10
+
+-enum ath9k_tx_queue_subtype {
+- ATH9K_WME_AC_BK = 0,
+- ATH9K_WME_AC_BE,
+- ATH9K_WME_AC_VI,
+- ATH9K_WME_AC_VO,
+- ATH9K_WME_UPSD
+-};
++/* Used as a queue subtype instead of a WMM AC */
++#define ATH9K_WME_UPSD 4
+
+ enum ath9k_tx_queue_flags {
+ TXQ_FLAG_TXOKINT_ENABLE = 0x0001,
+@@ -617,7 +612,7 @@ enum ath9k_pkt_type {
+ struct ath9k_tx_queue_info {
+ u32 tqi_ver;
+ enum ath9k_tx_queue tqi_type;
+- enum ath9k_tx_queue_subtype tqi_subtype;
++ int tqi_subtype;
+ enum ath9k_tx_queue_flags tqi_qflags;
+ u32 tqi_priority;
+ u32 tqi_aifs;
+diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
+index 846107c..200e390 100644
+--- a/drivers/net/wireless/ath/ath9k/main.c
++++ b/drivers/net/wireless/ath/ath9k/main.c
+@@ -814,19 +814,19 @@ int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
+
+ switch (queue) {
+ case 0:
+- qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
++ qnum = sc->tx.hwq_map[WME_AC_VO];
+ break;
+ case 1:
+- qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
++ qnum = sc->tx.hwq_map[WME_AC_VI];
+ break;
+ case 2:
+- qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
++ qnum = sc->tx.hwq_map[WME_AC_BE];
+ break;
+ case 3:
+- qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
++ qnum = sc->tx.hwq_map[WME_AC_BK];
+ break;
+ default:
+- qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
++ qnum = sc->tx.hwq_map[WME_AC_BE];
+ break;
+ }
+
+@@ -838,16 +838,16 @@ int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
+ int qnum;
+
+ switch (queue) {
+- case ATH9K_WME_AC_VO:
++ case WME_AC_VO:
+ qnum = 0;
+ break;
+- case ATH9K_WME_AC_VI:
++ case WME_AC_VI:
+ qnum = 1;
+ break;
+- case ATH9K_WME_AC_BE:
++ case WME_AC_BE:
+ qnum = 2;
+ break;
+- case ATH9K_WME_AC_BK:
++ case WME_AC_BK:
+ qnum = 3;
+ break;
+ default:
+@@ -1559,7 +1559,7 @@ static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
+ ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
+
+ if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
+- if ((qnum == sc->tx.hwq_map[ATH9K_WME_AC_BE]) && !ret)
++ if ((qnum == sc->tx.hwq_map[WME_AC_BE]) && !ret)
+ ath_beaconq_config(sc);
+
+ mutex_unlock(&sc->mutex);
+diff --git a/drivers/net/wireless/ath/ath9k/virtual.c b/drivers/net/wireless/ath/ath9k/virtual.c
+index 105ad40..89423ca 100644
+--- a/drivers/net/wireless/ath/ath9k/virtual.c
++++ b/drivers/net/wireless/ath/ath9k/virtual.c
+@@ -219,7 +219,7 @@ static int ath9k_send_nullfunc(struct ath_wiphy *aphy,
+ info->control.rates[1].idx = -1;
+
+ memset(&txctl, 0, sizeof(struct ath_tx_control));
+- txctl.txq = &sc->tx.txq[sc->tx.hwq_map[ATH9K_WME_AC_VO]];
++ txctl.txq = &sc->tx.txq[sc->tx.hwq_map[WME_AC_VO]];
+ txctl.frame_type = ps ? ATH9K_IFT_PAUSE : ATH9K_IFT_UNPAUSE;
+
+ if (ath_tx_start(aphy->hw, skb, &txctl) != 0)
+diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
+index ec124fb..9bff6c5 100644
+--- a/drivers/net/wireless/ath/ath9k/xmit.c
++++ b/drivers/net/wireless/ath/ath9k/xmit.c
+@@ -959,32 +959,6 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
+ return &sc->tx.txq[qnum];
+ }
+
+-int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
+-{
+- int qnum;
+-
+- switch (qtype) {
+- case ATH9K_TX_QUEUE_DATA:
+- if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
+- ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
+- "HAL AC %u out of range, max %zu!\n",
+- haltype, ARRAY_SIZE(sc->tx.hwq_map));
+- return -1;
+- }
+- qnum = sc->tx.hwq_map[haltype];
+- break;
+- case ATH9K_TX_QUEUE_BEACON:
+- qnum = sc->beacon.beaconq;
+- break;
+- case ATH9K_TX_QUEUE_CAB:
+- qnum = sc->beacon.cabq->axq_qnum;
+- break;
+- default:
+- qnum = -1;
+- }
+- return qnum;
+-}
+-
+ int ath_txq_update(struct ath_softc *sc, int qnum,
+ struct ath9k_tx_queue_info *qinfo)
+ {
+@@ -2423,26 +2397,8 @@ void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
+ for (acno = 0, ac = &an->ac[acno];
+ acno < WME_NUM_AC; acno++, ac++) {
+ ac->sched = false;
++ ac->qnum = sc->tx.hwq_map[acno];
+ INIT_LIST_HEAD(&ac->tid_q);
+-
+- switch (acno) {
+- case WME_AC_BE:
+- ac->qnum = ath_tx_get_qnum(sc,
+- ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
+- break;
+- case WME_AC_BK:
+- ac->qnum = ath_tx_get_qnum(sc,
+- ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
+- break;
+- case WME_AC_VI:
+- ac->qnum = ath_tx_get_qnum(sc,
+- ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
+- break;
+- case WME_AC_VO:
+- ac->qnum = ath_tx_get_qnum(sc,
+- ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
+- break;
+- }
+ }
+ }
+
+--
+1.6.3.3
+
--- /dev/null
+From bd6c2c1e1308086c7c3ee9cb6bfed97935075b3e Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@openwrt.org>
+Date: Wed, 2 Jun 2010 00:02:49 +0200
+Subject: [PATCH 14/24] ath9k: remove declarations of some nonexistant functions
+
+Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+---
+ drivers/net/wireless/ath/ath9k/ath9k.h | 2 --
+ 1 files changed, 0 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
+index a0f1567..6b5a26f 100644
+--- a/drivers/net/wireless/ath/ath9k/ath9k.h
++++ b/drivers/net/wireless/ath/ath9k/ath9k.h
+@@ -628,8 +628,6 @@ irqreturn_t ath_isr(int irq, void *dev);
+ int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
+ const struct ath_bus_ops *bus_ops);
+ void ath9k_deinit_device(struct ath_softc *sc);
+-const char *ath_mac_bb_name(u32 mac_bb_version);
+-const char *ath_rf_name(u16 rf_version);
+ void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
+ void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
+ struct ath9k_channel *ichan);
+--
+1.6.3.3
+
--- /dev/null
+From a55ad78bc802f5df3ecc13801a96d1d457b3ee0a Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@openwrt.org>
+Date: Wed, 2 Jun 2010 00:05:57 +0200
+Subject: [PATCH 15/24] ath9k: make ath_get_hal_qnum static
+
+Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+---
+ drivers/net/wireless/ath/ath9k/ath9k.h | 1 -
+ drivers/net/wireless/ath/ath9k/main.c | 2 +-
+ 2 files changed, 1 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
+index 6b5a26f..6aa8fa6 100644
+--- a/drivers/net/wireless/ath/ath9k/ath9k.h
++++ b/drivers/net/wireless/ath/ath9k/ath9k.h
+@@ -612,7 +612,6 @@ struct ath_wiphy {
+
+ void ath9k_tasklet(unsigned long data);
+ int ath_reset(struct ath_softc *sc, bool retry_tx);
+-int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
+ int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
+ int ath_cabq_update(struct ath_softc *);
+
+diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
+index 200e390..52ed4c8 100644
+--- a/drivers/net/wireless/ath/ath9k/main.c
++++ b/drivers/net/wireless/ath/ath9k/main.c
+@@ -808,7 +808,7 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
+ return r;
+ }
+
+-int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
++static int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
+ {
+ int qnum;
+
+--
+1.6.3.3
+
--- /dev/null
+From f6a1fe7f5f04d8ef6e84e32db9c052c3d17c1114 Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@openwrt.org>
+Date: Fri, 11 Jun 2010 16:23:22 +0200
+Subject: [PATCH 16/24] ath9k: fix extending the rx timestamp with the hardware TSF
+
+AR5416 and all newer chipsets use a 32 bit rx timestamp, so there
+is no need to keep the 15 bit timestamp extending logic around.
+
+This patch removes ath9k_hw_extend_tsf (replaced by a call to
+ath9k_hw_gettsf64), and reduces the frequency of TSF reads, which
+can improve performance in some cases.
+
+This change also has the side effect of making rx timestamps
+more accurate.
+
+Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+---
+ drivers/net/wireless/ath/ath9k/hw.c | 15 ---------------
+ drivers/net/wireless/ath/ath9k/hw.h | 1 -
+ drivers/net/wireless/ath/ath9k/recv.c | 17 ++++++++++++++---
+ 3 files changed, 14 insertions(+), 19 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
+index 874c4e9..1fa3fe7 100644
+--- a/drivers/net/wireless/ath/ath9k/hw.c
++++ b/drivers/net/wireless/ath/ath9k/hw.c
+@@ -2616,21 +2616,6 @@ void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
+ }
+ EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
+
+-/*
+- * Extend 15-bit time stamp from rx descriptor to
+- * a full 64-bit TSF using the current h/w TSF.
+-*/
+-u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
+-{
+- u64 tsf;
+-
+- tsf = ath9k_hw_gettsf64(ah);
+- if ((tsf & 0x7fff) < rstamp)
+- tsf -= 0x8000;
+- return (tsf & ~0x7fff) | rstamp;
+-}
+-EXPORT_SYMBOL(ath9k_hw_extend_tsf);
+-
+ void ath9k_hw_set11nmac2040(struct ath_hw *ah)
+ {
+ struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
+diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
+index 009f0fa..ba84ac7 100644
+--- a/drivers/net/wireless/ath/ath9k/hw.h
++++ b/drivers/net/wireless/ath/ath9k/hw.h
+@@ -894,7 +894,6 @@ u64 ath9k_hw_gettsf64(struct ath_hw *ah);
+ void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
+ void ath9k_hw_reset_tsf(struct ath_hw *ah);
+ void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
+-u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp);
+ void ath9k_hw_init_global_settings(struct ath_hw *ah);
+ void ath9k_hw_set11nmac2040(struct ath_hw *ah);
+ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
+diff --git a/drivers/net/wireless/ath/ath9k/recv.c b/drivers/net/wireless/ath/ath9k/recv.c
+index 5141cd8..78ef1ae 100644
+--- a/drivers/net/wireless/ath/ath9k/recv.c
++++ b/drivers/net/wireless/ath/ath9k/recv.c
+@@ -1002,8 +1002,6 @@ static int ath9k_rx_skb_preprocess(struct ath_common *common,
+ struct ieee80211_rx_status *rx_status,
+ bool *decrypt_error)
+ {
+- struct ath_hw *ah = common->ah;
+-
+ memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
+
+ /*
+@@ -1018,7 +1016,6 @@ static int ath9k_rx_skb_preprocess(struct ath_common *common,
+ if (ath9k_process_rate(common, hw, rx_stats, rx_status))
+ return -EINVAL;
+
+- rx_status->mactime = ath9k_hw_extend_tsf(ah, rx_stats->rs_tstamp);
+ rx_status->band = hw->conf.channel->band;
+ rx_status->freq = hw->conf.channel->center_freq;
+ rx_status->signal = ATH_DEFAULT_NOISE_FLOOR + rx_stats->rs_rssi;
+@@ -1100,6 +1097,8 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
+ bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
+ int dma_type;
+ u8 rx_status_len = ah->caps.rx_status_len;
++ u64 tsf = 0;
++ u32 tsf_lower = 0;
+
+ if (edma)
+ dma_type = DMA_BIDIRECTIONAL;
+@@ -1109,6 +1108,9 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
+ qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
+ spin_lock_bh(&sc->rx.rxbuflock);
+
++ tsf = ath9k_hw_gettsf64(ah);
++ tsf_lower = tsf & 0xffffffff;
++
+ do {
+ /* If handling rx interrupt and flush is in progress => exit */
+ if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
+@@ -1141,6 +1143,15 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
+ if (flush)
+ goto requeue;
+
++ rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp;
++ if (rs.rs_tstamp > tsf_lower &&
++ unlikely(rs.rs_tstamp - tsf_lower > 0x10000000))
++ rxs->mactime -= 0x100000000ULL;
++
++ if (rs.rs_tstamp < tsf_lower &&
++ unlikely(tsf_lower - rs.rs_tstamp > 0x10000000))
++ rxs->mactime += 0x100000000ULL;
++
+ retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs,
+ rxs, &decrypt_error);
+ if (retval)
+--
+1.6.3.3
+
--- /dev/null
+From 38bf688e571b4cfc813578bd4b4dd0de26703729 Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@openwrt.org>
+Date: Fri, 11 Jun 2010 00:51:56 +0200
+Subject: [PATCH 17/24] ath9k: fix queue stopping threshold
+
+ath9k tries to prevent WMM queue tx buffer starvation caused by
+traffic on different queues by limiting the number of pending frames
+in a tx queue (tracked in the ath_buf structure). This had a leak
+issue, because the a skb can be reassigned to a different ath_buf
+in the tx path, causing the pending frame counter to become inaccurate.
+
+To fix this, track the number of frames in an array in the softc,
+using the mac80211 queue mapping as index.
+
+Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+---
+ drivers/net/wireless/ath/ath9k/ath9k.h | 3 +-
+ drivers/net/wireless/ath/ath9k/xmit.c | 53 +++++++++++++++++--------------
+ 2 files changed, 30 insertions(+), 26 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
+index 6aa8fa6..1a19aea 100644
+--- a/drivers/net/wireless/ath/ath9k/ath9k.h
++++ b/drivers/net/wireless/ath/ath9k/ath9k.h
+@@ -207,7 +207,6 @@ struct ath_txq {
+ struct list_head txq_fifo_pending;
+ u8 txq_headidx;
+ u8 txq_tailidx;
+- int pending_frames;
+ };
+
+ struct ath_atx_ac {
+@@ -245,7 +244,6 @@ struct ath_buf {
+ struct ath_buf_state bf_state;
+ dma_addr_t bf_dmacontext;
+ struct ath_wiphy *aphy;
+- struct ath_txq *txq;
+ };
+
+ struct ath_atx_tid {
+@@ -296,6 +294,7 @@ struct ath_tx {
+ struct list_head txbuf;
+ struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
+ struct ath_descdma txdma;
++ int pending_frames[WME_NUM_AC];
+ };
+
+ struct ath_rx_edma {
+diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
+index 9bff6c5..875b8b4 100644
+--- a/drivers/net/wireless/ath/ath9k/xmit.c
++++ b/drivers/net/wireless/ath/ath9k/xmit.c
+@@ -1760,7 +1760,7 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
+ struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+ struct ath_txq *txq = txctl->txq;
+ struct ath_buf *bf;
+- int r;
++ int q, r;
+
+ bf = ath_tx_get_buffer(sc);
+ if (!bf) {
+@@ -1768,14 +1768,6 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
+ return -1;
+ }
+
+- bf->txq = txctl->txq;
+- spin_lock_bh(&bf->txq->axq_lock);
+- if (++bf->txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
+- ath_mac80211_stop_queue(sc, skb_get_queue_mapping(skb));
+- txq->stopped = 1;
+- }
+- spin_unlock_bh(&bf->txq->axq_lock);
+-
+ r = ath_tx_setup_buffer(hw, bf, skb, txctl);
+ if (unlikely(r)) {
+ ath_print(common, ATH_DBG_FATAL, "TX mem alloc failure\n");
+@@ -1796,6 +1788,17 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
+ return r;
+ }
+
++ q = skb_get_queue_mapping(skb);
++ if (q >= 4)
++ q = 0;
++
++ spin_lock_bh(&txq->axq_lock);
++ if (++sc->tx.pending_frames[q] > ATH_MAX_QDEPTH && !txq->stopped) {
++ ath_mac80211_stop_queue(sc, skb_get_queue_mapping(skb));
++ txq->stopped = 1;
++ }
++ spin_unlock_bh(&txq->axq_lock);
++
+ ath_tx_start_dma(sc, bf, txctl);
+
+ return 0;
+@@ -1865,7 +1868,7 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
+ struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+ struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+ struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
+- int padpos, padsize;
++ int q, padpos, padsize;
+
+ ath_print(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
+
+@@ -1904,8 +1907,16 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
+
+ if (unlikely(tx_info->pad[0] & ATH_TX_INFO_FRAME_TYPE_INTERNAL))
+ ath9k_tx_status(hw, skb);
+- else
++ else {
++ q = skb_get_queue_mapping(skb);
++ if (q >= 4)
++ q = 0;
++
++ if (--sc->tx.pending_frames[q] < 0)
++ sc->tx.pending_frames[q] = 0;
++
+ ieee80211_tx_status(hw, skb);
++ }
+ }
+
+ static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
+@@ -1926,13 +1937,6 @@ static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
+ tx_flags |= ATH_TX_XRETRY;
+ }
+
+- if (bf->txq) {
+- spin_lock_bh(&bf->txq->axq_lock);
+- bf->txq->pending_frames--;
+- spin_unlock_bh(&bf->txq->axq_lock);
+- bf->txq = NULL;
+- }
+-
+ dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE);
+ ath_tx_complete(sc, skb, bf->aphy, tx_flags);
+ ath_debug_stat_tx(sc, txq, bf, ts);
+@@ -2020,13 +2024,14 @@ static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
+ {
+ int qnum;
+
++ qnum = ath_get_mac80211_qnum(txq->axq_class, sc);
++ if (qnum == -1)
++ return;
++
+ spin_lock_bh(&txq->axq_lock);
+- if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
+- qnum = ath_get_mac80211_qnum(txq->axq_class, sc);
+- if (qnum != -1) {
+- ath_mac80211_start_queue(sc, qnum);
+- txq->stopped = 0;
+- }
++ if (txq->stopped && sc->tx.pending_frames[qnum] < ATH_MAX_QDEPTH) {
++ ath_mac80211_start_queue(sc, qnum);
++ txq->stopped = 0;
+ }
+ spin_unlock_bh(&txq->axq_lock);
+ }
+--
+1.6.3.3
+
--- /dev/null
+From 7ca3a56dd363b66f91f9e32ba8009707ef2c84f0 Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@openwrt.org>
+Date: Thu, 10 Jun 2010 22:07:52 +0200
+Subject: [PATCH 18/24] ath9k: add a debugfs entry for ignoring CCA on the extension channel in HT40
+
+Debugfs requires a u32 for bool knobs though so we turn the
+ath9k_hw knob into a u32 as well.
+
+Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
+---
+ drivers/net/wireless/ath/ath9k/debug.c | 4 ++++
+ drivers/net/wireless/ath/ath9k/hw.h | 2 +-
+ 2 files changed, 5 insertions(+), 1 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath9k/debug.c b/drivers/net/wireless/ath/ath9k/debug.c
+index a6cb48d..54aae93 100644
+--- a/drivers/net/wireless/ath/ath9k/debug.c
++++ b/drivers/net/wireless/ath/ath9k/debug.c
+@@ -956,6 +956,10 @@ int ath9k_init_debug(struct ath_hw *ah)
+ sc->debug.debugfs_phy, sc, &fops_regval))
+ goto err;
+
++ if (!debugfs_create_bool("ignore_extcca", S_IRUSR | S_IWUSR,
++ sc->debug.debugfs_phy, &ah->config.cwm_ignore_extcca))
++ goto err;
++
+ sc->debug.regidx = 0;
+ return 0;
+ err:
+diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
+index ba84ac7..20ec29f 100644
+--- a/drivers/net/wireless/ath/ath9k/hw.h
++++ b/drivers/net/wireless/ath/ath9k/hw.h
+@@ -238,7 +238,7 @@ struct ath9k_ops_config {
+ int sw_beacon_response_time;
+ int additional_swba_backoff;
+ int ack_6mb;
+- int cwm_ignore_extcca;
++ u32 cwm_ignore_extcca;
+ u8 pcie_powersave_enable;
+ u8 pcie_clock_req;
+ u32 pcie_waen;
+--
+1.6.3.3
+
--- /dev/null
+From 1069209f005c5d3f424188b7b4f7375eb43e6d5c Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@openwrt.org>
+Date: Fri, 11 Jun 2010 16:20:21 +0200
+Subject: [PATCH 19/24] ath9k_hw: remove a useless function for setting the mac address
+
+ath9k_hw_setmac() only copies the mac address it is called with into
+common->macaddr, yet in all call sites, the supplied mac address pointer
+is already common->macaddr.
+
+Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+---
+ drivers/net/wireless/ath/ath9k/htc_drv_txrx.c | 3 ---
+ drivers/net/wireless/ath/ath9k/hw.c | 6 ------
+ drivers/net/wireless/ath/ath9k/hw.h | 1 -
+ drivers/net/wireless/ath/ath9k/recv.c | 3 ---
+ 4 files changed, 0 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
+index 89d81ab..89d3848 100644
+--- a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
++++ b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
+@@ -403,9 +403,6 @@ static void ath9k_htc_opmode_init(struct ath9k_htc_priv *priv)
+ /* configure operational mode */
+ ath9k_hw_setopmode(ah);
+
+- /* Handle any link-level address change. */
+- ath9k_hw_setmac(ah, common->macaddr);
+-
+ /* calculate and install multicast filter */
+ mfilt[0] = mfilt[1] = ~0;
+ ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
+diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
+index 1fa3fe7..83e0461 100644
+--- a/drivers/net/wireless/ath/ath9k/hw.c
++++ b/drivers/net/wireless/ath/ath9k/hw.c
+@@ -2538,12 +2538,6 @@ void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
+ }
+ EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
+
+-void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
+-{
+- memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
+-}
+-EXPORT_SYMBOL(ath9k_hw_setmac);
+-
+ void ath9k_hw_setopmode(struct ath_hw *ah)
+ {
+ ath9k_hw_set_operating_mode(ah, ah->opmode);
+diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
+index 20ec29f..09dd7be 100644
+--- a/drivers/net/wireless/ath/ath9k/hw.h
++++ b/drivers/net/wireless/ath/ath9k/hw.h
+@@ -885,7 +885,6 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
+ bool ath9k_hw_phy_disable(struct ath_hw *ah);
+ bool ath9k_hw_disable(struct ath_hw *ah);
+ void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
+-void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
+ void ath9k_hw_setopmode(struct ath_hw *ah);
+ void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
+ void ath9k_hw_setbssidmask(struct ath_hw *ah);
+diff --git a/drivers/net/wireless/ath/ath9k/recv.c b/drivers/net/wireless/ath/ath9k/recv.c
+index 78ef1ae..da0cfe9 100644
+--- a/drivers/net/wireless/ath/ath9k/recv.c
++++ b/drivers/net/wireless/ath/ath9k/recv.c
+@@ -116,9 +116,6 @@ static void ath_opmode_init(struct ath_softc *sc)
+ /* configure operational mode */
+ ath9k_hw_setopmode(ah);
+
+- /* Handle any link-level address change. */
+- ath9k_hw_setmac(ah, common->macaddr);
+-
+ /* calculate and install multicast filter */
+ mfilt[0] = mfilt[1] = ~0;
+ ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
+--
+1.6.3.3
+
--- /dev/null
+From 97f3821f474c31e6a231e5a8ecb22320304c9b49 Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@openwrt.org>
+Date: Thu, 10 Jun 2010 22:09:33 +0200
+Subject: [PATCH 20/24] ath9k_hw: add register definitions related to PA predistortion
+
+Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+---
+ drivers/net/wireless/ath/ath9k/ar9003_phy.h | 224 +++++++++++++++++++++++++--
+ 1 files changed, 207 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
+index 265f59f..3394dfe 100644
+--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
++++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
+@@ -459,7 +459,11 @@
+ #define AR_PHY_TSTDAC (AR_SM_BASE + 0x168)
+
+ #define AR_PHY_CHAN_STATUS (AR_SM_BASE + 0x16c)
+-#define AR_PHY_CHAN_INFO_MEMORY (AR_SM_BASE + 0x170)
++
++#define AR_PHY_CHAN_INFO_MEMORY (AR_SM_BASE + 0x170)
++#define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ 0x00000008
++#define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ_S 3
++
+ #define AR_PHY_CHNINFO_NOISEPWR (AR_SM_BASE + 0x174)
+ #define AR_PHY_CHNINFO_GAINDIFF (AR_SM_BASE + 0x178)
+ #define AR_PHY_CHNINFO_FINETIM (AR_SM_BASE + 0x17c)
+@@ -475,17 +479,63 @@
+ #define AR_PHY_PWRTX_MAX (AR_SM_BASE + 0x1f0)
+ #define AR_PHY_POWER_TX_SUB (AR_SM_BASE + 0x1f4)
+
+-#define AR_PHY_TPC_4_B0 (AR_SM_BASE + 0x204)
+-#define AR_PHY_TPC_5_B0 (AR_SM_BASE + 0x208)
+-#define AR_PHY_TPC_6_B0 (AR_SM_BASE + 0x20c)
+-#define AR_PHY_TPC_11_B0 (AR_SM_BASE + 0x220)
+-#define AR_PHY_TPC_18 (AR_SM_BASE + 0x23c)
+-#define AR_PHY_TPC_19 (AR_SM_BASE + 0x240)
++#define AR_PHY_TPC_1 (AR_SM_BASE + 0x1f8)
++#define AR_PHY_TPC_1_FORCED_DAC_GAIN 0x0000003e
++#define AR_PHY_TPC_1_FORCED_DAC_GAIN_S 1
++#define AR_PHY_TPC_1_FORCE_DAC_GAIN 0x00000001
++#define AR_PHY_TPC_1_FORCE_DAC_GAIN_S 0
++
++#define AR_PHY_TPC_4_B0 (AR_SM_BASE + 0x204)
++#define AR_PHY_TPC_5_B0 (AR_SM_BASE + 0x208)
++#define AR_PHY_TPC_6_B0 (AR_SM_BASE + 0x20c)
++
++#define AR_PHY_TPC_11_B0 (AR_SM_BASE + 0x220)
++#define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220)
++#define AR_PHY_TPC_11_B2 (AR_SM2_BASE + 0x220)
++#define AR_PHY_TPC_11_OLPC_GAIN_DELTA 0x00ff0000
++#define AR_PHY_TPC_11_OLPC_GAIN_DELTA_S 16
++
++#define AR_PHY_TPC_12 (AR_SM_BASE + 0x224)
++#define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5 0x3e000000
++#define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5_S 25
++
++#define AR_PHY_TPC_18 (AR_SM_BASE + 0x23c)
++#define AR_PHY_TPC_18_THERM_CAL_VALUE 0x000000ff
++#define AR_PHY_TPC_18_THERM_CAL_VALUE_S 0
++#define AR_PHY_TPC_18_VOLT_CAL_VALUE 0x0000ff00
++#define AR_PHY_TPC_18_VOLT_CAL_VALUE_S 8
++
++#define AR_PHY_TPC_19 (AR_SM_BASE + 0x240)
++#define AR_PHY_TPC_19_ALPHA_VOLT 0x001f0000
++#define AR_PHY_TPC_19_ALPHA_VOLT_S 16
++#define AR_PHY_TPC_19_ALPHA_THERM 0xff
++#define AR_PHY_TPC_19_ALPHA_THERM_S 0
++
++#define AR_PHY_TX_FORCED_GAIN (AR_SM_BASE + 0x258)
++#define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN 0x00000001
++#define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN_S 0
++#define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN 0x0000000e
++#define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_S 1
++#define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN 0x00000030
++#define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_S 4
++#define AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN 0x000003c0
++#define AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN_S 6
++#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA 0x00003c00
++#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA_S 10
++#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB 0x0003c000
++#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB_S 14
++#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC 0x003c0000
++#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC_S 18
++#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND 0x00c00000
++#define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND_S 22
++#define AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL 0x01000000
++#define AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL_S 24
+
+-#define AR_PHY_TX_FORCED_GAIN (AR_SM_BASE + 0x258)
+
+ #define AR_PHY_PDADC_TAB_0 (AR_SM_BASE + 0x280)
+
++#define AR_PHY_TXGAIN_TABLE (AR_SM_BASE + 0x300)
++
+ #define AR_PHY_TX_IQCAL_CONTROL_1 (AR_SM_BASE + 0x448)
+ #define AR_PHY_TX_IQCAL_START (AR_SM_BASE + 0x440)
+ #define AR_PHY_TX_IQCAL_STATUS_B0 (AR_SM_BASE + 0x48c)
+@@ -498,7 +548,17 @@
+ #define AR_PHY_ONLY_WARMRESET (AR_SM_BASE + 0x5d0)
+ #define AR_PHY_ONLY_CTL (AR_SM_BASE + 0x5d4)
+ #define AR_PHY_ECO_CTRL (AR_SM_BASE + 0x5dc)
+-#define AR_PHY_BB_THERM_ADC_1 (AR_SM_BASE + 0x248)
++
++#define AR_PHY_BB_THERM_ADC_1 (AR_SM_BASE + 0x248)
++#define AR_PHY_BB_THERM_ADC_1_INIT_THERM 0x000000ff
++#define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S 0
++
++#define AR_PHY_BB_THERM_ADC_4 (AR_SM_BASE + 0x254)
++#define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE 0x000000ff
++#define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_S 0
++#define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE 0x0000ff00
++#define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_S 8
++
+
+ #define AR_PHY_65NM_CH0_SYNTH4 0x1608c
+ #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT 0x00000002
+@@ -668,17 +728,9 @@
+ #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE 0x00003fff
+ #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S 0
+
+-#define AR_PHY_TPC_18_THERM_CAL_VALUE 0xff
+-#define AR_PHY_TPC_18_THERM_CAL_VALUE_S 0
+-#define AR_PHY_TPC_19_ALPHA_THERM 0xff
+-#define AR_PHY_TPC_19_ALPHA_THERM_S 0
+-
+ #define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000
+ #define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28
+
+-#define AR_PHY_BB_THERM_ADC_1_INIT_THERM 0x000000ff
+-#define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S 0
+-
+ /*
+ * Channel 1 Register Map
+ */
+@@ -850,6 +902,144 @@
+
+ #define AR_PHY_WATCHDOG_STATUS_CLR 0x00000008
+
++/*
++ * PAPRD registers
++ */
++#define AR_PHY_XPA_TIMING_CTL (AR_SM_BASE + 0x64)
++
++#define AR_PHY_PAPRD_AM2AM (AR_CHAN_BASE + 0xe4)
++#define AR_PHY_PAPRD_AM2AM_MASK 0x01ffffff
++#define AR_PHY_PAPRD_AM2AM_MASK_S 0
++
++#define AR_PHY_PAPRD_AM2PM (AR_CHAN_BASE + 0xe8)
++#define AR_PHY_PAPRD_AM2PM_MASK 0x01ffffff
++#define AR_PHY_PAPRD_AM2PM_MASK_S 0
++
++#define AR_PHY_PAPRD_HT40 (AR_CHAN_BASE + 0xec)
++#define AR_PHY_PAPRD_HT40_MASK 0x01ffffff
++#define AR_PHY_PAPRD_HT40_MASK_S 0
++
++#define AR_PHY_PAPRD_CTRL0_B0 (AR_CHAN_BASE + 0xf0)
++#define AR_PHY_PAPRD_CTRL0_B1 (AR_CHAN1_BASE + 0xf0)
++#define AR_PHY_PAPRD_CTRL0_B2 (AR_CHAN2_BASE + 0xf0)
++#define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE 0x00000001
++#define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE_S 0
++#define AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK 0x00000002
++#define AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK_S 1
++#define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH 0xf8000000
++#define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH_S 27
++
++#define AR_PHY_PAPRD_CTRL1_B0 (AR_CHAN_BASE + 0xf4)
++#define AR_PHY_PAPRD_CTRL1_B1 (AR_CHAN1_BASE + 0xf4)
++#define AR_PHY_PAPRD_CTRL1_B2 (AR_CHAN2_BASE + 0xf4)
++#define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA 0x00000001
++#define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA_S 0
++#define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENABLE 0x00000002
++#define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENABLE_S 1
++#define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENABLE 0x00000004
++#define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENABLE_S 2
++#define AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL 0x000001f8
++#define AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_S 3
++#define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_MASK 0x0001fe00
++#define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_MASK_S 9
++#define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT 0x0ffe0000
++#define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT_S 17
++
++#define AR_PHY_PAPRD_TRAINER_CNTL1 (AR_SM_BASE + 0x490)
++#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE 0x00000001
++#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE_S 0
++#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING 0x0000007e
++#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_S 1
++#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE 0x00000100
++#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_S 8
++#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE 0x00000200
++#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_S 9
++#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE 0x00000400
++#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_S 10
++#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE 0x00000800
++#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_S 11
++#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP 0x0003f000
++#define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_S 12
++
++#define AR_PHY_PAPRD_TRAINER_CNTL2 (AR_SM_BASE + 0x494)
++#define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN 0xFFFFFFFF
++#define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_S 0
++
++#define AR_PHY_PAPRD_TRAINER_CNTL3 (AR_SM_BASE + 0x498)
++#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE 0x0000003f
++#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_S 0
++#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP 0x00000fc0
++#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_S 6
++#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL 0x0001f000
++#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_S 12
++#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES 0x000e0000
++#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_S 17
++#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN 0x00f00000
++#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_S 20
++#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN 0x0f000000
++#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_S 24
++#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE 0x20000000
++#define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_S 29
++
++#define AR_PHY_PAPRD_TRAINER_CNTL4 (AR_SM_BASE + 0x49c)
++#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES 0x03ff0000
++#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_S 16
++#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA 0x0000f000
++#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_S 12
++#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR 0x00000fff
++#define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_S 0
++
++#define AR_PHY_PAPRD_PRE_POST_SCALE_0_B0 (AR_CHAN_BASE + 0x100)
++#define AR_PHY_PAPRD_PRE_POST_SCALE_1_B0 (AR_CHAN_BASE + 0x104)
++#define AR_PHY_PAPRD_PRE_POST_SCALE_2_B0 (AR_CHAN_BASE + 0x108)
++#define AR_PHY_PAPRD_PRE_POST_SCALE_3_B0 (AR_CHAN_BASE + 0x10c)
++#define AR_PHY_PAPRD_PRE_POST_SCALE_4_B0 (AR_CHAN_BASE + 0x110)
++#define AR_PHY_PAPRD_PRE_POST_SCALE_5_B0 (AR_CHAN_BASE + 0x114)
++#define AR_PHY_PAPRD_PRE_POST_SCALE_6_B0 (AR_CHAN_BASE + 0x118)
++#define AR_PHY_PAPRD_PRE_POST_SCALE_7_B0 (AR_CHAN_BASE + 0x11c)
++#define AR_PHY_PAPRD_PRE_POST_SCALING 0x3FFFF
++#define AR_PHY_PAPRD_PRE_POST_SCALING_S 0
++
++#define AR_PHY_PAPRD_TRAINER_STAT1 (AR_SM_BASE + 0x4a0)
++#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE 0x00000001
++#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_S 0
++#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE 0x00000002
++#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_S 1
++#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR 0x00000004
++#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_S 2
++#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE 0x00000008
++#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_S 3
++#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX 0x000001f0
++#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_S 4
++#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR 0x0001fe00
++#define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_S 9
++
++#define AR_PHY_PAPRD_TRAINER_STAT2 (AR_SM_BASE + 0x4a4)
++#define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL 0x0000ffff
++#define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_S 0
++#define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX 0x001f0000
++#define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_S 16
++#define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX 0x00600000
++#define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_S 21
++
++#define AR_PHY_PAPRD_TRAINER_STAT3 (AR_SM_BASE + 0x4a8)
++#define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT 0x000fffff
++#define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_S 0
++
++#define AR_PHY_PAPRD_MEM_TAB_B0 (AR_CHAN_BASE + 0x120)
++#define AR_PHY_PAPRD_MEM_TAB_B1 (AR_CHAN1_BASE + 0x120)
++#define AR_PHY_PAPRD_MEM_TAB_B2 (AR_CHAN2_BASE + 0x120)
++
++#define AR_PHY_PA_GAIN123_B0 (AR_CHAN_BASE + 0xf8)
++#define AR_PHY_PA_GAIN123_B1 (AR_CHAN1_BASE + 0xf8)
++#define AR_PHY_PA_GAIN123_B2 (AR_CHAN2_BASE + 0xf8)
++#define AR_PHY_PA_GAIN123_PA_GAIN1 0x3FF
++#define AR_PHY_PA_GAIN123_PA_GAIN1_S 0
++
++#define AR_PHY_POWERTX_RATE5 (AR_SM_BASE + 0x1d0)
++#define AR_PHY_POWERTX_RATE5_POWERTXHT20_0 0x3F
++#define AR_PHY_POWERTX_RATE5_POWERTXHT20_0_S 0
++
+ void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
+
+ #endif /* AR9003_PHY_H */
+--
+1.6.3.3
+
--- /dev/null
+From 4a6b419e6d81cb87cacebd92562cbc745aac1b9a Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@openwrt.org>
+Date: Thu, 10 Jun 2010 22:19:47 +0200
+Subject: [PATCH 21/24] ath9k_hw: add support for parsing PA predistortion related EEPROM fields
+
+Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+---
+ drivers/net/wireless/ath/ath9k/ar9003_eeprom.c | 13 ++++++++++---
+ drivers/net/wireless/ath/ath9k/ar9003_eeprom.h | 4 +++-
+ drivers/net/wireless/ath/ath9k/eeprom.h | 3 ++-
+ drivers/net/wireless/ath/ath9k/hw.c | 2 ++
+ drivers/net/wireless/ath/ath9k/hw.h | 1 +
+ 5 files changed, 18 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+index 23eb60e..343c9a4 100644
+--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+@@ -67,6 +67,7 @@ static const struct ar9300_eeprom ar9300_default = {
+ * bit2 - enable fastClock - enabled
+ * bit3 - enable doubling - enabled
+ * bit4 - enable internal regulator - disabled
++ * bit5 - enable pa predistortion - disabled
+ */
+ .miscConfiguration = 0, /* bit0 - turn down drivestrength */
+ .eepromWriteEnableGpio = 3,
+@@ -129,9 +130,11 @@ static const struct ar9300_eeprom ar9300_default = {
+ .txEndToRxOn = 0x2,
+ .txFrameToXpaOn = 0xe,
+ .thresh62 = 28,
+- .futureModal = { /* [32] */
++ .papdRateMaskHt20 = LE32(0x80c080),
++ .papdRateMaskHt40 = LE32(0x80c080),
++ .futureModal = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
++ 0, 0, 0, 0, 0, 0, 0, 0
+ },
+ },
+ .calFreqPier2G = {
+@@ -326,9 +329,11 @@ static const struct ar9300_eeprom ar9300_default = {
+ .txEndToRxOn = 0x2,
+ .txFrameToXpaOn = 0xe,
+ .thresh62 = 28,
++ .papdRateMaskHt20 = LE32(0xf0e0e0),
++ .papdRateMaskHt40 = LE32(0xf0e0e0),
+ .futureModal = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
++ 0, 0, 0, 0, 0, 0, 0, 0
+ },
+ },
+ .calFreqPier5G = {
+@@ -644,6 +649,8 @@ static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
+ return (pBase->featureEnable & 0x10) >> 4;
+ case EEP_SWREG:
+ return le32_to_cpu(pBase->swreg);
++ case EEP_PAPRD:
++ return !!(pBase->featureEnable & BIT(5));
+ default:
+ return 0;
+ }
+diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
+index 23fb353..3c533bb 100644
+--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
++++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
+@@ -234,7 +234,9 @@ struct ar9300_modal_eep_header {
+ u8 txEndToRxOn;
+ u8 txFrameToXpaOn;
+ u8 thresh62;
+- u8 futureModal[32];
++ __le32 papdRateMaskHt20;
++ __le32 papdRateMaskHt40;
++ u8 futureModal[24];
+ } __packed;
+
+ struct ar9300_cal_data_per_freq_op_loop {
+diff --git a/drivers/net/wireless/ath/ath9k/eeprom.h b/drivers/net/wireless/ath/ath9k/eeprom.h
+index 7da7d73..bdd8aa0 100644
+--- a/drivers/net/wireless/ath/ath9k/eeprom.h
++++ b/drivers/net/wireless/ath/ath9k/eeprom.h
+@@ -263,7 +263,8 @@ enum eeprom_param {
+ EEP_PWR_TABLE_OFFSET,
+ EEP_DRIVE_STRENGTH,
+ EEP_INTERNAL_REGULATOR,
+- EEP_SWREG
++ EEP_SWREG,
++ EEP_PAPRD,
+ };
+
+ enum ar5416_rates {
+diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
+index 83e0461..5a2e72a 100644
+--- a/drivers/net/wireless/ath/ath9k/hw.c
++++ b/drivers/net/wireless/ath/ath9k/hw.c
+@@ -2235,6 +2235,8 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
+ pCap->rx_status_len = sizeof(struct ar9003_rxs);
+ pCap->tx_desc_len = sizeof(struct ar9003_txc);
+ pCap->txs_len = sizeof(struct ar9003_txs);
++ if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
++ pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
+ } else {
+ pCap->tx_desc_len = sizeof(struct ath_desc);
+ if (AR_SREV_9280_20(ah) &&
+diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
+index 09dd7be..9d09216 100644
+--- a/drivers/net/wireless/ath/ath9k/hw.h
++++ b/drivers/net/wireless/ath/ath9k/hw.h
+@@ -200,6 +200,7 @@ enum ath9k_hw_caps {
+ ATH9K_HW_CAP_LDPC = BIT(19),
+ ATH9K_HW_CAP_FASTCLOCK = BIT(20),
+ ATH9K_HW_CAP_SGI_20 = BIT(21),
++ ATH9K_HW_CAP_PAPRD = BIT(22),
+ };
+
+ enum ath9k_capability_type {
+--
+1.6.3.3
+
--- /dev/null
+From 8196760e1eb201d4d2707560b3c6beae05d4c107 Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@openwrt.org>
+Date: Thu, 10 Jun 2010 22:21:40 +0200
+Subject: [PATCH 22/24] ath9k_hw: add functions for controlling PA predistortion calibration
+
+Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+---
+ drivers/net/wireless/ath/ath9k/Makefile | 3 +-
+ drivers/net/wireless/ath/ath9k/ar9003_mac.c | 8 +
+ drivers/net/wireless/ath/ath9k/ar9003_mac.h | 4 +
+ drivers/net/wireless/ath/ath9k/ar9003_paprd.c | 714 +++++++++++++++++++++++++
+ drivers/net/wireless/ath/ath9k/hw.h | 18 +
+ 5 files changed, 746 insertions(+), 1 deletions(-)
+ create mode 100644 drivers/net/wireless/ath/ath9k/ar9003_paprd.c
+
+diff --git a/drivers/net/wireless/ath/ath9k/Makefile b/drivers/net/wireless/ath/ath9k/Makefile
+index dd112be..973ae4f 100644
+--- a/drivers/net/wireless/ath/ath9k/Makefile
++++ b/drivers/net/wireless/ath/ath9k/Makefile
+@@ -32,7 +32,8 @@ ath9k_hw-y:= \
+ mac.o \
+ ar9002_mac.o \
+ ar9003_mac.o \
+- ar9003_eeprom.o
++ ar9003_eeprom.o \
++ ar9003_paprd.o
+
+ obj-$(CONFIG_ATH9K_HW) += ath9k_hw.o
+
+diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.c b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
+index 4073107..06ef710 100644
+--- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
+@@ -470,6 +470,14 @@ static void ar9003_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
+ ads->ctl11 &= ~AR_VirtMoreFrag;
+ }
+
++void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains)
++{
++ struct ar9003_txc *ads = ds;
++
++ ads->ctl12 |= SM(chains, AR_PAPRDChainMask);
++}
++EXPORT_SYMBOL(ar9003_hw_set_paprd_txdesc);
++
+ void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
+ {
+ struct ath_hw_ops *ops = ath9k_hw_ops(hw);
+diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.h b/drivers/net/wireless/ath/ath9k/ar9003_mac.h
+index 5a7a286..f76f27d 100644
+--- a/drivers/net/wireless/ath/ath9k/ar9003_mac.h
++++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.h
+@@ -40,6 +40,10 @@
+
+ #define AR_Not_Sounding 0x20000000
+
++/* ctl 12 */
++#define AR_PAPRDChainMask 0x00000e00
++#define AR_PAPRDChainMask_S 9
++
+ #define MAP_ISR_S2_CST 6
+ #define MAP_ISR_S2_GTT 6
+ #define MAP_ISR_S2_TIM 3
+diff --git a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
+new file mode 100644
+index 0000000..49e0c86
+--- /dev/null
++++ b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
+@@ -0,0 +1,714 @@
++/*
++ * Copyright (c) 2010 Atheros Communications Inc.
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include "hw.h"
++#include "ar9003_phy.h"
++
++void ar9003_paprd_enable(struct ath_hw *ah, bool val)
++{
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B0,
++ AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B1,
++ AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B2,
++ AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val);
++}
++EXPORT_SYMBOL(ar9003_paprd_enable);
++
++static void ar9003_paprd_setup_single_table(struct ath_hw *ah)
++{
++ struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
++ struct ar9300_modal_eep_header *hdr;
++ const u32 ctrl0[3] = {
++ AR_PHY_PAPRD_CTRL0_B0,
++ AR_PHY_PAPRD_CTRL0_B1,
++ AR_PHY_PAPRD_CTRL0_B2
++ };
++ const u32 ctrl1[3] = {
++ AR_PHY_PAPRD_CTRL1_B0,
++ AR_PHY_PAPRD_CTRL1_B1,
++ AR_PHY_PAPRD_CTRL1_B2
++ };
++ u32 am_mask, ht40_mask;
++ int i;
++
++ if (ah->curchan && IS_CHAN_5GHZ(ah->curchan))
++ hdr = &eep->modalHeader5G;
++ else
++ hdr = &eep->modalHeader2G;
++
++ am_mask = le32_to_cpu(hdr->papdRateMaskHt20);
++ ht40_mask = le32_to_cpu(hdr->papdRateMaskHt40);
++
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2AM, AR_PHY_PAPRD_AM2AM_MASK, am_mask);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2PM, AR_PHY_PAPRD_AM2PM_MASK, am_mask);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_HT40, AR_PHY_PAPRD_HT40_MASK, ht40_mask);
++
++ for (i = 0; i < 3; i++) {
++ REG_RMW_FIELD(ah, ctrl0[i],
++ AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK, 1);
++ REG_RMW_FIELD(ah, ctrl1[i],
++ AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENABLE, 1);
++ REG_RMW_FIELD(ah, ctrl1[i],
++ AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENABLE, 1);
++ REG_RMW_FIELD(ah, ctrl1[i],
++ AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA, 0);
++ REG_RMW_FIELD(ah, ctrl1[i],
++ AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_MASK, 181);
++ REG_RMW_FIELD(ah, ctrl1[i],
++ AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT, 361);
++ REG_RMW_FIELD(ah, ctrl1[i],
++ AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA, 0);
++ REG_RMW_FIELD(ah, ctrl0[i],
++ AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH, 3);
++ }
++
++ ar9003_paprd_enable(ah, false);
++
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL1,
++ AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP, 0x30);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL1,
++ AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE, 1);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL1,
++ AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE, 1);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL1,
++ AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE, 0);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL1,
++ AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE, 0);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL1,
++ AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING, 28);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL1,
++ AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE, 1);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL2,
++ AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN, 147);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
++ AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN, 4);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
++ AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN, 4);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
++ AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES, 7);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
++ AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL, 1);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
++ AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, -6);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
++ AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE,
++ -15);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
++ AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE, 1);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL4,
++ AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA, 0);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL4,
++ AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR, 400);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL4,
++ AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES,
++ 100);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_PRE_POST_SCALE_0_B0,
++ AR_PHY_PAPRD_PRE_POST_SCALING, 261376);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_PRE_POST_SCALE_1_B0,
++ AR_PHY_PAPRD_PRE_POST_SCALING, 248079);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_PRE_POST_SCALE_2_B0,
++ AR_PHY_PAPRD_PRE_POST_SCALING, 233759);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_PRE_POST_SCALE_3_B0,
++ AR_PHY_PAPRD_PRE_POST_SCALING, 220464);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_PRE_POST_SCALE_4_B0,
++ AR_PHY_PAPRD_PRE_POST_SCALING, 208194);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_PRE_POST_SCALE_5_B0,
++ AR_PHY_PAPRD_PRE_POST_SCALING, 196949);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_PRE_POST_SCALE_6_B0,
++ AR_PHY_PAPRD_PRE_POST_SCALING, 185706);
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_PRE_POST_SCALE_7_B0,
++ AR_PHY_PAPRD_PRE_POST_SCALING, 175487);
++}
++
++static void ar9003_paprd_get_gain_table(struct ath_hw *ah)
++{
++ u32 *entry = ah->paprd_gain_table_entries;
++ u8 *index = ah->paprd_gain_table_index;
++ u32 reg = AR_PHY_TXGAIN_TABLE;
++ int i;
++
++ memset(entry, 0, sizeof(ah->paprd_gain_table_entries));
++ memset(index, 0, sizeof(ah->paprd_gain_table_index));
++
++ for (i = 0; i < 32; i++) {
++ entry[i] = REG_READ(ah, reg);
++ index[i] = (entry[i] >> 24) & 0xff;
++ reg += 4;
++ }
++}
++
++static unsigned int ar9003_get_desired_gain(struct ath_hw *ah, int chain,
++ int target_power)
++{
++ int olpc_gain_delta = 0;
++ int alpha_therm, alpha_volt;
++ int therm_cal_value, volt_cal_value;
++ int therm_value, volt_value;
++ int thermal_gain_corr, voltage_gain_corr;
++ int desired_scale, desired_gain = 0;
++ u32 reg;
++
++ REG_CLR_BIT(ah, AR_PHY_PAPRD_TRAINER_STAT1,
++ AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE);
++ desired_scale = REG_READ_FIELD(ah, AR_PHY_TPC_12,
++ AR_PHY_TPC_12_DESIRED_SCALE_HT40_5);
++ alpha_therm = REG_READ_FIELD(ah, AR_PHY_TPC_19,
++ AR_PHY_TPC_19_ALPHA_THERM);
++ alpha_volt = REG_READ_FIELD(ah, AR_PHY_TPC_19,
++ AR_PHY_TPC_19_ALPHA_VOLT);
++ therm_cal_value = REG_READ_FIELD(ah, AR_PHY_TPC_18,
++ AR_PHY_TPC_18_THERM_CAL_VALUE);
++ volt_cal_value = REG_READ_FIELD(ah, AR_PHY_TPC_18,
++ AR_PHY_TPC_18_VOLT_CAL_VALUE);
++ therm_value = REG_READ_FIELD(ah, AR_PHY_BB_THERM_ADC_4,
++ AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE);
++ volt_value = REG_READ_FIELD(ah, AR_PHY_BB_THERM_ADC_4,
++ AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE);
++
++ if (chain == 0)
++ reg = AR_PHY_TPC_11_B0;
++ else if (chain == 1)
++ reg = AR_PHY_TPC_11_B1;
++ else
++ reg = AR_PHY_TPC_11_B2;
++
++ olpc_gain_delta = REG_READ_FIELD(ah, reg,
++ AR_PHY_TPC_11_OLPC_GAIN_DELTA);
++
++ if (olpc_gain_delta >= 128)
++ olpc_gain_delta = olpc_gain_delta - 256;
++
++ thermal_gain_corr = (alpha_therm * (therm_value - therm_cal_value) +
++ (256 / 2)) / 256;
++ voltage_gain_corr = (alpha_volt * (volt_value - volt_cal_value) +
++ (128 / 2)) / 128;
++ desired_gain = target_power - olpc_gain_delta - thermal_gain_corr -
++ voltage_gain_corr + desired_scale;
++
++ return desired_gain;
++}
++
++static void ar9003_tx_force_gain(struct ath_hw *ah, unsigned int gain_index)
++{
++ int selected_gain_entry, txbb1dbgain, txbb6dbgain, txmxrgain;
++ int padrvgnA, padrvgnB, padrvgnC, padrvgnD;
++ u32 *gain_table_entries = ah->paprd_gain_table_entries;
++
++ selected_gain_entry = gain_table_entries[gain_index];
++ txbb1dbgain = selected_gain_entry & 0x7;
++ txbb6dbgain = (selected_gain_entry >> 3) & 0x3;
++ txmxrgain = (selected_gain_entry >> 5) & 0xf;
++ padrvgnA = (selected_gain_entry >> 9) & 0xf;
++ padrvgnB = (selected_gain_entry >> 13) & 0xf;
++ padrvgnC = (selected_gain_entry >> 17) & 0xf;
++ padrvgnD = (selected_gain_entry >> 21) & 0x3;
++
++ REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
++ AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN, txbb1dbgain);
++ REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
++ AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN, txbb6dbgain);
++ REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
++ AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN, txmxrgain);
++ REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
++ AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA, padrvgnA);
++ REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
++ AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB, padrvgnB);
++ REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
++ AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC, padrvgnC);
++ REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
++ AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND, padrvgnD);
++ REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
++ AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL, 0);
++ REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
++ AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN, 0);
++ REG_RMW_FIELD(ah, AR_PHY_TPC_1, AR_PHY_TPC_1_FORCED_DAC_GAIN, 0);
++ REG_RMW_FIELD(ah, AR_PHY_TPC_1, AR_PHY_TPC_1_FORCE_DAC_GAIN, 0);
++}
++
++static inline int find_expn(int num)
++{
++ return fls(num) - 1;
++}
++
++static inline int find_proper_scale(int expn, int N)
++{
++ return (expn > N) ? expn - 10 : 0;
++}
++
++#define NUM_BIN 23
++
++static bool create_pa_curve(u32 *data_L, u32 *data_U, u32 *pa_table, u16 *gain)
++{
++ unsigned int thresh_accum_cnt;
++ int x_est[NUM_BIN + 1], Y[NUM_BIN + 1], theta[NUM_BIN + 1];
++ int PA_in[NUM_BIN + 1];
++ int B1_tmp[NUM_BIN + 1], B2_tmp[NUM_BIN + 1];
++ unsigned int B1_abs_max, B2_abs_max;
++ int max_index, scale_factor;
++ int y_est[NUM_BIN + 1];
++ int x_est_fxp1_nonlin, x_tilde[NUM_BIN + 1];
++ unsigned int x_tilde_abs;
++ int G_fxp, Y_intercept, order_x_by_y, M, I, L, sum_y_sqr, sum_y_quad;
++ int Q_x, Q_B1, Q_B2, beta_raw, alpha_raw, scale_B;
++ int Q_scale_B, Q_beta, Q_alpha, alpha, beta, order_1, order_2;
++ int order1_5x, order2_3x, order1_5x_rem, order2_3x_rem;
++ int y5, y3, tmp;
++ int theta_low_bin = 0;
++ int i;
++
++ /* disregard any bin that contains <= 16 samples */
++ thresh_accum_cnt = 16;
++ scale_factor = 5;
++ max_index = 0;
++ memset(theta, 0, sizeof(theta));
++ memset(x_est, 0, sizeof(x_est));
++ memset(Y, 0, sizeof(Y));
++ memset(y_est, 0, sizeof(y_est));
++ memset(x_tilde, 0, sizeof(x_tilde));
++
++ for (i = 0; i < NUM_BIN; i++) {
++ s32 accum_cnt, accum_tx, accum_rx, accum_ang;
++
++ /* number of samples */
++ accum_cnt = data_L[i] & 0xffff;
++
++ if (accum_cnt <= thresh_accum_cnt)
++ continue;
++
++ /* sum(tx amplitude) */
++ accum_tx = ((data_L[i] >> 16) & 0xffff) |
++ ((data_U[i] & 0x7ff) << 16);
++
++ /* sum(rx amplitude distance to lower bin edge) */
++ accum_rx = ((data_U[i] >> 11) & 0x1f) |
++ ((data_L[i + 23] & 0xffff) << 5);
++
++ /* sum(angles) */
++ accum_ang = ((data_L[i + 23] >> 16) & 0xffff) |
++ ((data_U[i + 23] & 0x7ff) << 16);
++
++ accum_tx <<= scale_factor;
++ accum_rx <<= scale_factor;
++ x_est[i + 1] = (((accum_tx + accum_cnt) / accum_cnt) + 32) >>
++ scale_factor;
++
++ Y[i + 1] = ((((accum_rx + accum_cnt) / accum_cnt) + 32) >>
++ scale_factor) +
++ (1 << scale_factor) * max_index + 16;
++
++ if (accum_ang >= (1 << 26))
++ accum_ang -= 1 << 27;
++
++ theta[i + 1] = ((accum_ang * (1 << scale_factor)) + accum_cnt) /
++ accum_cnt;
++
++ max_index++;
++ }
++
++ /*
++ * Find average theta of first 5 bin and all of those to same value.
++ * Curve is linear at that range.
++ */
++ for (i = 1; i < 6; i++)
++ theta_low_bin += theta[i];
++
++ theta_low_bin = theta_low_bin / 5;
++ for (i = 1; i < 6; i++)
++ theta[i] = theta_low_bin;
++
++ /* Set values at origin */
++ theta[0] = theta_low_bin;
++ for (i = 0; i <= max_index; i++)
++ theta[i] -= theta_low_bin;
++
++ x_est[0] = 0;
++ Y[0] = 0;
++ scale_factor = 8;
++
++ /* low signal gain */
++ if (x_est[6] == x_est[3])
++ return false;
++
++ G_fxp =
++ (((Y[6] - Y[3]) * 1 << scale_factor) +
++ (x_est[6] - x_est[3])) / (x_est[6] - x_est[3]);
++
++ Y_intercept =
++ (G_fxp * (x_est[0] - x_est[3]) +
++ (1 << scale_factor)) / (1 << scale_factor) + Y[3];
++
++ for (i = 0; i <= max_index; i++)
++ y_est[i] = Y[i] - Y_intercept;
++
++ for (i = 0; i <= 3; i++) {
++ y_est[i] = i * 32;
++
++ /* prevent division by zero */
++ if (G_fxp == 0)
++ return false;
++
++ x_est[i] = ((y_est[i] * 1 << scale_factor) + G_fxp) / G_fxp;
++ }
++
++ x_est_fxp1_nonlin =
++ x_est[max_index] - ((1 << scale_factor) * y_est[max_index] +
++ G_fxp) / G_fxp;
++
++ order_x_by_y =
++ (x_est_fxp1_nonlin + y_est[max_index]) / y_est[max_index];
++
++ if (order_x_by_y == 0)
++ M = 10;
++ else if (order_x_by_y == 1)
++ M = 9;
++ else
++ M = 8;
++
++ I = (max_index > 15) ? 7 : max_index >> 1;
++ L = max_index - I;
++ scale_factor = 8;
++ sum_y_sqr = 0;
++ sum_y_quad = 0;
++ x_tilde_abs = 0;
++
++ for (i = 0; i <= L; i++) {
++ unsigned int y_sqr;
++ unsigned int y_quad;
++ unsigned int tmp_abs;
++
++ /* prevent division by zero */
++ if (y_est[i + I] == 0)
++ return false;
++
++ x_est_fxp1_nonlin =
++ x_est[i + I] - ((1 << scale_factor) * y_est[i + I] +
++ G_fxp) / G_fxp;
++
++ x_tilde[i] =
++ (x_est_fxp1_nonlin * (1 << M) + y_est[i + I]) / y_est[i +
++ I];
++ x_tilde[i] =
++ (x_tilde[i] * (1 << M) + y_est[i + I]) / y_est[i + I];
++ x_tilde[i] =
++ (x_tilde[i] * (1 << M) + y_est[i + I]) / y_est[i + I];
++ y_sqr =
++ (y_est[i + I] * y_est[i + I] +
++ (scale_factor * scale_factor)) / (scale_factor *
++ scale_factor);
++ tmp_abs = abs(x_tilde[i]);
++ if (tmp_abs > x_tilde_abs)
++ x_tilde_abs = tmp_abs;
++
++ y_quad = y_sqr * y_sqr;
++ sum_y_sqr = sum_y_sqr + y_sqr;
++ sum_y_quad = sum_y_quad + y_quad;
++ B1_tmp[i] = y_sqr * (L + 1);
++ B2_tmp[i] = y_sqr;
++ }
++
++ B1_abs_max = 0;
++ B2_abs_max = 0;
++ for (i = 0; i <= L; i++) {
++ int abs_val;
++
++ B1_tmp[i] -= sum_y_sqr;
++ B2_tmp[i] = sum_y_quad - sum_y_sqr * B2_tmp[i];
++
++ abs_val = abs(B1_tmp[i]);
++ if (abs_val > B1_abs_max)
++ B1_abs_max = abs_val;
++
++ abs_val = abs(B2_tmp[i]);
++ if (abs_val > B2_abs_max)
++ B2_abs_max = abs_val;
++ }
++
++ Q_x = find_proper_scale(find_expn(x_tilde_abs), 10);
++ Q_B1 = find_proper_scale(find_expn(B1_abs_max), 10);
++ Q_B2 = find_proper_scale(find_expn(B2_abs_max), 10);
++
++ beta_raw = 0;
++ alpha_raw = 0;
++ for (i = 0; i <= L; i++) {
++ x_tilde[i] = x_tilde[i] / (1 << Q_x);
++ B1_tmp[i] = B1_tmp[i] / (1 << Q_B1);
++ B2_tmp[i] = B2_tmp[i] / (1 << Q_B2);
++ beta_raw = beta_raw + B1_tmp[i] * x_tilde[i];
++ alpha_raw = alpha_raw + B2_tmp[i] * x_tilde[i];
++ }
++
++ scale_B =
++ ((sum_y_quad / scale_factor) * (L + 1) -
++ (sum_y_sqr / scale_factor) * sum_y_sqr) * scale_factor;
++
++ Q_scale_B = find_proper_scale(find_expn(abs(scale_B)), 10);
++ scale_B = scale_B / (1 << Q_scale_B);
++ Q_beta = find_proper_scale(find_expn(abs(beta_raw)), 10);
++ Q_alpha = find_proper_scale(find_expn(abs(alpha_raw)), 10);
++ beta_raw = beta_raw / (1 << Q_beta);
++ alpha_raw = alpha_raw / (1 << Q_alpha);
++ alpha = (alpha_raw << 10) / scale_B;
++ beta = (beta_raw << 10) / scale_B;
++ order_1 = 3 * M - Q_x - Q_B1 - Q_beta + 10 + Q_scale_B;
++ order_2 = 3 * M - Q_x - Q_B2 - Q_alpha + 10 + Q_scale_B;
++ order1_5x = order_1 / 5;
++ order2_3x = order_2 / 3;
++ order1_5x_rem = order_1 - 5 * order1_5x;
++ order2_3x_rem = order_2 - 3 * order2_3x;
++
++ for (i = 0; i < PAPRD_TABLE_SZ; i++) {
++ tmp = i * 32;
++ y5 = ((beta * tmp) >> 6) >> order1_5x;
++ y5 = (y5 * tmp) >> order1_5x;
++ y5 = (y5 * tmp) >> order1_5x;
++ y5 = (y5 * tmp) >> order1_5x;
++ y5 = (y5 * tmp) >> order1_5x;
++ y5 = y5 >> order1_5x_rem;
++ y3 = (alpha * tmp) >> order2_3x;
++ y3 = (y3 * tmp) >> order2_3x;
++ y3 = (y3 * tmp) >> order2_3x;
++ y3 = y3 >> order2_3x_rem;
++ PA_in[i] = y5 + y3 + (256 * tmp) / G_fxp;
++
++ if (i >= 2) {
++ tmp = PA_in[i] - PA_in[i - 1];
++ if (tmp < 0)
++ PA_in[i] =
++ PA_in[i - 1] + (PA_in[i - 1] -
++ PA_in[i - 2]);
++ }
++
++ PA_in[i] = (PA_in[i] < 1400) ? PA_in[i] : 1400;
++ }
++
++ beta_raw = 0;
++ alpha_raw = 0;
++
++ for (i = 0; i <= L; i++) {
++ int theta_tilde =
++ ((theta[i + I] << M) + y_est[i + I]) / y_est[i + I];
++ theta_tilde =
++ ((theta_tilde << M) + y_est[i + I]) / y_est[i + I];
++ theta_tilde =
++ ((theta_tilde << M) + y_est[i + I]) / y_est[i + I];
++ beta_raw = beta_raw + B1_tmp[i] * theta_tilde;
++ alpha_raw = alpha_raw + B2_tmp[i] * theta_tilde;
++ }
++
++ Q_beta = find_proper_scale(find_expn(abs(beta_raw)), 10);
++ Q_alpha = find_proper_scale(find_expn(abs(alpha_raw)), 10);
++ beta_raw = beta_raw / (1 << Q_beta);
++ alpha_raw = alpha_raw / (1 << Q_alpha);
++
++ alpha = (alpha_raw << 10) / scale_B;
++ beta = (beta_raw << 10) / scale_B;
++ order_1 = 3 * M - Q_x - Q_B1 - Q_beta + 10 + Q_scale_B + 5;
++ order_2 = 3 * M - Q_x - Q_B2 - Q_alpha + 10 + Q_scale_B + 5;
++ order1_5x = order_1 / 5;
++ order2_3x = order_2 / 3;
++ order1_5x_rem = order_1 - 5 * order1_5x;
++ order2_3x_rem = order_2 - 3 * order2_3x;
++
++ for (i = 0; i < PAPRD_TABLE_SZ; i++) {
++ int PA_angle;
++
++ /* pa_table[4] is calculated from PA_angle for i=5 */
++ if (i == 4)
++ continue;
++
++ tmp = i * 32;
++ if (beta > 0)
++ y5 = (((beta * tmp - 64) >> 6) -
++ (1 << order1_5x)) / (1 << order1_5x);
++ else
++ y5 = ((((beta * tmp - 64) >> 6) +
++ (1 << order1_5x)) / (1 << order1_5x));
++
++ y5 = (y5 * tmp) / (1 << order1_5x);
++ y5 = (y5 * tmp) / (1 << order1_5x);
++ y5 = (y5 * tmp) / (1 << order1_5x);
++ y5 = (y5 * tmp) / (1 << order1_5x);
++ y5 = y5 / (1 << order1_5x_rem);
++
++ if (beta > 0)
++ y3 = (alpha * tmp -
++ (1 << order2_3x)) / (1 << order2_3x);
++ else
++ y3 = (alpha * tmp +
++ (1 << order2_3x)) / (1 << order2_3x);
++ y3 = (y3 * tmp) / (1 << order2_3x);
++ y3 = (y3 * tmp) / (1 << order2_3x);
++ y3 = y3 / (1 << order2_3x_rem);
++
++ if (i < 4) {
++ PA_angle = 0;
++ } else {
++ PA_angle = y5 + y3;
++ if (PA_angle < -150)
++ PA_angle = -150;
++ else if (PA_angle > 150)
++ PA_angle = 150;
++ }
++
++ pa_table[i] = ((PA_in[i] & 0x7ff) << 11) + (PA_angle & 0x7ff);
++ if (i == 5) {
++ PA_angle = (PA_angle + 2) >> 1;
++ pa_table[i - 1] = ((PA_in[i - 1] & 0x7ff) << 11) +
++ (PA_angle & 0x7ff);
++ }
++ }
++
++ *gain = G_fxp;
++ return true;
++}
++
++void ar9003_paprd_populate_single_table(struct ath_hw *ah,
++ struct ath9k_channel *chan, int chain)
++{
++ u32 *paprd_table_val = chan->pa_table[chain];
++ u32 small_signal_gain = chan->small_signal_gain[chain];
++ u32 training_power;
++ u32 reg = 0;
++ int i;
++
++ training_power =
++ REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE5,
++ AR_PHY_POWERTX_RATE5_POWERTXHT20_0);
++ training_power -= 4;
++
++ if (chain == 0)
++ reg = AR_PHY_PAPRD_MEM_TAB_B0;
++ else if (chain == 1)
++ reg = AR_PHY_PAPRD_MEM_TAB_B1;
++ else if (chain == 2)
++ reg = AR_PHY_PAPRD_MEM_TAB_B2;
++
++ for (i = 0; i < PAPRD_TABLE_SZ; i++) {
++ REG_WRITE(ah, reg, paprd_table_val[i]);
++ reg = reg + 4;
++ }
++
++ if (chain == 0)
++ reg = AR_PHY_PA_GAIN123_B0;
++ else if (chain == 1)
++ reg = AR_PHY_PA_GAIN123_B1;
++ else
++ reg = AR_PHY_PA_GAIN123_B2;
++
++ REG_RMW_FIELD(ah, reg, AR_PHY_PA_GAIN123_PA_GAIN1, small_signal_gain);
++
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B0,
++ AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL,
++ training_power);
++
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B1,
++ AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL,
++ training_power);
++
++ REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B2,
++ AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL,
++ training_power);
++}
++EXPORT_SYMBOL(ar9003_paprd_populate_single_table);
++
++int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain)
++{
++
++ unsigned int i, desired_gain, gain_index;
++ unsigned int train_power;
++
++ train_power = REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE5,
++ AR_PHY_POWERTX_RATE5_POWERTXHT20_0);
++
++ train_power = train_power - 4;
++
++ desired_gain = ar9003_get_desired_gain(ah, chain, train_power);
++
++ gain_index = 0;
++ for (i = 0; i < 32; i++) {
++ if (ah->paprd_gain_table_index[i] >= desired_gain)
++ break;
++ gain_index++;
++ }
++
++ ar9003_tx_force_gain(ah, gain_index);
++
++ REG_CLR_BIT(ah, AR_PHY_PAPRD_TRAINER_STAT1,
++ AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE);
++
++ return 0;
++}
++EXPORT_SYMBOL(ar9003_paprd_setup_gain_table);
++
++int ar9003_paprd_create_curve(struct ath_hw *ah, struct ath9k_channel *chan,
++ int chain)
++{
++ u16 *small_signal_gain = &chan->small_signal_gain[chain];
++ u32 *pa_table = chan->pa_table[chain];
++ u32 *data_L, *data_U;
++ int i, status = 0;
++ u32 *buf;
++ u32 reg;
++
++ memset(chan->pa_table[chain], 0, sizeof(chan->pa_table[chain]));
++
++ buf = kmalloc(2 * 48 * sizeof(u32), GFP_ATOMIC);
++ if (!buf)
++ return -ENOMEM;
++
++ data_L = &buf[0];
++ data_U = &buf[48];
++
++ REG_CLR_BIT(ah, AR_PHY_CHAN_INFO_MEMORY,
++ AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ);
++
++ reg = AR_PHY_CHAN_INFO_TAB_0;
++ for (i = 0; i < 48; i++)
++ data_L[i] = REG_READ(ah, reg + (i << 2));
++
++ REG_SET_BIT(ah, AR_PHY_CHAN_INFO_MEMORY,
++ AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ);
++
++ for (i = 0; i < 48; i++)
++ data_U[i] = REG_READ(ah, reg + (i << 2));
++
++ if (!create_pa_curve(data_L, data_U, pa_table, small_signal_gain))
++ status = -2;
++
++ REG_CLR_BIT(ah, AR_PHY_PAPRD_TRAINER_STAT1,
++ AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE);
++
++ kfree(buf);
++
++ return status;
++}
++EXPORT_SYMBOL(ar9003_paprd_create_curve);
++
++int ar9003_paprd_init_table(struct ath_hw *ah)
++{
++ ar9003_paprd_setup_single_table(ah);
++ ar9003_paprd_get_gain_table(ah);
++ return 0;
++}
++EXPORT_SYMBOL(ar9003_paprd_init_table);
++
++bool ar9003_paprd_is_done(struct ath_hw *ah)
++{
++ return !!REG_READ_FIELD(ah, AR_PHY_PAPRD_TRAINER_STAT1,
++ AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE);
++}
++EXPORT_SYMBOL(ar9003_paprd_is_done);
+diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
+index 9d09216..d60472b 100644
+--- a/drivers/net/wireless/ath/ath9k/hw.h
++++ b/drivers/net/wireless/ath/ath9k/hw.h
+@@ -158,6 +158,9 @@
+ #define ATH9K_HW_RX_HP_QDEPTH 16
+ #define ATH9K_HW_RX_LP_QDEPTH 128
+
++#define PAPRD_GAIN_TABLE_ENTRIES 32
++#define PAPRD_TABLE_SZ 24
++
+ enum ath_ini_subsys {
+ ATH_INI_PRE = 0,
+ ATH_INI_CORE,
+@@ -361,6 +364,9 @@ struct ath9k_channel {
+ int8_t iCoff;
+ int8_t qCoff;
+ int16_t rawNoiseFloor;
++ bool paprd_done;
++ u16 small_signal_gain[AR9300_MAX_CHAINS];
++ u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
+ };
+
+ #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
+@@ -819,6 +825,9 @@ struct ath_hw {
+
+ u32 bb_watchdog_last_status;
+ u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
++
++ u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
++ u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
+ };
+
+ static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
+@@ -946,6 +955,15 @@ void ar9003_hw_set_nf_limits(struct ath_hw *ah);
+ void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
+ void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
+ void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
++void ar9003_paprd_enable(struct ath_hw *ah, bool val);
++void ar9003_paprd_populate_single_table(struct ath_hw *ah,
++ struct ath9k_channel *chan, int chain);
++int ar9003_paprd_create_curve(struct ath_hw *ah, struct ath9k_channel *chan,
++ int chain);
++int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
++int ar9003_paprd_init_table(struct ath_hw *ah);
++bool ar9003_paprd_is_done(struct ath_hw *ah);
++void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains);
+
+ /* Hardware family op attach helpers */
+ void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
+--
+1.6.3.3
+
--- /dev/null
+From eacffd4dd6dee913b154ffd10f0341d41a6fe900 Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@openwrt.org>
+Date: Thu, 10 Jun 2010 22:22:48 +0200
+Subject: [PATCH 23/24] ath9k: implement PA predistortion support
+
+Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
+---
+ drivers/net/wireless/ath/ath9k/ath9k.h | 7 ++
+ drivers/net/wireless/ath/ath9k/init.c | 1 +
+ drivers/net/wireless/ath/ath9k/main.c | 116 ++++++++++++++++++++++++++++++++
+ drivers/net/wireless/ath/ath9k/xmit.c | 16 ++++-
+ 4 files changed, 137 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
+index 1a19aea..8d163ae 100644
+--- a/drivers/net/wireless/ath/ath9k/ath9k.h
++++ b/drivers/net/wireless/ath/ath9k/ath9k.h
+@@ -20,6 +20,7 @@
+ #include <linux/etherdevice.h>
+ #include <linux/device.h>
+ #include <linux/leds.h>
++#include <linux/completion.h>
+
+ #include "debug.h"
+ #include "common.h"
+@@ -224,6 +225,7 @@ struct ath_buf_state {
+ int bfs_tidno;
+ int bfs_retries;
+ u8 bf_type;
++ u8 bfs_paprd;
+ u32 bfs_keyix;
+ enum ath9k_key_type bfs_keytype;
+ };
+@@ -280,6 +282,7 @@ struct ath_tx_control {
+ struct ath_txq *txq;
+ int if_id;
+ enum ath9k_internal_frame_type frame_type;
++ u8 paprd;
+ };
+
+ #define ATH_TX_ERROR 0x01
+@@ -422,6 +425,7 @@ int ath_beaconq_config(struct ath_softc *sc);
+ #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */
+ #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
+
++void ath_paprd_calibrate(struct work_struct *work);
+ void ath_ani_calibrate(unsigned long data);
+
+ /**********/
+@@ -553,6 +557,9 @@ struct ath_softc {
+ spinlock_t sc_serial_rw;
+ spinlock_t sc_pm_lock;
+ struct mutex mutex;
++ struct work_struct paprd_work;
++ struct completion paprd_complete;
++ int paprd_txok;
+
+ u32 intrstatus;
+ u32 sc_flags; /* SC_OP_* */
+diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
+index 4e07830..e1fa268 100644
+--- a/drivers/net/wireless/ath/ath9k/init.c
++++ b/drivers/net/wireless/ath/ath9k/init.c
+@@ -736,6 +736,7 @@ int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
+ goto error_world;
+ }
+
++ INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
+ INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
+ INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
+ sc->wiphy_scheduler_int = msecs_to_jiffies(500);
+diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
+index 52ed4c8..7b2f4a7 100644
+--- a/drivers/net/wireless/ath/ath9k/main.c
++++ b/drivers/net/wireless/ath/ath9k/main.c
+@@ -232,6 +232,113 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
+ return r;
+ }
+
++static void ath_paprd_activate(struct ath_softc *sc)
++{
++ struct ath_hw *ah = sc->sc_ah;
++ int chain;
++
++ if (!ah->curchan->paprd_done)
++ return;
++
++ ath9k_ps_wakeup(sc);
++ for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
++ if (!(ah->caps.tx_chainmask & BIT(chain)))
++ continue;
++
++ ar9003_paprd_populate_single_table(ah, ah->curchan, chain);
++ }
++
++ ar9003_paprd_enable(ah, true);
++ ath9k_ps_restore(sc);
++}
++
++void ath_paprd_calibrate(struct work_struct *work)
++{
++ struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
++ struct ieee80211_hw *hw = sc->hw;
++ struct ath_hw *ah = sc->sc_ah;
++ struct ieee80211_hdr *hdr;
++ struct sk_buff *skb = NULL;
++ struct ieee80211_tx_info *tx_info;
++ int band = hw->conf.channel->band;
++ struct ieee80211_supported_band *sband = &sc->sbands[band];
++ struct ath_tx_control txctl;
++ int qnum, ftype;
++ int chain_ok = 0;
++ int chain;
++ int len = 1800;
++ int time_left;
++ int i;
++
++ ath9k_ps_wakeup(sc);
++ skb = alloc_skb(len, GFP_KERNEL);
++ if (!skb)
++ return;
++
++ tx_info = IEEE80211_SKB_CB(skb);
++
++ skb_put(skb, len);
++ memset(skb->data, 0, len);
++ hdr = (struct ieee80211_hdr *)skb->data;
++ ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
++ hdr->frame_control = cpu_to_le16(ftype);
++ hdr->duration_id = 10;
++ memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
++ memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
++ memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
++
++ memset(&txctl, 0, sizeof(txctl));
++ qnum = sc->tx.hwq_map[WME_AC_BE];
++ txctl.txq = &sc->tx.txq[qnum];
++
++ ar9003_paprd_init_table(ah);
++ for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
++ if (!(ah->caps.tx_chainmask & BIT(chain)))
++ continue;
++
++ chain_ok = 0;
++ memset(tx_info, 0, sizeof(*tx_info));
++ tx_info->band = band;
++
++ for (i = 0; i < 4; i++) {
++ tx_info->control.rates[i].idx = sband->n_bitrates - 1;
++ tx_info->control.rates[i].count = 6;
++ }
++
++ init_completion(&sc->paprd_complete);
++ ar9003_paprd_setup_gain_table(ah, chain);
++ txctl.paprd = BIT(chain);
++ if (ath_tx_start(hw, skb, &txctl) != 0)
++ break;
++
++ time_left = wait_for_completion_timeout(&sc->paprd_complete,
++ 100);
++ if (!time_left) {
++ ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
++ "Timeout waiting for paprd training on "
++ "TX chain %d\n",
++ chain);
++ break;
++ }
++
++ if (!ar9003_paprd_is_done(ah))
++ break;
++
++ if (ar9003_paprd_create_curve(ah, ah->curchan, chain) != 0)
++ break;
++
++ chain_ok = 1;
++ }
++ kfree_skb(skb);
++
++ if (chain_ok) {
++ ah->curchan->paprd_done = true;
++ ath_paprd_activate(sc);
++ }
++
++ ath9k_ps_restore(sc);
++}
++
+ /*
+ * This routine performs the periodic noise floor calibration function
+ * that is used to adjust and optimize the chip performance. This
+@@ -333,6 +440,13 @@ set_timer:
+ cal_interval = min(cal_interval, (u32)short_cal_interval);
+
+ mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
++ if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) &&
++ !(sc->sc_flags & SC_OP_SCANNING)) {
++ if (!sc->sc_ah->curchan->paprd_done)
++ ieee80211_queue_work(sc->hw, &sc->paprd_work);
++ else
++ ath_paprd_activate(sc);
++ }
+ }
+
+ static void ath_start_ani(struct ath_common *common)
+@@ -1131,6 +1245,7 @@ static void ath9k_stop(struct ieee80211_hw *hw)
+
+ cancel_delayed_work_sync(&sc->ath_led_blink_work);
+ cancel_delayed_work_sync(&sc->tx_complete_work);
++ cancel_work_sync(&sc->paprd_work);
+
+ if (!sc->num_sec_wiphy) {
+ cancel_delayed_work_sync(&sc->wiphy_work);
+@@ -1846,6 +1961,7 @@ static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
+ ath9k_wiphy_pause_all_forced(sc, aphy);
+ sc->sc_flags |= SC_OP_SCANNING;
+ del_timer_sync(&common->ani.timer);
++ cancel_work_sync(&sc->paprd_work);
+ cancel_delayed_work_sync(&sc->tx_complete_work);
+ mutex_unlock(&sc->mutex);
+ }
+diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
+index 875b8b4..20221b8 100644
+--- a/drivers/net/wireless/ath/ath9k/xmit.c
++++ b/drivers/net/wireless/ath/ath9k/xmit.c
+@@ -1637,12 +1637,13 @@ static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
+ bf->bf_frmlen -= padsize;
+ }
+
+- if (conf_is_ht(&hw->conf)) {
++ if (!txctl->paprd && conf_is_ht(&hw->conf)) {
+ bf->bf_state.bf_type |= BUF_HT;
+ if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
+ use_ldpc = true;
+ }
+
++ bf->bf_state.bfs_paprd = txctl->paprd;
+ bf->bf_flags = setup_tx_flags(skb, use_ldpc);
+
+ bf->bf_keytype = get_hw_crypto_keytype(skb);
+@@ -1717,6 +1718,9 @@ static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
+ bf->bf_buf_addr,
+ txctl->txq->axq_qnum);
+
++ if (bf->bf_state.bfs_paprd)
++ ar9003_hw_set_paprd_txdesc(ah, ds, bf->bf_state.bfs_paprd);
++
+ spin_lock_bh(&txctl->txq->axq_lock);
+
+ if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) &&
+@@ -1938,8 +1942,14 @@ static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
+ }
+
+ dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE);
+- ath_tx_complete(sc, skb, bf->aphy, tx_flags);
+- ath_debug_stat_tx(sc, txq, bf, ts);
++
++ if (bf->bf_state.bfs_paprd) {
++ sc->paprd_txok = txok;
++ complete(&sc->paprd_complete);
++ } else {
++ ath_tx_complete(sc, skb, bf->aphy, tx_flags);
++ ath_debug_stat_tx(sc, txq, bf, ts);
++ }
+
+ /*
+ * Return the list of ath_buf of this mpdu to free queue
+--
+1.6.3.3
+
--- /dev/null
+From 8a4a872a0dd99a80ffefbbfb3d99be1e2a068859 Mon Sep 17 00:00:00 2001
+From: Luis R. Rodriguez <lrodriguez@atheros.com>
+Date: Thu, 13 May 2010 17:33:23 -0700
+Subject: [PATCH 24/24] ath9k: enable AR9003 PCI IDs
+
+All AR9003 features are now complete so enable AR9003
+support.
+
+Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
+---
+ drivers/net/wireless/ath/ath9k/pci.c | 1 +
+ 1 files changed, 1 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
+index 1ec836c..257b10b 100644
+--- a/drivers/net/wireless/ath/ath9k/pci.c
++++ b/drivers/net/wireless/ath/ath9k/pci.c
+@@ -28,6 +28,7 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
+ { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
+ { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */
+ { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
++ { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */
+ { 0 }
+ };
+
+--
+1.6.3.3
+
projects / openwrt / staging / blogic.git / commitdiff