MIPS: Netlogic: Avoid unnecessary cache flushes

XLR dcache is fully coherent across CPUs, so avoid unnecessary dcache
flushes.

Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2729/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
index 3b728275b9b0bf1a004fdf40bacf119650f9428e..3780743a74b23e0014b7003feb91fa33759e71b8 100644 (file)
--- a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
@@ -25,13 +25,12 @@
 #define cpu_has_llsc           1
 #define cpu_has_vtag_icache    0
 #define cpu_has_dc_aliases     0
-#define cpu_has_ic_fills_f_dc  0
+#define cpu_has_ic_fills_f_dc  1
 #define cpu_has_dsp            0
 #define cpu_has_mipsmt         0
 #define cpu_has_userlocal      0
-#define cpu_icache_snoops_remote_store 0
+#define cpu_icache_snoops_remote_store 1
 
-#define cpu_has_nofpuex                0
 #define cpu_has_64bits         1
 
 #define cpu_has_mips32r1       1