Merge branches 'acpi-bus', 'acpi-button', 'acpi-sysfs' and 'acpi-misc'

* acpi-bus:
  ACPI: bus: Fix NULL pointer check in acpi_bus_get_private_data()

* acpi-button:
  ACPI: button: Add DMI quirk for Acer Switch 10 SW5-032 lid-switch

* acpi-sysfs:
  ACPI: sysfs: Change ACPI_MASKABLE_GPE_MAX to 0x100

* acpi-misc:
  ACPI: Fix Kconfig indentation

diff --cc Documentation/admin-guide/kernel-parameters.txt
index 122f2d2f3e96bf800043b0bca1b1efa72977c327,122f2d2f3e96bf800043b0bca1b1efa72977c327,a84a83f8881e08bf0d0d598bb01814be0ec18647,02724bd017cc8fee31b933bc489a540f984a51c4,122f2d2f3e96bf800043b0bca1b1efa72977c327..9c23934c28a9e601accb23598f8e4233b4f5ab9c
--- 1/Documentation/admin-guide/kernel-parameters.txt
--- 2/Documentation/admin-guide/kernel-parameters.txt
--- 3/Documentation/admin-guide/kernel-parameters.txt
--- 4/Documentation/admin-guide/kernel-parameters.txt
--- 5/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@@@@@ -4894,76 -4894,76 -4848,6 -4875,71 -4894,76 +4894,76 @@@@@@
                        interruptions from clocksource watchdog are not
                        acceptable).
     
  +     tsx=            [X86] Control Transactional Synchronization
  +                     Extensions (TSX) feature in Intel processors that
  +                     support TSX control.
  +  
  +                     This parameter controls the TSX feature. The options are:
  +  
  +                     on      - Enable TSX on the system. Although there are
  +                             mitigations for all known security vulnerabilities,
  +                             TSX has been known to be an accelerator for
  +                             several previous speculation-related CVEs, and
  +                             so there may be unknown security risks associated
  +                             with leaving it enabled.
  +  
  +                     off     - Disable TSX on the system. (Note that this
  +                             option takes effect only on newer CPUs which are
  +                             not vulnerable to MDS, i.e., have
  +                             MSR_IA32_ARCH_CAPABILITIES.MDS_NO=1 and which get
  +                             the new IA32_TSX_CTRL MSR through a microcode
  +                             update. This new MSR allows for the reliable
  +                             deactivation of the TSX functionality.)
  +  
  +                     auto    - Disable TSX if X86_BUG_TAA is present,
  +                               otherwise enable TSX on the system.
  +  
  +                     Not specifying this option is equivalent to tsx=off.
  +  
  +                     See Documentation/admin-guide/hw-vuln/tsx_async_abort.rst
  +                     for more details.
  +  
  +     tsx_async_abort= [X86,INTEL] Control mitigation for the TSX Async
  +                     Abort (TAA) vulnerability.
  +  
  +                     Similar to Micro-architectural Data Sampling (MDS)
  +                     certain CPUs that support Transactional
  +                     Synchronization Extensions (TSX) are vulnerable to an
  +                     exploit against CPU internal buffers which can forward
  +                     information to a disclosure gadget under certain
  +                     conditions.
  +  
  +                     In vulnerable processors, the speculatively forwarded
  +                     data can be used in a cache side channel attack, to
  +                     access data to which the attacker does not have direct
  +                     access.
  +  
  +                     This parameter controls the TAA mitigation.  The
  +                     options are:
  +  
  +                     full       - Enable TAA mitigation on vulnerable CPUs
  +                                  if TSX is enabled.
  +  
  +                     full,nosmt - Enable TAA mitigation and disable SMT on
  +                                  vulnerable CPUs. If TSX is disabled, SMT
  +                                  is not disabled because CPU is not
  +                                  vulnerable to cross-thread TAA attacks.
  +                     off        - Unconditionally disable TAA mitigation
  +  
  ++                    On MDS-affected machines, tsx_async_abort=off can be
  ++                    prevented by an active MDS mitigation as both vulnerabilities
  ++                    are mitigated with the same mechanism so in order to disable
  ++                    this mitigation, you need to specify mds=off too.
  ++ 
  +                     Not specifying this option is equivalent to
  +                     tsx_async_abort=full.  On CPUs which are MDS affected
  +                     and deploy MDS mitigation, TAA mitigation is not
  +                     required and doesn't provide any additional
  +                     mitigation.
  +  
  +                     For details see:
  +                     Documentation/admin-guide/hw-vuln/tsx_async_abort.rst
  +  
        turbografx.map[2|3]=    [HW,JOY]
                        TurboGraFX parallel port interface
                        Format: