Introduce arm_setup_page_tables() function

This patch introduces the arm_setup_page_tables() function to
set up page tables on ARM platforms. It replaces the
arm_configure_mmu_elx() functions and does the same thing except
that it doesn't enable the MMU at the end. The idea is to reduce
the amount of per-EL code that is generated by the C preprocessor
by splitting the memory regions definitions and page tables creation
(which is generic) from the MMU enablement (which is the only per-EL
configuration).

As a consequence, the call to the enable_mmu_elx() function has been
moved up into the plat_arch_setup() hook. Any other ARM standard
platforms that use the functions `arm_configure_mmu_elx()` must be
updated.

Change-Id: I6f12a20ce4e5187b3849a8574aac841a136de83d

diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index 2fe0a6905e6920b594a25e11dd71fe85541d0731..3cee6ff0d6af625f151a86f107a9016eadd55dde 100644 (file)
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -45,17 +45,7 @@
 /*
  * Utility functions common to ARM standard platforms
  */
-
-void arm_configure_mmu_el1(unsigned long total_base,
-                       unsigned long total_size,
-                       unsigned long ro_start,
-                       unsigned long ro_limit
-#if USE_COHERENT_MEM
-                       , unsigned long coh_start,
-                       unsigned long coh_limit
-#endif
-);
-void arm_configure_mmu_el3(unsigned long total_base,
+void arm_setup_page_tables(unsigned long total_base,
                        unsigned long total_size,
                        unsigned long ro_start,
                        unsigned long ro_limit

diff --git a/plat/arm/board/common/board_css_common.c b/plat/arm/board/common/board_css_common.c
index 62253f8c47535c0f020ad6a28fb10f603704ae2e..69b744d97386707508573ffb1d71deaab9c3d345 100644 (file)
--- a/plat/arm/board/common/board_css_common.c
+++ b/plat/arm/board/common/board_css_common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -31,9 +31,9 @@
 #include <plat_arm.h>
 
 /*
- * Table of regions for different BL stages to map using the MMU.
- * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
- * arm_configure_mmu_elx() will give the available subset of that,
+ * Table of memory regions for different BL stages to map using the MMU.
+ * This doesn't include Trusted SRAM as arm_setup_page_tables() already
+ * takes care of mapping it.
  */
 #if IMAGE_BL1
 const mmap_region_t plat_arm_mmap[] = {

diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index 0f557af243497afd870689d19914a185d16d51e0..affd0b8273b5508902ba24cb31c2f24b625856b3 100644 (file)
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -66,9 +66,9 @@ arm_config_t arm_config;
 
 
 /*
- * Table of regions for various BL stages to map using the MMU.
- * This doesn't include TZRAM as the 'mem_layout' argument passed to
- * arm_configure_mmu_elx() will give the available subset of that,
+ * Table of memory regions for various BL stages to map using the MMU.
+ * This doesn't include Trusted SRAM as arm_setup_page_tables() already
+ * takes care of mapping it.
  */
 #if IMAGE_BL1
 const mmap_region_t plat_arm_mmap[] = {

diff --git a/plat/arm/common/aarch64/arm_common.c b/plat/arm/common/aarch64/arm_common.c
index c4cc80e6de031eea63c525e9e2f331fcec6d9244..c0a7e6b47ad58c7d37a785b9d4ca519f4f2477e2 100644 (file)
--- a/plat/arm/common/aarch64/arm_common.c
+++ b/plat/arm/common/aarch64/arm_common.c
@@ -50,57 +50,48 @@ extern const mmap_region_t plat_arm_mmap[];
 #pragma weak plat_get_syscnt_freq
 #endif
 
-/*******************************************************************************
- * Macro generating the code for the function setting up the pagetables as per
- * the platform memory map & initialize the mmu, for the given exception level
- ******************************************************************************/
+/*
+ * Set up the page tables for the generic and platform-specific memory regions.
+ * The extents of the generic memory regions are specified by the function
+ * arguments and consist of:
+ * - Trusted SRAM seen by the BL image;
+ * - Read-only section (code and read-only data);
+ * - Coherent memory region, if applicable.
+ */
+void arm_setup_page_tables(unsigned long total_base,
+                          unsigned long total_size,
+                          unsigned long ro_start,
+                          unsigned long ro_limit
 #if USE_COHERENT_MEM
-#define DEFINE_CONFIGURE_MMU_EL(_el)                                   \
-       void arm_configure_mmu_el##_el(unsigned long total_base,        \
-                                  unsigned long total_size,            \
-                                  unsigned long ro_start,              \
-                                  unsigned long ro_limit,              \
-                                  unsigned long coh_start,             \
-                                  unsigned long coh_limit)             \
-       {                                                               \
-               mmap_add_region(total_base, total_base,                 \
-                               total_size,                             \
-                               MT_MEMORY | MT_RW | MT_SECURE);         \
-               mmap_add_region(ro_start, ro_start,                     \
-                               ro_limit - ro_start,                    \
-                               MT_MEMORY | MT_RO | MT_SECURE);         \
-               mmap_add_region(coh_start, coh_start,                   \
-                               coh_limit - coh_start,                  \
-                               MT_DEVICE | MT_RW | MT_SECURE);         \
-               mmap_add(plat_arm_get_mmap());                          \
-               init_xlat_tables();                                     \
-                                                                       \
-               enable_mmu_el##_el(0);                                  \
-       }
-#else
-#define DEFINE_CONFIGURE_MMU_EL(_el)                                   \
-       void arm_configure_mmu_el##_el(unsigned long total_base,        \
-                                  unsigned long total_size,            \
-                                  unsigned long ro_start,              \
-                                  unsigned long ro_limit)              \
-       {                                                               \
-               mmap_add_region(total_base, total_base,                 \
-                               total_size,                             \
-                               MT_MEMORY | MT_RW | MT_SECURE);         \
-               mmap_add_region(ro_start, ro_start,                     \
-                               ro_limit - ro_start,                    \
-                               MT_MEMORY | MT_RO | MT_SECURE);         \
-               mmap_add(plat_arm_get_mmap());                          \
-               init_xlat_tables();                                     \
-                                                                       \
-               enable_mmu_el##_el(0);                                  \
-       }
+                          ,
+                          unsigned long coh_start,
+                          unsigned long coh_limit
 #endif
+                          )
+{
+       /*
+        * Map the Trusted SRAM with appropriate memory attributes.
+        * Subsequent mappings will adjust the attributes for specific regions.
+        */
+       mmap_add_region(total_base, total_base,
+                       total_size,
+                       MT_MEMORY | MT_RW | MT_SECURE);
+       /* Re-map the read-only section */
+       mmap_add_region(ro_start, ro_start,
+                       ro_limit - ro_start,
+                       MT_MEMORY | MT_RO | MT_SECURE);
+#if USE_COHERENT_MEM
+       /* Re-map the coherent memory region */
+       mmap_add_region(coh_start, coh_start,
+                       coh_limit - coh_start,
+                       MT_DEVICE | MT_RW | MT_SECURE);
+#endif
+       /* Now (re-)map the platform-specific memory regions */
+       mmap_add(plat_arm_get_mmap());
 
-/* Define EL1 and EL3 variants of the function initialising the MMU */
-DEFINE_CONFIGURE_MMU_EL(1)
-DEFINE_CONFIGURE_MMU_EL(3)
-
+       /* Create the page tables to reflect the above mappings */
+       init_xlat_tables();
+}
 
 uintptr_t plat_get_ns_image_entrypoint(void)
 {

diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c
index 951f48a5b76d0bb47725c98cf2894c824a0c9344..1ffd7ee2ccd9c6c22e5484025f4f1ee40d3c3eab 100644 (file)
--- a/plat/arm/common/arm_bl1_setup.c
+++ b/plat/arm/common/arm_bl1_setup.c
@@ -118,7 +118,7 @@ void bl1_early_platform_setup(void)
  *****************************************************************************/
 void arm_bl1_plat_arch_setup(void)
 {
-       arm_configure_mmu_el3(bl1_tzram_layout.total_base,
+       arm_setup_page_tables(bl1_tzram_layout.total_base,
                              bl1_tzram_layout.total_size,
                              BL1_RO_BASE,
                              BL1_RO_LIMIT
@@ -127,6 +127,7 @@ void arm_bl1_plat_arch_setup(void)
                              BL1_COHERENT_RAM_LIMIT
 #endif
                             );
+       enable_mmu_el3(0);
 }
 
 void bl1_plat_arch_setup(void)

diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index 681dc8adf8bfe406c3c439d6438c4d44a919429b..e8e7928c02d5af5b833a1fdfed38d17716e57359 100644 (file)
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -234,7 +234,7 @@ void bl2_platform_setup(void)
  ******************************************************************************/
 void arm_bl2_plat_arch_setup(void)
 {
-       arm_configure_mmu_el1(bl2_tzram_layout.total_base,
+       arm_setup_page_tables(bl2_tzram_layout.total_base,
                              bl2_tzram_layout.total_size,
                              BL2_RO_BASE,
                              BL2_RO_LIMIT
@@ -243,6 +243,7 @@ void arm_bl2_plat_arch_setup(void)
                              BL2_COHERENT_RAM_LIMIT
 #endif
                              );
+       enable_mmu_el1(0);
 }
 
 void bl2_plat_arch_setup(void)

diff --git a/plat/arm/common/arm_bl2u_setup.c b/plat/arm/common/arm_bl2u_setup.c
index 5b7354b3ebc13eab1546c7e97e167d13deb74ba0..5f2634a2fe61e685c2da35eb0d9121da8761ac6f 100644 (file)
--- a/plat/arm/common/arm_bl2u_setup.c
+++ b/plat/arm/common/arm_bl2u_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -102,7 +102,7 @@ void bl2u_early_platform_setup(meminfo_t *mem_layout, void *plat_info)
  ******************************************************************************/
 void arm_bl2u_plat_arch_setup(void)
 {
-       arm_configure_mmu_el1(BL2U_RO_LIMIT,
+       arm_setup_page_tables(BL2U_RO_LIMIT,
                              BL31_LIMIT,
                              BL2U_RO_BASE,
                              BL2U_RO_LIMIT
@@ -112,6 +112,7 @@ void arm_bl2u_plat_arch_setup(void)
                              BL2U_COHERENT_RAM_LIMIT
 #endif
                );
+       enable_mmu_el1(0);
 }
 
 void bl2u_plat_arch_setup(void)

diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index 8eb681802ccb8544ad946e2ad801f1f07c28a284..9cfa3b8b7d1ead6e3b2672f5945fb6e8dc5091b4 100644 (file)
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -246,12 +246,14 @@ void bl31_plat_runtime_setup(void)
 }
 
 /*******************************************************************************
- * Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the mmu in a quick and dirty way.
+ * Perform the very early platform specific architectural setup shared between
+ * ARM standard platforms. This only does basic initialization. Later
+ * architectural setup (bl31_arch_setup()) does not do anything platform
+ * specific.
  ******************************************************************************/
 void arm_bl31_plat_arch_setup(void)
 {
-       arm_configure_mmu_el3(BL31_RO_BASE,
+       arm_setup_page_tables(BL31_RO_BASE,
                              (BL31_END - BL31_RO_BASE),
                              BL31_RO_BASE,
                              BL31_RO_LIMIT
@@ -260,6 +262,7 @@ void arm_bl31_plat_arch_setup(void)
                              BL31_COHERENT_RAM_LIMIT
 #endif
                              );
+       enable_mmu_el3(0);
 }
 
 void bl31_plat_arch_setup(void)

diff --git a/plat/arm/common/tsp/arm_tsp_setup.c b/plat/arm/common/tsp/arm_tsp_setup.c
index 2a67fd10256c4e098e2e59baee0b8917bf646ad2..6c6ceea0816e4798720feacf03d916c81b1d2858 100644 (file)
--- a/plat/arm/common/tsp/arm_tsp_setup.c
+++ b/plat/arm/common/tsp/arm_tsp_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -98,7 +98,7 @@ void tsp_platform_setup(void)
  ******************************************************************************/
 void tsp_plat_arch_setup(void)
 {
-       arm_configure_mmu_el1(BL32_RO_BASE,
+       arm_setup_page_tables(BL32_RO_BASE,
                              (BL32_END - BL32_RO_BASE),
                              BL32_RO_BASE,
                              BL32_RO_LIMIT
@@ -107,4 +107,5 @@ void tsp_plat_arch_setup(void)
                              BL32_COHERENT_RAM_LIMIT
 #endif
                              );
+       enable_mmu_el1(0);
 }

diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
index 6f1a18b102deb8b56c5ec1db812f0ff133d3ed22..2ea8b1c982dad835c1f2ab211bcbd51e913733d2 100644 (file)
--- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
+++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
@@ -147,18 +147,18 @@ void bl31_plat_runtime_setup(void)
 }
 
 /*
- * Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the MMU in a quick and dirty way.
+ * Perform the very early platform specific architectural setup here.
  */
 void bl31_plat_arch_setup(void)
 {
        plat_arm_interconnect_init();
        plat_arm_interconnect_enter_coherency();
 
-       arm_configure_mmu_el3(BL31_RO_BASE,
+       arm_setup_page_tables(BL31_RO_BASE,
                              BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE,
                              BL31_RO_BASE,
                              BL31_RO_LIMIT,
                              BL31_COHERENT_RAM_BASE,
                              BL31_COHERENT_RAM_LIMIT);
+       enable_mmu_el3(0);
 }

diff --git a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
index 58a3e2a18d6e89031c9a3757786befcfaf9fb9a0..19e2c12987a304c7b21f708e23e4f60bc4ee6260 100644 (file)
--- a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
+++ b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -90,7 +90,7 @@ void tsp_platform_setup(void)
  ******************************************************************************/
 void tsp_plat_arch_setup(void)
 {
-       arm_configure_mmu_el1(BL32_RO_BASE,
+       arm_setup_page_tables(BL32_RO_BASE,
                              (BL32_END - BL32_RO_BASE),
                              BL32_RO_BASE,
                              BL32_RO_LIMIT
@@ -99,4 +99,5 @@ void tsp_plat_arch_setup(void)
                              BL32_COHERENT_RAM_LIMIT
 #endif
                              );
+       enable_mmu_el1(0);
 }