COBJS-$(CONFIG_P1011) += ddr-gen3.o
COBJS-$(CONFIG_P1012) += ddr-gen3.o
COBJS-$(CONFIG_P1013) += ddr-gen3.o
+COBJS-$(CONFIG_P1014) += ddr-gen3.o
COBJS-$(CONFIG_P1020) += ddr-gen3.o
COBJS-$(CONFIG_P1021) += ddr-gen3.o
COBJS-$(CONFIG_P1022) += ddr-gen3.o
CPU_TYPE_ENTRY(P1012, P1012, 1),
CPU_TYPE_ENTRY(P1012, P1012_E, 1),
CPU_TYPE_ENTRY(P1013, P1013, 1),
+ CPU_TYPE_ENTRY(P1014, P1014_E, 1),
+ CPU_TYPE_ENTRY(P1014, P1014, 1),
CPU_TYPE_ENTRY(P1013, P1013_E, 1),
CPU_TYPE_ENTRY(P1020, P1020, 2),
CPU_TYPE_ENTRY(P1020, P1020_E, 2),
/* Enable TSEC2.0 for the platforms that have it if we are using TSEC */
#if defined(CONFIG_TSEC_ENET) && \
- (defined(CONFIG_P1010) || \
+ (defined(CONFIG_P1010) || defined(CONFIG_P1014) || \
defined(CONFIG_P1020) || defined(CONFIG_P1011))
#define CONFIG_TSECV2
#endif
* SEC (crypto unit) major compatible version determination
*/
#if defined(CONFIG_FSL_CORENET) || \
- defined(CONFIG_P1010)
+ defined(CONFIG_P1010) || defined(CONFIG_P1014)
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#elif defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx)
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define SVR_P1012_E 0x80ED01
#define SVR_P1013 0x80E700
#define SVR_P1013_E 0x80EF00
+#define SVR_P1014 0x80F101
+#define SVR_P1014_E 0x80F901
#define SVR_P1020 0x80E400
#define SVR_P1020_E 0x80EC00
#define SVR_P1021 0x80E401
defined(CONFIG_MPC8641) || defined(CONFIG_MPC8610)
#define FSL_HW_NUM_LAWS 10
#elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572) || \
- defined(CONFIG_P1010) || \
+ defined(CONFIG_P1010) || defined(CONFIG_P1014) || \
defined(CONFIG_P1011) || defined(CONFIG_P1020) || \
defined(CONFIG_P1012) || defined(CONFIG_P1021) || \
defined(CONFIG_P1013) || defined(CONFIG_P1022) || \