drm/amdgpu/discovery: move common discovery code out of navi1*_reg_base_init()
authorXiaojie Yuan <xiaojie.yuan@amd.com>
Mon, 5 Aug 2019 08:19:45 +0000 (16:19 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 6 Aug 2019 18:53:05 +0000 (13:53 -0500)
move amdgpu_discovery_reg_base_init() from navi1*_reg_base_init() to a
common function nv_reg_base_init().

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c
drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c
drivers/gpu/drm/amd/amdgpu/nv.c

index 55014ce8670a20049195ab247788ce65a7155558..a56c93620e78621a1f0408de982bb5a3b7d4c46f 100644 (file)
 
 int navi10_reg_base_init(struct amdgpu_device *adev)
 {
-       int r, i;
+       int i;
 
-       if (amdgpu_discovery) {
-               r = amdgpu_discovery_reg_base_init(adev);
-               if (r) {
-                       DRM_WARN("failed to init reg base from ip discovery table, "
-                                       "fallback to legacy init method\n");
-                       goto legacy_init;
-               }
-
-               return 0;
-       }
-
-legacy_init:
        for (i = 0 ; i < MAX_INSTANCE ; ++i) {
                adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
                adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
index 864668a7f1d2501e3992d17a026c12b61e7f66b6..3b5f0f65e0964ba2260424041053b4a28d19efb4 100644 (file)
 
 int navi14_reg_base_init(struct amdgpu_device *adev)
 {
-       int r, i;
+       int i;
 
-       if (amdgpu_discovery) {
-               r = amdgpu_discovery_reg_base_init(adev);
-               if (r) {
-                       DRM_WARN("failed to init reg base from ip discovery table, "
-                                       "fallback to legacy init method\n");
-                       goto legacy_init;
-               }
-
-               return 0;
-       }
-
-legacy_init:
        for (i = 0 ; i < MAX_INSTANCE ; ++i) {
                adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
                adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
index 2f09d870f644fdf38aba92f72b63c3fd84946d05..3e67536f0dc9c0b532b56bf3ea04a121b1e95fa1 100644 (file)
@@ -376,9 +376,22 @@ static const struct amdgpu_ip_block_version nv_common_ip_block =
        .funcs = &nv_common_ip_funcs,
 };
 
-int nv_set_ip_blocks(struct amdgpu_device *adev)
+static int nv_reg_base_init(struct amdgpu_device *adev)
 {
-       /* Set IP register base before any HW register access */
+       int r;
+
+       if (amdgpu_discovery) {
+               r = amdgpu_discovery_reg_base_init(adev);
+               if (r) {
+                       DRM_WARN("failed to init reg base from ip discovery table, "
+                                       "fallback to legacy init method\n");
+                       goto legacy_init;
+               }
+
+               return 0;
+       }
+
+legacy_init:
        switch (adev->asic_type) {
        case CHIP_NAVI10:
                navi10_reg_base_init(adev);
@@ -393,6 +406,18 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
                return -EINVAL;
        }
 
+       return 0;
+}
+
+int nv_set_ip_blocks(struct amdgpu_device *adev)
+{
+       int r;
+
+       /* Set IP register base before any HW register access */
+       r = nv_reg_base_init(adev);
+       if (r)
+               return r;
+
        adev->nbio_funcs = &nbio_v2_3_funcs;
 
        adev->nbio_funcs->detect_hw_virt(adev);