drm/amd/display: Add missing MI masks

This will fix the memory Input programing with MST tiled display.
This Fix should fix connectivity problems with MST tiled Display

Signed-off-by: Leon Elazar <leon.elazar@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
index f90d586656efcc397f36d493a7cc7e3d533b51bb..ec053c241901b23e3628fe08f3db8e4a7e922d76 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
@@ -92,6 +92,8 @@ struct dce_mem_input_registers {
        .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
 
 #define MI_GFX8_TILE_MASK_SH_LIST(mask_sh, blk)\
+       SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
+       SFB(blk, GRPH_CONTROL, GRPH_BANK_WIDTH, mask_sh),\
        SFB(blk, GRPH_CONTROL, GRPH_BANK_HEIGHT, mask_sh),\
        SFB(blk, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, mask_sh),\
        SFB(blk, GRPH_CONTROL, GRPH_TILE_SPLIT, mask_sh),\