KVM: PPC: Book3S HV: Handle migration with POWER9 disabled DAWR

POWER9 with the DAWR disabled causes problems for partition
migration. Either we have to fail the migration (since we lose the
DAWR) or we silently drop the DAWR and allow the migration to pass.

This patch does the latter and allows the migration to pass (at the
cost of silently losing the DAWR). This is not ideal but hopefully the
best overall solution. This approach has been acked by Paulus.

With this patch kvmppc_set_one_reg() will store the DAWR in the vcpu
but won't actually set it on POWER9 hardware.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index 3d1023b03d5aa92296f6413e7d3b9179bf61552a..af1772169eff6507c505f7a493413fc7ea5f782a 100644 (file)
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -892,8 +892,14 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
        ld      r6, VCPU_DAWRX(r4)
        ld      r7, VCPU_CIABR(r4)
        ld      r8, VCPU_TAR(r4)
+       /*
+        * Handle broken DAWR case by not writing it. This means we
+        * can still store the DAWR register for migration.
+        */
+BEGIN_FTR_SECTION
        mtspr   SPRN_DAWR, r5
        mtspr   SPRN_DAWRX, r6
+END_FTR_SECTION_IFSET(CPU_FTR_DAWR)
        mtspr   SPRN_CIABR, r7
        mtspr   SPRN_TAR, r8
        ld      r5, VCPU_IC(r4)
@@ -1855,6 +1861,10 @@ BEGIN_FTR_SECTION
        ld      r6, STACK_SLOT_DAWR(r1)
        ld      r7, STACK_SLOT_DAWRX(r1)
        mtspr   SPRN_CIABR, r5
+       /*
+        * If the DAWR doesn't work, it's ok to write these here as
+        * this value should always be zero
+       */
        mtspr   SPRN_DAWR, r6
        mtspr   SPRN_DAWRX, r7
 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)