x86, amd: Enable L3 cache index disable on family 0x15

AMD family 0x15 CPUs support L3 cache index disable, so enable
it on them.

Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com>
Cc: <andreas.herrmann3@amd.com>
LKML-Reference: <1295881543-572552-3-git-send-email-hans.rosenfeld@amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index 0a99f7198bc373a8a2b45da3518234823786a590..a4f394c8e0558b77d8f12c47f75839418965abef 100644 (file)
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -85,6 +85,9 @@ int amd_cache_northbridges(void)
             boot_cpu_data.x86_mask >= 0x1))
                amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
 
+       if (boot_cpu_data.x86 == 0x15)
+               amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
+
        return 0;
 }
 EXPORT_SYMBOL_GPL(amd_cache_northbridges);