include $(TOPDIR)/rules.mk
-PKG_VERSION:=2.4
-PKG_RELEASE:=1
-PKG_HASH:=bf3eb3617a74cddd7fb0e0eacbfe38c3258ee07d4c8ed730deef7a175cc3d55b
+PKG_VERSION:=2.5
+PKG_RELEASE:=$(AUTORELEASE)
+PKG_HASH:=ad8a2ffcbcd12d919723da07630fc0840c3c2fba7656d1462e45488e42995d7c
PKG_MAINTAINER:=Vladimir Vid <vladimir.vid@sartura.hr>
BL33=$(STAGING_DIR_IMAGE)/$(UBOOT)-u-boot.bin \
MV_DDR_PATH=$(STAGING_DIR_IMAGE)/$(MV_DDR_NAME) \
WTP=$(STAGING_DIR_IMAGE)/$(A3700_UTILS_NAME) \
+ USE_COHERENT_MEM=0 \
+ FIP_ALIGN=0x100 \
DDR_TOPOLOGY=$(DDR_TOPOLOGY) \
CLOCKSPRESET=$(CLOCKSPRESET) \
A3700_UTILS_COMMIT_ID=$(A3700_UTILS_RELEASE) \
MV_DDR_COMMIT_ID=$(MV_DDR_RELEASE) \
all \
- mrvl_flash
+ mrvl_flash \
+ mrvl_uart
A3700_UTILS_NAME:=a3700-utils
A3700_UTILS_RELEASE:=5598e150
mkdir -p $(STAGING_DIR_IMAGE)
$(TAR) -C $(STAGING_DIR_IMAGE) -xf $(DL_DIR)/$(A3700_UTILS_SOURCE)
+ echo "master" > $(STAGING_DIR_IMAGE)/$(A3700_UTILS_NAME)/branch.txt
$(call PatchDir/Default,$(STAGING_DIR_IMAGE)/$(A3700_UTILS_NAME),./patches-a3700-utils)
$(TAR) -C $(STAGING_DIR_IMAGE) -xf $(DL_DIR)/$(MV_DDR_SOURCE)
+ echo "master" > $(STAGING_DIR_IMAGE)/$(MV_DDR_NAME)/branch.txt
$(call PatchDir/Default,$(STAGING_DIR_IMAGE)/$(MV_DDR_NAME),./patches-mv-ddr-marvell)
$(TAR) -C $(STAGING_DIR_IMAGE) -xf $(DL_DIR)/$(LINARO_SOURCE)
endef
--- /dev/null
+--- a/plat/marvell/armada/a3k/common/a3700_common.mk
++++ b/plat/marvell/armada/a3k/common/a3700_common.mk
+@@ -76,7 +76,7 @@ $(if $(wildcard $(value WTP)/*),,$(error
+ $(if $(shell test -s "$(value WTP)/branch.txt" || git -C $(value WTP) rev-parse --show-cdup 2>&1),$(error "'WTP=$(value WTP)' was specified, but '$(value WTP)' does not contain valid Marvell a3700_utils release tarball nor git repository"))
+
+ DOIMAGEPATH := $(WTP)
+-DOIMAGETOOL := $(DOIMAGEPATH)/wtptp/src/TBB_Linux/release/TBB_linux
++DOIMAGETOOL := $(DOIMAGEPATH)/wtptp/linux/tbb_linux
+
+ BUILD_UART := uart-images
+ UART_IMAGE := $(BUILD_UART).tgz.bin
+@@ -132,7 +132,7 @@ TIMBLDUARTARGS := $(MARVELL_SECURE_BOOT
+ CRYPTOPP_LIBDIR ?= $(CRYPTOPP_PATH)
+ CRYPTOPP_INCDIR ?= $(CRYPTOPP_PATH)
+
+-$(DOIMAGETOOL): FORCE
++$(DOIMAGETOOL):
+ $(if $(CRYPTOPP_LIBDIR),,$(error "Platform '$(PLAT)' for WTP image tool requires CRYPTOPP_PATH or CRYPTOPP_LIBDIR. Please set CRYPTOPP_PATH or CRYPTOPP_LIBDIR to point to the right directory"))
+ $(if $(CRYPTOPP_INCDIR),,$(error "Platform '$(PLAT)' for WTP image tool requires CRYPTOPP_PATH or CRYPTOPP_INCDIR. Please set CRYPTOPP_PATH or CRYPTOPP_INCDIR to point to the right directory"))
+ $(if $(wildcard $(CRYPTOPP_LIBDIR)/*),,$(error "Either 'CRYPTOPP_PATH' or 'CRYPTOPP_LIB' was set to '$(CRYPTOPP_LIBDIR)', but '$(CRYPTOPP_LIBDIR)' does not exist"))
--- /dev/null
+From 66a7752834382595d26214783ae4698fd1f00bd6 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
+Date: Thu, 13 May 2021 14:53:44 +0200
+Subject: [PATCH] fix(plat/marvell/a3720/uart): fix UART clock rate value and
+ divisor calculation
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+UART parent clock is by default the platform's xtal clock, which is
+25 MHz.
+
+The value defined in the driver, though, is 25.8048 MHz. This is a hack
+for the suboptimal divisor calculation
+ Divisor = UART clock / (16 * baudrate)
+which does not use rounding division, resulting in a suboptimal value
+for divisor if the correct parent clock rate was used.
+
+Change the code for divisor calculation to
+ Divisor = Round(UART clock / (16 * baudrate))
+and change the parent clock rate value to 25 MHz.
+
+The final UART divisor for default baudrate 115200 is not affected by
+this change.
+
+(Note that the parent clock rate should not be defined via a macro,
+since the xtal clock can also be 40 MHz. This is outside of the scope of
+this fix, though.)
+
+Signed-off-by: Pali Rohár <pali@kernel.org>
+Change-Id: Iaa401173df87aec94f2dd1b38a90fb6ed0bf0ec6
+---
+ drivers/marvell/uart/a3700_console.S | 3 ++-
+ plat/marvell/armada/a3k/common/include/platform_def.h | 2 +-
+ 2 files changed, 3 insertions(+), 2 deletions(-)
+
+--- a/drivers/marvell/uart/a3700_console.S
++++ b/drivers/marvell/uart/a3700_console.S
+@@ -45,8 +45,9 @@ func console_a3700_core_init
+ cbz w2, init_fail
+
+ /* Program the baudrate */
+- /* Divisor = Uart clock / (16 * baudrate) */
++ /* Divisor = Round(Uartclock / (16 * baudrate)) */
+ lsl w2, w2, #4
++ add w1, w1, w2, lsr #1
+ udiv w2, w1, w2
+ and w2, w2, #0x3ff
+
+--- a/plat/marvell/armada/a3k/common/include/platform_def.h
++++ b/plat/marvell/armada/a3k/common/include/platform_def.h
+@@ -164,7 +164,7 @@
+ * PL011 related constants
+ */
+ #define PLAT_MARVELL_BOOT_UART_BASE (MVEBU_REGS_BASE + 0x12000)
+-#define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 25804800
++#define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 25000000
+
+ #define PLAT_MARVELL_CRASH_UART_BASE PLAT_MARVELL_BOOT_UART_BASE
+ #define PLAT_MARVELL_CRASH_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
--- /dev/null
+From b9185c75f7ec2b600ebe0d49281e216a2456b764 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
+Date: Thu, 13 May 2021 15:11:06 +0200
+Subject: [PATCH] fix(plat/marvell/a3720/uart): fix configuring UART clock
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+When configuring the UART_BAUD_REG register, the function
+console_a3700_core_init() currently only changes the baud divisor field,
+leaving other fields to their previous value.
+
+This is incorrect, because the baud divisor is computed with the
+assumption that the parent clock rate is 25 MHz, and since the other
+fields in this register configure the parent clock, which could have
+been changed by U-Boot or Linux.
+
+Fix this function to also configure the other fields so that the UART
+parent clock is selected to be the xtal clock.
+
+For example without this change TF-A prints only
+
+ ERROR: a3700_system_off needs to be implemented
+
+followed by garbage after plat_crash_console_init() is called.
+
+After applying this change instead of garbage it also print crash info:
+
+ PANIC at PC : 0x0000000004023800
+
+Signed-off-by: Pali Rohár <pali@kernel.org>
+Change-Id: I72f338355cc60d939b8bb978d9c7fdd576416b81
+---
+ drivers/marvell/uart/a3700_console.S | 7 ++-----
+ 1 file changed, 2 insertions(+), 5 deletions(-)
+
+--- a/drivers/marvell/uart/a3700_console.S
++++ b/drivers/marvell/uart/a3700_console.S
+@@ -49,12 +49,9 @@ func console_a3700_core_init
+ lsl w2, w2, #4
+ add w1, w1, w2, lsr #1
+ udiv w2, w1, w2
+- and w2, w2, #0x3ff
++ and w2, w2, #0x3ff /* clear all other bits to use default clock */
+
+- ldr w3, [x0, #UART_BAUD_REG]
+- bic w3, w3, 0x3ff
+- orr w3, w3, w2
+- str w3, [x0, #UART_BAUD_REG]/* set baud rate divisor */
++ str w2, [x0, #UART_BAUD_REG]/* set baud rate divisor */
+
+ /* Set UART to default 16X scheme */
+ mov w3, #0
--- /dev/null
+From 3133625859b74df42deddd80b705578af6fc2fea Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
+Date: Fri, 14 May 2021 13:21:56 +0200
+Subject: [PATCH] refactor(plat/marvell/uart): de-duplicate PLAT_MARVELL_UART
+ macros
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Macros PLAT_MARVELL_BOOT_UART* and PLAT_MARVELL_CRASH_UART* are defined
+to same values. De-duplicate them into PLAT_MARVELL_UART* macros.
+
+Signed-off-by: Pali Rohár <pali@kernel.org>
+Change-Id: Iae5daf7cad6a971e6f3dbe561df3d0174106ca7f
+---
+ plat/marvell/armada/a3k/common/include/platform_def.h | 7 ++-----
+ plat/marvell/armada/a8k/a80x0_puzzle/board/system_power.c | 4 ++--
+ plat/marvell/armada/a8k/common/include/platform_def.h | 7 ++-----
+ plat/marvell/armada/common/aarch64/marvell_helpers.S | 8 ++++----
+ plat/marvell/armada/common/marvell_console.c | 8 ++++----
+ 5 files changed, 14 insertions(+), 20 deletions(-)
+
+--- a/plat/marvell/armada/a3k/common/include/platform_def.h
++++ b/plat/marvell/armada/a3k/common/include/platform_def.h
+@@ -163,11 +163,8 @@
+ /*
+ * PL011 related constants
+ */
+-#define PLAT_MARVELL_BOOT_UART_BASE (MVEBU_REGS_BASE + 0x12000)
+-#define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 25000000
+-
+-#define PLAT_MARVELL_CRASH_UART_BASE PLAT_MARVELL_BOOT_UART_BASE
+-#define PLAT_MARVELL_CRASH_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
++#define PLAT_MARVELL_UART_BASE (MVEBU_REGS_BASE + 0x12000)
++#define PLAT_MARVELL_UART_CLK_IN_HZ 25000000
+
+ #define PLAT_MARVELL_BL31_RUN_UART_BASE PLAT_MARVELL_BOOT_UART_BASE
+ #define PLAT_MARVELL_BL31_RUN_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
+--- a/plat/marvell/armada/a8k/a80x0_puzzle/board/system_power.c
++++ b/plat/marvell/armada/a8k/a80x0_puzzle/board/system_power.c
+@@ -41,8 +41,8 @@ int system_power_off(void)
+ len = sizeof(system_off_now);
+ system_off_now[len - 1] = add_xor_checksum(system_off_now, len);
+
+- console_16550_register(PLAT_MARVELL_BOOT_UART_BASE + 0x100,
+- PLAT_MARVELL_BOOT_UART_CLK_IN_HZ, 115200, &console);
++ console_16550_register(PLAT_MARVELL_UART_BASE + 0x100,
++ PLAT_MARVELL_UART_CLK_IN_HZ, 115200, &console);
+
+ /* Send system_off_now to console */
+ for (i = 0; i < len; i++) {
+--- a/plat/marvell/armada/a8k/common/include/platform_def.h
++++ b/plat/marvell/armada/a8k/common/include/platform_def.h
+@@ -168,11 +168,8 @@
+ /*
+ * PL011 related constants
+ */
+-#define PLAT_MARVELL_BOOT_UART_BASE (MVEBU_REGS_BASE + 0x512000)
+-#define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 200000000
+-
+-#define PLAT_MARVELL_CRASH_UART_BASE PLAT_MARVELL_BOOT_UART_BASE
+-#define PLAT_MARVELL_CRASH_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
++#define PLAT_MARVELL_UART_BASE (MVEBU_REGS_BASE + 0x512000)
++#define PLAT_MARVELL_UART_CLK_IN_HZ 200000000
+
+ #define PLAT_MARVELL_BL31_RUN_UART_BASE PLAT_MARVELL_BOOT_UART_BASE
+ #define PLAT_MARVELL_BL31_RUN_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
+--- a/plat/marvell/armada/common/aarch64/marvell_helpers.S
++++ b/plat/marvell/armada/common/aarch64/marvell_helpers.S
+@@ -63,8 +63,8 @@ endfunc plat_marvell_calc_core_pos
+ * ---------------------------------------------
+ */
+ func plat_crash_console_init
+- mov_imm x0, PLAT_MARVELL_CRASH_UART_BASE
+- mov_imm x1, PLAT_MARVELL_CRASH_UART_CLK_IN_HZ
++ mov_imm x0, PLAT_MARVELL_UART_BASE
++ mov_imm x1, PLAT_MARVELL_UART_CLK_IN_HZ
+ mov_imm x2, MARVELL_CONSOLE_BAUDRATE
+ #ifdef PLAT_a3700
+ b console_a3700_core_init
+@@ -81,7 +81,7 @@ endfunc plat_crash_console_init
+ * ---------------------------------------------
+ */
+ func plat_crash_console_putc
+- mov_imm x1, PLAT_MARVELL_CRASH_UART_BASE
++ mov_imm x1, PLAT_MARVELL_UART_BASE
+ #ifdef PLAT_a3700
+
+ b console_a3700_core_putc
+@@ -99,7 +99,7 @@ endfunc plat_crash_console_putc
+ * ---------------------------------------------
+ */
+ func plat_crash_console_flush
+- mov_imm x0, PLAT_MARVELL_CRASH_UART_BASE
++ mov_imm x0, PLAT_MARVELL_UART_BASE
+ #ifdef PLAT_a3700
+ b console_a3700_core_flush
+ #else
+--- a/plat/marvell/armada/common/marvell_console.c
++++ b/plat/marvell/armada/common/marvell_console.c
+@@ -31,8 +31,8 @@ static console_t marvell_runtime_console
+ void marvell_console_boot_init(void)
+ {
+ int rc =
+- console_marvell_register(PLAT_MARVELL_BOOT_UART_BASE,
+- PLAT_MARVELL_BOOT_UART_CLK_IN_HZ,
++ console_marvell_register(PLAT_MARVELL_UART_BASE,
++ PLAT_MARVELL_UART_CLK_IN_HZ,
+ MARVELL_CONSOLE_BAUDRATE,
+ &marvell_boot_console);
+ if (rc == 0) {
+@@ -58,8 +58,8 @@ void marvell_console_boot_end(void)
+ void marvell_console_runtime_init(void)
+ {
+ int rc =
+- console_marvell_register(PLAT_MARVELL_BOOT_UART_BASE,
+- PLAT_MARVELL_BOOT_UART_CLK_IN_HZ,
++ console_marvell_register(PLAT_MARVELL_UART_BASE,
++ PLAT_MARVELL_UART_CLK_IN_HZ,
+ MARVELL_CONSOLE_BAUDRATE,
+ &marvell_runtime_console);
+ if (rc == 0)
--- /dev/null
+From 5a91c439cbeb1f64b8b9830de91efad5113d3c89 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
+Date: Fri, 14 May 2021 15:52:11 +0200
+Subject: [PATCH] fix(plat/marvell/a3720/uart): fix UART parent clock rate
+ determination
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The UART code for the A3K platform assumes that UART parent clock rate
+is always 25 MHz. This is incorrect, because the xtal clock can also run
+at 40 MHz (this is board specific).
+
+The frequency of the xtal clock is determined by a value on a strapping
+pin during SOC reset. The code to determine this frequency is already in
+A3K's comphy driver.
+
+Move the get_ref_clk() function from the comphy driver to a separate
+file and use it for UART parent clock rate determination.
+
+Signed-off-by: Pali Rohár <pali@kernel.org>
+Change-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e
+---
+ drivers/marvell/comphy/phy-comphy-3700.c | 24 +------------
+ .../marvell/armada/a3k/common/plat_marvell.h | 2 ++
+ .../marvell/armada/a3k/common/a3700_common.mk | 1 +
+ .../armada/a3k/common/aarch64/a3700_clock.S | 35 +++++++++++++++++++
+ .../armada/a3k/common/include/platform_def.h | 1 -
+ .../armada/common/aarch64/marvell_helpers.S | 10 +++++-
+ plat/marvell/armada/common/marvell_console.c | 1 +
+ 7 files changed, 49 insertions(+), 25 deletions(-)
+ create mode 100644 plat/marvell/armada/a3k/common/aarch64/a3700_clock.S
+
+--- a/drivers/marvell/comphy/phy-comphy-3700.c
++++ b/drivers/marvell/comphy/phy-comphy-3700.c
+@@ -14,6 +14,7 @@
+
+ #include <mvebu.h>
+ #include <mvebu_def.h>
++#include <plat_marvell.h>
+
+ #include "phy-comphy-3700.h"
+ #include "phy-comphy-common.h"
+@@ -29,15 +30,6 @@
+ #define USB3_GBE1_PHY (MVEBU_REGS_BASE + 0x5C000)
+ #define COMPHY_SD_ADDR (MVEBU_REGS_BASE + 0x1F000)
+
+-/*
+- * Below address in used only for reading, therefore no problem with concurrent
+- * Linux access.
+- */
+-#define MVEBU_TEST_PIN_LATCH_N (MVEBU_NB_GPIO_REG_BASE + 0x8)
+- #define MVEBU_XTAL_MODE_MASK BIT(9)
+- #define MVEBU_XTAL_MODE_OFFS 9
+- #define MVEBU_XTAL_CLOCK_25MHZ 0x0
+-
+ struct sgmii_phy_init_data_fix {
+ uint16_t addr;
+ uint16_t value;
+@@ -125,20 +117,6 @@ static uint16_t sgmii_phy_init[512] = {
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */
+ };
+
+-/* returns reference clock in MHz (25 or 40) */
+-static uint32_t get_ref_clk(void)
+-{
+- uint32_t val;
+-
+- val = (mmio_read_32(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >>
+- MVEBU_XTAL_MODE_OFFS;
+-
+- if (val == MVEBU_XTAL_CLOCK_25MHZ)
+- return 25;
+- else
+- return 40;
+-}
+-
+ /* PHY selector configures with corresponding modes */
+ static void mvebu_a3700_comphy_set_phy_selector(uint8_t comphy_index,
+ uint32_t comphy_mode)
+--- a/include/plat/marvell/armada/a3k/common/plat_marvell.h
++++ b/include/plat/marvell/armada/a3k/common/plat_marvell.h
+@@ -100,4 +100,6 @@ void plat_marvell_interconnect_enter_coh
+
+ const mmap_region_t *plat_marvell_get_mmap(void);
+
++uint32_t get_ref_clk(void);
++
+ #endif /* PLAT_MARVELL_H */
+--- a/plat/marvell/armada/a3k/common/a3700_common.mk
++++ b/plat/marvell/armada/a3k/common/a3700_common.mk
+@@ -38,6 +38,7 @@ PLAT_INCLUDES := -I$(PLAT_FAMILY_BASE)/
+ -I$/drivers/arm/gic/common/
+
+ PLAT_BL_COMMON_SOURCES := $(PLAT_COMMON_BASE)/aarch64/a3700_common.c \
++ $(PLAT_COMMON_BASE)/aarch64/a3700_clock.S \
+ $(MARVELL_DRV_BASE)/uart/a3700_console.S
+
+ BL1_SOURCES += $(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \
+--- /dev/null
++++ b/plat/marvell/armada/a3k/common/aarch64/a3700_clock.S
+@@ -0,0 +1,35 @@
++/*
++ * Copyright (C) 2018 Marvell International Ltd.
++ *
++ * SPDX-License-Identifier: BSD-3-Clause
++ * https://spdx.org/licenses
++ */
++
++#include <asm_macros.S>
++#include <platform_def.h>
++
++/*
++ * Below address in used only for reading, therefore no problem with concurrent
++ * Linux access.
++ */
++#define MVEBU_TEST_PIN_LATCH_N (MVEBU_NB_GPIO_REG_BASE + 0x8)
++ #define MVEBU_XTAL_MODE_MASK BIT(9)
++
++ /* -----------------------------------------------------
++ * uint32_t get_ref_clk (void);
++ *
++ * returns reference clock in MHz (25 or 40)
++ * -----------------------------------------------------
++ */
++.globl get_ref_clk
++func get_ref_clk
++ mov_imm x0, MVEBU_TEST_PIN_LATCH_N
++ ldr w0, [x0]
++ tst w0, #MVEBU_XTAL_MODE_MASK
++ bne 40
++ mov w0, #25
++ ret
++40:
++ mov w0, #40
++ ret
++endfunc get_ref_clk
+--- a/plat/marvell/armada/a3k/common/include/platform_def.h
++++ b/plat/marvell/armada/a3k/common/include/platform_def.h
+@@ -164,7 +164,6 @@
+ * PL011 related constants
+ */
+ #define PLAT_MARVELL_UART_BASE (MVEBU_REGS_BASE + 0x12000)
+-#define PLAT_MARVELL_UART_CLK_IN_HZ 25000000
+
+ #define PLAT_MARVELL_BL31_RUN_UART_BASE PLAT_MARVELL_BOOT_UART_BASE
+ #define PLAT_MARVELL_BL31_RUN_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
+--- a/plat/marvell/armada/common/aarch64/marvell_helpers.S
++++ b/plat/marvell/armada/common/aarch64/marvell_helpers.S
+@@ -63,8 +63,16 @@ endfunc plat_marvell_calc_core_pos
+ * ---------------------------------------------
+ */
+ func plat_crash_console_init
+- mov_imm x0, PLAT_MARVELL_UART_BASE
++#ifdef PLAT_a3700
++ mov x1, x30
++ bl get_ref_clk
++ mov x30, x1
++ mov_imm x1, 1000000
++ mul x1, x0, x1
++#else
+ mov_imm x1, PLAT_MARVELL_UART_CLK_IN_HZ
++#endif
++ mov_imm x0, PLAT_MARVELL_UART_BASE
+ mov_imm x2, MARVELL_CONSOLE_BAUDRATE
+ #ifdef PLAT_a3700
+ b console_a3700_core_init
+--- a/plat/marvell/armada/common/marvell_console.c
++++ b/plat/marvell/armada/common/marvell_console.c
+@@ -14,6 +14,7 @@
+
+ #ifdef PLAT_a3700
+ #include <drivers/marvell/uart/a3700_console.h>
++#define PLAT_MARVELL_UART_CLK_IN_HZ (get_ref_clk() * 1000000)
+ #define console_marvell_register console_a3700_register
+ #else
+ #include <drivers/ti/uart/uart_16550.h>
projects / openwrt / staging / hauke.git / commitdiff