[POWERPC] powerpc: PA6T cputable entry, PVR value
authorOlof Johansson <olof@lixom.net>
Wed, 6 Sep 2006 19:35:57 +0000 (14:35 -0500)
committerPaul Mackerras <paulus@samba.org>
Wed, 13 Sep 2006 08:39:52 +0000 (18:39 +1000)
Introduce PWRficient PA6T cputable entries and feature bits.

Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Paul Mackerras <paulus@samba.org>
arch/powerpc/kernel/cputable.c
include/asm-powerpc/cputable.h
include/asm-powerpc/reg.h

index 306da4cd37a0fc21c008353f9073540f90321186..db65c9f6559aed57ae034d8653257bb4557f38b5 100644 (file)
@@ -58,6 +58,9 @@ extern void __restore_cpu_ppc970(void);
 #define COMMON_USER_POWER6     (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_05 |\
                                 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
                                 PPC_FEATURE_TRUE_LE)
+#define COMMON_USER_PA6T       (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\
+                                PPC_FEATURE_TRUE_LE | \
+                                PPC_FEATURE_HAS_ALTIVEC_COMP)
 #define COMMON_USER_BOOKE      (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \
                                 PPC_FEATURE_BOOKE)
 
@@ -286,6 +289,17 @@ struct cpu_spec    cpu_specs[] = {
                .dcache_bsize           = 128,
                .platform               = "ppc-cell-be",
        },
+       {       /* PA Semi PA6T */
+               .pvr_mask               = 0x7fff0000,
+               .pvr_value              = 0x00900000,
+               .cpu_name               = "PA6T",
+               .cpu_features           = CPU_FTRS_PA6T,
+               .cpu_user_features      = COMMON_USER_PA6T,
+               .icache_bsize           = 64,
+               .dcache_bsize           = 64,
+               .num_pmcs               = 6,
+               .platform               = "pa6t",
+       },
        {       /* default match */
                .pvr_mask               = 0x00000000,
                .pvr_value              = 0x00000000,
index 3608259c49cfcd1a1c71ae9832c71cd1cd24ff65..12707ab9dc98db6bcc6bf75556dd925e9a56818e 100644 (file)
@@ -23,6 +23,7 @@
 #define PPC_FEATURE_SMT                        0x00004000
 #define PPC_FEATURE_ICACHE_SNOOP       0x00002000
 #define PPC_FEATURE_ARCH_2_05          0x00001000
+#define PPC_FEATURE_PA6T               0x00000800
 
 #define PPC_FEATURE_TRUE_LE            0x00000002
 #define PPC_FEATURE_PPC_LE             0x00000001
@@ -332,6 +333,10 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
            CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
            CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE)
+#define CPU_FTRS_PA6T (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
+           CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
+           CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
+           CPU_FTR_PURR | CPU_FTR_REAL_LE)
 #define CPU_FTRS_COMPATIBLE    (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
            CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
 #endif
@@ -340,7 +345,7 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
 #define CPU_FTRS_POSSIBLE      \
            (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |        \
            CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 |       \
-           CPU_FTRS_CELL | CPU_FTR_CI_LARGE_PAGE)
+           CPU_FTRS_CELL | CPU_FTRS_PA6T)
 #else
 enum {
        CPU_FTRS_POSSIBLE =
@@ -379,7 +384,7 @@ enum {
 #define CPU_FTRS_ALWAYS                \
            (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &        \
            CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 &       \
-           CPU_FTRS_CELL & CPU_FTRS_POSSIBLE)
+           CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
 #else
 enum {
        CPU_FTRS_ALWAYS =
index cf73475a0c69fc7f0a30570ad88086077feb254b..3a9fcc15811b44dff427a5b9fcbf52d48f18b4c8 100644 (file)
 #define PV_630p        0x0041
 #define PV_970MP       0x0044
 #define PV_BE          0x0070
+#define PV_PA6T                0x0090
 
 /*
  * Number of entries in the SLB. If this ever changes we should handle