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Tegra114: pinmux: Fix bad CAM_MCLK func 3 table entry
author
Tom Warren
<twarren@nvidia.com>
Wed, 13 Mar 2013 22:00:54 +0000
(15:00 -0700)
committer
Tom Warren
<twarren@nvidia.com>
Thu, 14 Mar 2013 18:08:57 +0000
(11:08 -0700)
This caused CAM_MCLK's pinmux reg to be locked out, since the
table parsing code couldn't find a matching entry for VI_ALT3
and wrote garbage to the register.
Signed-off-by: Tom Warren <twarren@nvidia.com>
arch/arm/cpu/tegra114-common/pinmux.c
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diff --git
a/arch/arm/cpu/tegra114-common/pinmux.c
b/arch/arm/cpu/tegra114-common/pinmux.c
index 27b5f694fa3cb5e649224ed953ebf31db0c30330..16368c5bc114f8e84cbcf6c959b74e07bf357f76 100644
(file)
--- a/
arch/arm/cpu/tegra114-common/pinmux.c
+++ b/
arch/arm/cpu/tegra114-common/pinmux.c
@@
-226,7
+226,7
@@
const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
PINI(SDMMC4_DAT6, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
PINI(SDMMC4_DAT7, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
PIN_RESERVED, /* Reserved by t114: 0x3280 */
- PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT
2
, RSVD4),
+ PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT
3
, RSVD4),
PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, RSVD4),
PINI(GPIO_PBB0, CAM, I2S4, VI, VI_ALT1, VI_ALT3),
PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, RSVD4),