#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
#define AR934X_WMAC_SIZE 0x20000
+#define AR934X_EHCI_BASE 0x1b000000
-+#define AR934X_EHCI_SIZE 0x1000
++#define AR934X_EHCI_SIZE 0x200
/*
* DDR_CTRL block
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -92,6 +92,10 @@
#define AR934X_EHCI_BASE 0x1b000000
- #define AR934X_EHCI_SIZE 0x1000
+ #define AR934X_EHCI_SIZE 0x200
+#define QCA955X_EHCI0_BASE 0x1b000000
+#define QCA955X_EHCI1_BASE 0x1b400000
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -92,6 +92,8 @@
#define AR934X_EHCI_BASE 0x1b000000
- #define AR934X_EHCI_SIZE 0x1000
+ #define AR934X_EHCI_SIZE 0x200
+#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
+#define QCA955X_WMAC_SIZE 0x20000
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -92,6 +92,19 @@
#define AR934X_EHCI_BASE 0x1b000000
- #define AR934X_EHCI_SIZE 0x1000
+ #define AR934X_EHCI_SIZE 0x200
+#define QCA955X_PCI_MEM_BASE0 0x10000000
+#define QCA955X_PCI_MEM_BASE1 0x12000000