MIPS: Map CM Global Control Registers

Map the Global Control Registers (GCRs) provided by the MIPS Coherence
Manager (CM) in preparation for using some of them in later patches.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index fa344a78b6729fc2b4e89fbaf29ce323abeb5477..47056b4bf8a13fdfcc7e62458d890583597efee9 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -318,6 +318,22 @@ config MIPS_L1_CACHE_SHIFT
 config DYNAMIC_IO_PORT_BASE
        bool
 
+config MIPS_CM
+       bool
+       help
+         Select this if your system contains a MIPS Coherence Manager and you
+         wish U-Boot to configure it or make use of it to retrieve system
+         information such as cache configuration.
+
+config MIPS_CM_BASE
+       hex
+       default 0x1fbf8000
+       help
+         The physical base address at which to map the MIPS Coherence Manager
+         Global Configuration Registers (GCRs). This should be set such that
+         the GCRs occupy a region of the physical address space which is
+         otherwise unused, or at minimum that software doesn't need to access.
+
 endif
 
 endmenu

diff --git a/arch/mips/cpu/Makefile b/arch/mips/cpu/Makefile
index fc6b455c68bb5245f29c2979f8488f8d61c15d3f..429fd3a50c97949a7f51e4e8126dbb4442ce32b6 100644 (file)
--- a/arch/mips/cpu/Makefile
+++ b/arch/mips/cpu/Makefile
@@ -7,3 +7,5 @@ extra-y = start.o
 obj-y += time.o
 obj-y += interrupts.o
 obj-y += cpu.o
+
+obj-$(CONFIG_MIPS_CM)  += cm_init.o

diff --git a/arch/mips/cpu/cm_init.S b/arch/mips/cpu/cm_init.S
new file mode 100644 (file)
index 0000000..ddcaa49
--- /dev/null
+++ b/arch/mips/cpu/cm_init.S
@@ -0,0 +1,45 @@
+/*
+ * MIPS Coherence Manager (CM) Initialisation
+ *
+ * Copyright (c) 2016 Imagination Technologies Ltd.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <asm/addrspace.h>
+#include <asm/asm.h>
+#include <asm/cm.h>
+#include <asm/mipsregs.h>
+#include <asm/regdef.h>
+
+LEAF(mips_cm_map)
+       /* Config3 must exist for a CM to be present */
+       mfc0            t0, CP0_CONFIG, 1
+       bgez            t0, 2f
+       mfc0            t0, CP0_CONFIG, 2
+       bgez            t0, 2f
+
+       /* Check Config3.CMGCR to determine CM presence */
+       mfc0            t0, CP0_CONFIG, 3
+       and             t0, t0, MIPS_CONF3_CMGCR
+       beqz            t0, 2f
+
+       /* Find the current physical GCR base address */
+1:     MFC0            t0, CP0_CMGCRBASE
+       PTR_SLL         t0, t0, 4
+
+       /* If the GCRs are where we want, we're done */
+       PTR_LI          t1, CONFIG_MIPS_CM_BASE
+       beq             t0, t1, 2f
+
+       /* Move the GCRs to our configured base address */
+       PTR_LI          t2, CKSEG1
+       PTR_ADDU        t0, t0, t2
+       sw              zero, GCR_BASE_UPPER(t0)
+       sw              t1, GCR_BASE(t0)
+
+       /* Re-check the GCR base */
+       b               1b
+
+2:     jr              ra
+       END(mips_cm_map)

diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index 6f1d2192b0d30944441112bda2deb6eb0f02aa8a..c157d03d314f67dad89ead4e55fe82f2ec20912c 100644 (file)
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -141,6 +141,12 @@ reset:
 1:
        PTR_L   gp, 0(ra)
 
+#ifdef CONFIG_MIPS_CM
+       PTR_LA  t9, mips_cm_map
+       jalr    t9
+        nop
+#endif
+
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 # ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
        /* Initialize any external memory */

diff --git a/arch/mips/include/asm/cm.h b/arch/mips/include/asm/cm.h
new file mode 100644 (file)
index 0000000..0261733
--- /dev/null
+++ b/arch/mips/include/asm/cm.h
@@ -0,0 +1,19 @@
+/*
+ * MIPS Coherence Manager (CM) Register Definitions
+ *
+ * Copyright (c) 2016 Imagination Technologies Ltd.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+#ifndef __MIPS_ASM_CM_H__
+#define __MIPS_ASM_CM_H__
+
+/* Global Control Register (GCR) offsets */
+#define GCR_BASE                       0x0008
+#define GCR_BASE_UPPER                 0x000c
+#define GCR_REV                                0x0030
+
+/* GCR_REV CM versions */
+#define GCR_REV_CM3                    0x0800
+
+#endif /* __MIPS_ASM_CM_H__ */