drm/i915: dev_priv cleanup in i915_irq.c

And a little bit of function prototype changes.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index cb8a75f6ca167911d8e0c60194f0faafd2861596..07ca71cabb2bfe94a6c250cc538dce500157f404 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2848,10 +2848,8 @@ static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
        spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 }
 
-static void ibx_irq_reset(struct drm_device *dev)
+static void ibx_irq_reset(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = to_i915(dev);
-
        if (HAS_PCH_NOP(dev_priv))
                return;
 
@@ -2881,12 +2879,10 @@ static void ibx_irq_pre_postinstall(struct drm_device *dev)
        POSTING_READ(SDEIER);
 }
 
-static void gen5_gt_irq_reset(struct drm_device *dev)
+static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = to_i915(dev);
-
        GEN5_IRQ_RESET(GT);
-       if (INTEL_INFO(dev)->gen >= 6)
+       if (INTEL_GEN(dev_priv) >= 6)
                GEN5_IRQ_RESET(GEN6_PM);
 }
 
@@ -2951,9 +2947,9 @@ static void ironlake_irq_reset(struct drm_device *dev)
        if (IS_GEN7(dev_priv))
                I915_WRITE(GEN7_ERR_INT, 0xffffffff);
 
-       gen5_gt_irq_reset(dev);
+       gen5_gt_irq_reset(dev_priv);
 
-       ibx_irq_reset(dev);
+       ibx_irq_reset(dev_priv);
 }
 
 static void valleyview_irq_preinstall(struct drm_device *dev)
@@ -2963,7 +2959,7 @@ static void valleyview_irq_preinstall(struct drm_device *dev)
        I915_WRITE(VLV_MASTER_IER, 0);
        POSTING_READ(VLV_MASTER_IER);
 
-       gen5_gt_irq_reset(dev);
+       gen5_gt_irq_reset(dev_priv);
 
        spin_lock_irq(&dev_priv->irq_lock);
        if (dev_priv->display_irqs_enabled)
@@ -2999,7 +2995,7 @@ static void gen8_irq_reset(struct drm_device *dev)
        GEN5_IRQ_RESET(GEN8_PCU_);
 
        if (HAS_PCH_SPLIT(dev_priv))
-               ibx_irq_reset(dev);
+               ibx_irq_reset(dev_priv);
 }
 
 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
@@ -3222,7 +3218,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
 
        GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
 
-       if (INTEL_INFO(dev)->gen >= 6) {
+       if (INTEL_GEN(dev_priv) >= 6) {
                /*
                 * RPS interrupts will get enabled/disabled on demand when RPS
                 * itself is enabled/disabled.
@@ -3242,7 +3238,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
        struct drm_i915_private *dev_priv = to_i915(dev);
        u32 display_mask, extra_mask;
 
-       if (INTEL_INFO(dev)->gen >= 7) {
+       if (INTEL_GEN(dev_priv) >= 7) {
                display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
                                DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
                                DE_PLANEB_FLIP_DONE_IVB |
@@ -3466,7 +3462,7 @@ static void valleyview_irq_uninstall(struct drm_device *dev)
        I915_WRITE(VLV_MASTER_IER, 0);
        POSTING_READ(VLV_MASTER_IER);
 
-       gen5_gt_irq_reset(dev);
+       gen5_gt_irq_reset(dev_priv);
 
        I915_WRITE(HWSTAM, 0xffffffff);