drm/i915: extract intel_dpio_phy.h from i915_drv.h
authorJani Nikula <jani.nikula@intel.com>
Thu, 2 May 2019 15:02:40 +0000 (18:02 +0300)
committerJani Nikula <jani.nikula@intel.com>
Fri, 3 May 2019 07:06:28 +0000 (10:06 +0300)
It used to be handy that we only had a couple of headers, but over time
i915_drv.h has become unwieldy. Extract declarations to a separate
header file corresponding to the implementation module, clarifying the
modularity of the driver.

Ensure the new header is self-contained, and do so with minimal further
includes, using forward declarations as needed. Include the new header
only where needed, and sort the modified include directives while at it
and as needed.

No functional changes.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/876a1671a84c6839bcafdf276cf9c4e1da6c631c.1556809195.git.jani.nikula@intel.com
drivers/gpu/drm/i915/Makefile.header-test
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/intel_ddi.c
drivers/gpu/drm/i915/intel_dp.c
drivers/gpu/drm/i915/intel_dp_mst.c
drivers/gpu/drm/i915/intel_dpio_phy.c
drivers/gpu/drm/i915/intel_dpio_phy.h [new file with mode: 0644]
drivers/gpu/drm/i915/intel_dpll_mgr.c
drivers/gpu/drm/i915/intel_hdmi.c
drivers/gpu/drm/i915/intel_runtime_pm.c

index 95e4ee821d6033a3bdb2c94ac87fc2bfb44bb70f..459b84f84c2abaa99a65ea4c2ceca9f41abac4f1 100644 (file)
@@ -28,6 +28,7 @@ header_test := \
        intel_dp_aux_backlight.h \
        intel_dp_link_training.h \
        intel_dp_mst.h \
+       intel_dpio_phy.h \
        intel_dpll_mgr.h \
        intel_drv.h \
        intel_dsi.h \
index 9e701dedaf491048bdcd4ed8ed7e5599f220111e..85cc5e1260653c7faf3116a19845ff3d285e4f56 100644 (file)
@@ -3313,47 +3313,6 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv);
 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
                                            struct intel_display_error_state *error);
 
-/* intel_dpio_phy.c */
-void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
-                            enum dpio_phy *phy, enum dpio_channel *ch);
-void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
-                                 enum port port, u32 margin, u32 scale,
-                                 u32 enable, u32 deemphasis);
-void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
-void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
-bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
-                           enum dpio_phy phy);
-bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
-                             enum dpio_phy phy);
-u8 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count);
-void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
-                                    u8 lane_lat_optim_mask);
-u8 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
-
-void chv_set_phy_signal_level(struct intel_encoder *encoder,
-                             u32 deemph_reg_value, u32 margin_reg_value,
-                             bool uniq_trans_scale);
-void chv_data_lane_soft_reset(struct intel_encoder *encoder,
-                             const struct intel_crtc_state *crtc_state,
-                             bool reset);
-void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
-                           const struct intel_crtc_state *crtc_state);
-void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
-                               const struct intel_crtc_state *crtc_state);
-void chv_phy_release_cl2_override(struct intel_encoder *encoder);
-void chv_phy_post_pll_disable(struct intel_encoder *encoder,
-                             const struct intel_crtc_state *old_crtc_state);
-
-void vlv_set_phy_signal_level(struct intel_encoder *encoder,
-                             u32 demph_reg_value, u32 preemph_reg_value,
-                             u32 uniqtranscale_reg_value, u32 tx3_demph);
-void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
-                           const struct intel_crtc_state *crtc_state);
-void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
-                               const struct intel_crtc_state *crtc_state);
-void vlv_phy_reset_lanes(struct intel_encoder *encoder,
-                        const struct intel_crtc_state *old_crtc_state);
-
 #define __I915_REG_OP(op__, dev_priv__, ...) \
        intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
 
index f5f58f6bc7e26b5b9bd7d2c7d576095fabc2a7d3..ec6ed93d7c0ae5252ce406b71109230971d64d71 100644 (file)
@@ -34,6 +34,7 @@
 #include "intel_ddi.h"
 #include "intel_dp.h"
 #include "intel_dp_link_training.h"
+#include "intel_dpio_phy.h"
 #include "intel_drv.h"
 #include "intel_dsi.h"
 #include "intel_fifo_underrun.h"
index 42a880e0b392cda861d0207d86dc1272cafc8622..8d52fd0a141764d5da4cac6c8b3cb96fb7c5b74e 100644 (file)
@@ -50,6 +50,7 @@
 #include "intel_dp.h"
 #include "intel_dp_link_training.h"
 #include "intel_dp_mst.h"
+#include "intel_dpio_phy.h"
 #include "intel_drv.h"
 #include "intel_fifo_underrun.h"
 #include "intel_hdcp.h"
index 725518e8bfaa4ac1fac8285af2e3405771e286e4..0caf645fbbb841b38a63e05c73ea198e4ed70d22 100644 (file)
@@ -34,6 +34,7 @@
 #include "intel_ddi.h"
 #include "intel_dp.h"
 #include "intel_dp_mst.h"
+#include "intel_dpio_phy.h"
 #include "intel_drv.h"
 
 static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
index d80887b5e234bbf1d57423b1cf4f50c16d02e80a..bdbe4175982710711569f8485745885e37f593c1 100644 (file)
@@ -22,6 +22,7 @@
  */
 
 #include "intel_dp.h"
+#include "intel_dpio_phy.h"
 #include "intel_drv.h"
 #include "intel_sideband.h"
 
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.h b/drivers/gpu/drm/i915/intel_dpio_phy.h
new file mode 100644 (file)
index 0000000..f418aab
--- /dev/null
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef __INTEL_DPIO_PHY_H__
+#define __INTEL_DPIO_PHY_H__
+
+#include <linux/types.h>
+
+enum dpio_channel;
+enum dpio_phy;
+enum port;
+struct drm_i915_private;
+struct intel_crtc_state;
+struct intel_encoder;
+
+void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
+                            enum dpio_phy *phy, enum dpio_channel *ch);
+void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
+                                 enum port port, u32 margin, u32 scale,
+                                 u32 enable, u32 deemphasis);
+void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
+void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
+bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
+                           enum dpio_phy phy);
+bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
+                             enum dpio_phy phy);
+u8 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count);
+void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
+                                    u8 lane_lat_optim_mask);
+u8 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
+
+void chv_set_phy_signal_level(struct intel_encoder *encoder,
+                             u32 deemph_reg_value, u32 margin_reg_value,
+                             bool uniq_trans_scale);
+void chv_data_lane_soft_reset(struct intel_encoder *encoder,
+                             const struct intel_crtc_state *crtc_state,
+                             bool reset);
+void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
+                           const struct intel_crtc_state *crtc_state);
+void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
+                               const struct intel_crtc_state *crtc_state);
+void chv_phy_release_cl2_override(struct intel_encoder *encoder);
+void chv_phy_post_pll_disable(struct intel_encoder *encoder,
+                             const struct intel_crtc_state *old_crtc_state);
+
+void vlv_set_phy_signal_level(struct intel_encoder *encoder,
+                             u32 demph_reg_value, u32 preemph_reg_value,
+                             u32 uniqtranscale_reg_value, u32 tx3_demph);
+void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
+                           const struct intel_crtc_state *crtc_state);
+void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
+                               const struct intel_crtc_state *crtc_state);
+void vlv_phy_reset_lanes(struct intel_encoder *encoder,
+                        const struct intel_crtc_state *old_crtc_state);
+
+#endif /* __INTEL_DPIO_PHY_H__ */
index dda5ddb49b34d16b404575372dccbaeb39cfcf56..8f731a6f9bd755f2d7b4a100062d629a4d696741 100644 (file)
@@ -21,6 +21,7 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
+#include "intel_dpio_phy.h"
 #include "intel_dpll_mgr.h"
 #include "intel_drv.h"
 
index f8440c6c784dffed607ff651a4f055a7fc4ea73b..571e6b5d23759cfb8cb694225f1ad72f89d6f937 100644 (file)
@@ -45,6 +45,7 @@
 #include "intel_connector.h"
 #include "intel_ddi.h"
 #include "intel_dp.h"
+#include "intel_dpio_phy.h"
 #include "intel_drv.h"
 #include "intel_fifo_underrun.h"
 #include "intel_hdcp.h"
index be71197abc00c3d91520cf6eb6f3bf5e1a1d6eb4..1b7ea6bab613bf3280d16a67ea8648830d55089a 100644 (file)
@@ -38,6 +38,7 @@
 #include "intel_crt.h"
 #include "intel_csr.h"
 #include "intel_dp.h"
+#include "intel_dpio_phy.h"
 #include "intel_drv.h"
 #include "intel_hotplug.h"
 #include "intel_sideband.h"