x86: quark: Initialize non-standard BARs

Quark SoC has some non-standard BARs (excluding PCI standard BARs)
which need be initialized with suggested values. This includes GPIO,
WDT, RCBA, PCIe ECAM and some ACPI register block base addresses.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index 47ba15253f2217e7dd2e08b71476ad5cf33246cd..cf596e45e189bba12f23dd248ebc054e3578da77 100644 (file)
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -9,6 +9,46 @@
 #include <asm/pci.h>
 #include <asm/post.h>
 #include <asm/processor.h>
+#include <asm/arch/device.h>
+#include <asm/arch/msg_port.h>
+#include <asm/arch/quark.h>
+
+static void quark_setup_bars(void)
+{
+       /* GPIO - D31:F0:R44h */
+       pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA,
+                              CONFIG_GPIO_BASE | IO_BAR_EN);
+
+       /* ACPI PM1 Block - D31:F0:R48h */
+       pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK,
+                              CONFIG_ACPI_PM1_BASE | IO_BAR_EN);
+
+       /* GPE0 - D31:F0:R4Ch */
+       pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK,
+                              CONFIG_ACPI_GPE0_BASE | IO_BAR_EN);
+
+       /* WDT - D31:F0:R84h */
+       pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA,
+                              CONFIG_WDT_BASE | IO_BAR_EN);
+
+       /* RCBA - D31:F0:RF0h */
+       pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA,
+                              CONFIG_RCBA_BASE | MEM_BAR_EN);
+
+       /* ACPI P Block - Msg Port 04:R70h */
+       msg_port_write(MSG_PORT_RMU, PBLK_BA,
+                      CONFIG_ACPI_PBLK_BASE | IO_BAR_EN);
+
+       /* SPI DMA - Msg Port 04:R7Ah */
+       msg_port_write(MSG_PORT_RMU, SPI_DMA_BA,
+                      CONFIG_SPI_DMA_BASE | IO_BAR_EN);
+
+       /* PCIe ECAM */
+       msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL,
+                      CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
+       msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG,
+                      CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
+}
 
 int arch_cpu_init(void)
 {
@@ -28,6 +68,12 @@ int arch_cpu_init(void)
        if (ret)
                return ret;
 
+       /*
+        * Quark SoC has some non-standard BARs (excluding PCI standard BARs)
+        * which need be initialized with suggested values
+        */
+       quark_setup_bars();
+
        return 0;
 }
 

diff --git a/arch/x86/include/asm/arch-quark/quark.h b/arch/x86/include/asm/arch-quark/quark.h
index ebbcf7755d1bba01693a8f76fbeb2775c58b06d6..ceb583e3f055b1a298e1c899c53c23b7a5e9ae40 100644 (file)
--- a/arch/x86/include/asm/arch-quark/quark.h
+++ b/arch/x86/include/asm/arch-quark/quark.h
@@ -14,9 +14,29 @@
 #define MSG_PORT_MEM_MGR       0x05
 #define MSG_PORT_SOC_UNIT      0x31
 
+/* Port 0x00: Memory Arbiter Message Port Registers */
+
+/* Enhanced Configuration Space */
+#define AEC_CTRL               0x00
+
+/* Port 0x03: Host Bridge Message Port Registers */
+
 /* Host Memory I/O Boundary */
 #define HM_BOUND               0x08
 
+/* Extended Configuration Space */
+#define HEC_REG                        0x09
+
+/* Port 0x04: Remote Management Unit Message Port Registers */
+
+/* ACPI PBLK Base Address Register */
+#define PBLK_BA                        0x70
+
+/* SPI DMA Base Address Register */
+#define SPI_DMA_BA             0x7a
+
+/* Port 0x05: Memory Manager Message Port Registers */
+
 /* eSRAM Block Page Control */
 #define ESRAM_BLK_CTRL         0x82
 #define ESRAM_BLOCK_MODE       0x10000000
@@ -37,4 +57,16 @@
 /* 64KiB of RMU binary in flash */
 #define RMU_BINARY_SIZE                0x10000
 
+/* Legacy Bridge PCI Configuration Registers */
+#define LB_GBA                 0x44
+#define LB_PM1BLK              0x48
+#define LB_GPE0BLK             0x4c
+#define LB_ACTL                        0x58
+#define LB_PABCDRC             0x60
+#define LB_PEFGHRC             0x64
+#define LB_WDTBA               0x84
+#define LB_BCE                 0xd4
+#define LB_BC                  0xd8
+#define LB_RCBA                        0xf0
+
 #endif /* _QUARK_H_ */