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+* The wake up enable bit in the FVP power controller is cleared when a cpu is
+ physically powered up to prevent a spurious wake up from a subsequent cpu
+ off state.
ARM Trusted Firmware - version 0.2
==================================
bakery_lock_release(mpidr, &pwrc_lock);
}
-void fvp_pwrc_write_pwkupr(unsigned long mpidr)
+void fvp_pwrc_set_wen(unsigned long mpidr)
{
bakery_lock_get(mpidr, &pwrc_lock);
mmio_write_32(PWRC_BASE + PWKUPR_OFF,
bakery_lock_release(mpidr, &pwrc_lock);
}
+void fvp_pwrc_clr_wen(unsigned long mpidr)
+{
+ bakery_lock_get(mpidr, &pwrc_lock);
+ mmio_write_32(PWRC_BASE + PWKUPR_OFF,
+ (unsigned int) mpidr);
+ bakery_lock_release(mpidr, &pwrc_lock);
+}
+
void fvp_pwrc_write_pcoffr(unsigned long mpidr)
{
bakery_lock_get(mpidr, &pwrc_lock);
extern void fvp_pwrc_write_pcoffr(unsigned long);
extern void fvp_pwrc_write_ppoffr(unsigned long);
extern void fvp_pwrc_write_pponr(unsigned long);
-extern void fvp_pwrc_write_pwkupr(unsigned long);
+extern void fvp_pwrc_set_wen(unsigned long);
+extern void fvp_pwrc_clr_wen(unsigned long);
extern unsigned int fvp_pwrc_read_psysr(unsigned long);
extern unsigned int fvp_pwrc_get_cpu_wkr(unsigned long);
* Program the power controller to power this
* cpu off and enable wakeup interrupts.
*/
- fvp_pwrc_write_pwkupr(mpidr);
+ fvp_pwrc_set_wen(mpidr);
fvp_pwrc_write_ppoffr(mpidr);
}
break;
write_cpuectlr(ectlr);
}
+ /*
+ * Clear PWKUPR.WEN bit to ensure interrupts do not interfere
+ * with a cpu power down unless the bit is set again
+ */
+ fvp_pwrc_clr_wen(mpidr);
+
/* Zero the jump address in the mailbox for this cpu */
fvp_mboxes = (mailbox *) (TZDRAM_BASE + MBOX_OFF);
linear_id = platform_get_core_pos(mpidr);