Add cache topology info to FVP DTBs

From version 4.0 onwards, the ARM64 Linux kernel expects the device
tree to indicate the cache hierarchy. Failing to provide this
information results in the following warning message to be printed by
the kernel:

    `Unable to detect cache hierarchy from DT for CPU x`

All the FVP device trees provided in the TF source tree have been
modified to add this information.

Fixes ARM-software/tf-issues#325

Change-Id: I0ff888992e602b81a0fe1744a86151d625727511

diff --git a/fdts/fvp-base-gicv2-psci.dtb b/fdts/fvp-base-gicv2-psci.dtb
index 89318c1874f35951c1ee93c7ca6c219808045294..245a6c33b7f6ce0c45f9c7ec8f01010b850e3b69 100644 (file)
Binary files a/fdts/fvp-base-gicv2-psci.dtb and b/fdts/fvp-base-gicv2-psci.dtb differ

diff --git a/fdts/fvp-base-gicv2-psci.dts b/fdts/fvp-base-gicv2-psci.dts
index 1d26541c3a060b85c4e796a48ca50389e20a6a1d..fc343baa757981c68d45d91e550482d3308f2b57 100644 (file)
--- a/fdts/fvp-base-gicv2-psci.dts
+++ b/fdts/fvp-base-gicv2-psci.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -125,6 +125,7 @@
                        reg = <0x0 0x0>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU1:cpu@1 {
@@ -133,6 +134,7 @@
                        reg = <0x0 0x1>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU2:cpu@2 {
@@ -141,6 +143,7 @@
                        reg = <0x0 0x2>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU3:cpu@3 {
@@ -149,6 +152,7 @@
                        reg = <0x0 0x3>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU4:cpu@100 {
@@ -157,6 +161,7 @@
                        reg = <0x0 0x100>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU5:cpu@101 {
@@ -165,6 +170,7 @@
                        reg = <0x0 0x101>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU6:cpu@102 {
@@ -173,6 +179,7 @@
                        reg = <0x0 0x102>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU7:cpu@103 {
@@ -181,6 +188,11 @@
                        reg = <0x0 0x103>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
+               };
+
+               L2_0: l2-cache0 {
+                       compatible = "cache";
                };
        };
 

diff --git a/fdts/fvp-base-gicv2legacy-psci.dtb b/fdts/fvp-base-gicv2legacy-psci.dtb
index 0d176201d72dcaf4d40573220e9750ecb03dac0e..4c6f37a62c8c3e689718afd66015ec57fe99216c 100644 (file)
Binary files a/fdts/fvp-base-gicv2legacy-psci.dtb and b/fdts/fvp-base-gicv2legacy-psci.dtb differ

diff --git a/fdts/fvp-base-gicv2legacy-psci.dts b/fdts/fvp-base-gicv2legacy-psci.dts
index 58d31593289bb040025f8506b644396d101de7ab..5a7ce2f1df4d85fa4de91fd754d05bdc494ec5e5 100644 (file)
--- a/fdts/fvp-base-gicv2legacy-psci.dts
+++ b/fdts/fvp-base-gicv2legacy-psci.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -125,6 +125,7 @@
                        reg = <0x0 0x0>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU1:cpu@1 {
@@ -133,6 +134,7 @@
                        reg = <0x0 0x1>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU2:cpu@2 {
@@ -141,6 +143,7 @@
                        reg = <0x0 0x2>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU3:cpu@3 {
@@ -149,6 +152,7 @@
                        reg = <0x0 0x3>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU4:cpu@100 {
@@ -157,6 +161,7 @@
                        reg = <0x0 0x100>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU5:cpu@101 {
@@ -165,6 +170,7 @@
                        reg = <0x0 0x101>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU6:cpu@102 {
@@ -173,6 +179,7 @@
                        reg = <0x0 0x102>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU7:cpu@103 {
@@ -181,6 +188,11 @@
                        reg = <0x0 0x103>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
+               };
+
+               L2_0: l2-cache0 {
+                       compatible = "cache";
                };
        };
 

diff --git a/fdts/fvp-base-gicv3-psci.dtb b/fdts/fvp-base-gicv3-psci.dtb
index f1dc75eeb8b7cac39a82f0f5db655473a4dbd501..0acbe17e7b3187526a1c39851b297c17233988d0 100644 (file)
Binary files a/fdts/fvp-base-gicv3-psci.dtb and b/fdts/fvp-base-gicv3-psci.dtb differ

diff --git a/fdts/fvp-base-gicv3-psci.dts b/fdts/fvp-base-gicv3-psci.dts
index da090f5c32ead1216d3dfb482bbea564ca2fe5a7..5d54dbf32a8025507a7a1eb51d7cdff2fac8c59e 100644 (file)
--- a/fdts/fvp-base-gicv3-psci.dts
+++ b/fdts/fvp-base-gicv3-psci.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -123,6 +123,7 @@
                        reg = <0x0 0x0>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU1:cpu@1 {
@@ -131,6 +132,7 @@
                        reg = <0x0 0x1>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU2:cpu@2 {
@@ -139,6 +141,7 @@
                        reg = <0x0 0x2>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU3:cpu@3 {
@@ -147,6 +150,7 @@
                        reg = <0x0 0x3>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU4:cpu@100 {
@@ -155,6 +159,7 @@
                        reg = <0x0 0x100>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU5:cpu@101 {
@@ -163,6 +168,7 @@
                        reg = <0x0 0x101>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU6:cpu@102 {
@@ -171,6 +177,7 @@
                        reg = <0x0 0x102>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU7:cpu@103 {
@@ -179,6 +186,11 @@
                        reg = <0x0 0x103>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
+               };
+
+               L2_0: l2-cache0 {
+                       compatible = "cache";
                };
        };
 

diff --git a/fdts/fvp-foundation-gicv2-psci.dtb b/fdts/fvp-foundation-gicv2-psci.dtb
index e45791813acf9562a198dd8ba4fc24c772867e92..5acb139a3cc99c30314df26296bd4246b2972070 100644 (file)
Binary files a/fdts/fvp-foundation-gicv2-psci.dtb and b/fdts/fvp-foundation-gicv2-psci.dtb differ

diff --git a/fdts/fvp-foundation-gicv2-psci.dts b/fdts/fvp-foundation-gicv2-psci.dts
index 5f93daa278082170f616df6c02c7b56a3a9025f8..d5c2dfbb507c46faf21b5b11772e87b2ef03f7cb 100644 (file)
--- a/fdts/fvp-foundation-gicv2-psci.dts
+++ b/fdts/fvp-foundation-gicv2-psci.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -110,6 +110,7 @@
                        reg = <0x0 0x0>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU1:cpu@1 {
@@ -118,6 +119,7 @@
                        reg = <0x0 0x1>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU2:cpu@2 {
@@ -126,6 +128,7 @@
                        reg = <0x0 0x2>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU3:cpu@3 {
@@ -134,6 +137,11 @@
                        reg = <0x0 0x3>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
+               };
+
+               L2_0: l2-cache0 {
+                       compatible = "cache";
                };
        };
 

diff --git a/fdts/fvp-foundation-gicv2legacy-psci.dtb b/fdts/fvp-foundation-gicv2legacy-psci.dtb
index ac7555d91ec1dc00d75f0fe190746308a8cc9635..efded4434694e65e47bdb8fdf796d4a631b48751 100644 (file)
Binary files a/fdts/fvp-foundation-gicv2legacy-psci.dtb and b/fdts/fvp-foundation-gicv2legacy-psci.dtb differ

diff --git a/fdts/fvp-foundation-gicv2legacy-psci.dts b/fdts/fvp-foundation-gicv2legacy-psci.dts
index 4238b3307401abd4c94dcc0fd3039b6d39abcd80..e6e4012ff33e873ed46c5f3226ee83c910029e3d 100644 (file)
--- a/fdts/fvp-foundation-gicv2legacy-psci.dts
+++ b/fdts/fvp-foundation-gicv2legacy-psci.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -110,6 +110,7 @@
                        reg = <0x0 0x0>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU1:cpu@1 {
@@ -118,6 +119,7 @@
                        reg = <0x0 0x1>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU2:cpu@2 {
@@ -126,6 +128,7 @@
                        reg = <0x0 0x2>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU3:cpu@3 {
@@ -134,6 +137,11 @@
                        reg = <0x0 0x3>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
+               };
+
+               L2_0: l2-cache0 {
+                       compatible = "cache";
                };
        };
 

diff --git a/fdts/fvp-foundation-gicv3-psci.dtb b/fdts/fvp-foundation-gicv3-psci.dtb
index f3e0c5d3aa0b47bdb278d044f3f010b382336eab..44024369911bcec285fa92f881109857ce133aa8 100644 (file)
Binary files a/fdts/fvp-foundation-gicv3-psci.dtb and b/fdts/fvp-foundation-gicv3-psci.dtb differ

diff --git a/fdts/fvp-foundation-gicv3-psci.dts b/fdts/fvp-foundation-gicv3-psci.dts
index daad1fbcee8c3be3ea4549eeacd7a523c9d8fdf5..45c699a62de3f60376f90319f4dbad66f8183bff 100644 (file)
--- a/fdts/fvp-foundation-gicv3-psci.dts
+++ b/fdts/fvp-foundation-gicv3-psci.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -108,6 +108,7 @@
                        reg = <0x0 0x0>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU1:cpu@1 {
@@ -116,6 +117,7 @@
                        reg = <0x0 0x1>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU2:cpu@2 {
@@ -124,6 +126,7 @@
                        reg = <0x0 0x2>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
                };
 
                CPU3:cpu@3 {
@@ -132,6 +135,11 @@
                        reg = <0x0 0x3>;
                        enable-method = "psci";
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       next-level-cache = <&L2_0>;
+               };
+
+               L2_0: l2-cache0 {
+                       compatible = "cache";
                };
        };