drm/nouveau/tegra: Avoid pulsing reset twice

When the GPU powergate is controlled by a generic power domain provider,
the reset will automatically be asserted and deasserted as part of the
power-ungating procedure.

On some Jetson TX2 boards, doing an additional assert and deassert of
the GPU outside of the power-ungate procedure can cause the GPU to go
into a bad state where the memory interface can no longer access system
memory.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
index 0e372a190d3f111fc982aba65a56294b648fa368..747a775121cfbd628c8252927630199a27a34aa4 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
@@ -52,18 +52,18 @@ nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev)
        clk_set_rate(tdev->clk_pwr, 204000000);
        udelay(10);
 
-       reset_control_assert(tdev->rst);
-       udelay(10);
-
        if (!tdev->pdev->dev.pm_domain) {
+               reset_control_assert(tdev->rst);
+               udelay(10);
+
                ret = tegra_powergate_remove_clamping(TEGRA_POWERGATE_3D);
                if (ret)
                        goto err_clamp;
                udelay(10);
-       }
 
-       reset_control_deassert(tdev->rst);
-       udelay(10);
+               reset_control_deassert(tdev->rst);
+               udelay(10);
+       }
 
        return 0;