mem_protect: Add DRAM2 to the list of mem protected ranges
authorRoberto Vargas <roberto.vargas@arm.com>
Tue, 8 Aug 2017 10:27:20 +0000 (11:27 +0100)
committerRoberto Vargas <roberto.vargas@arm.com>
Mon, 25 Sep 2017 12:32:20 +0000 (13:32 +0100)
On ARM platforms, the maximum size of the address space is limited
to 32-bits as defined in arm_def.h. In order to access DRAM2, which
is defined beyond the 32-bit address space, the maximum address space
is increased to 36-bits in AArch64. It is possible to increase the
virtual space for AArch32, but it is more difficult and not supported
for now.

NOTE - the actual maximum memory address space is platform dependent
and is checked at run-time by querying the PARange field in the
ID_AA64MMFR0_EL1 register.

Change-Id: I6cb05c78a63b1fed96db9a9773faca04a5b93d67
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
include/plat/arm/common/arm_def.h
plat/arm/board/common/board_css_common.c
plat/arm/board/fvp/fvp_common.c
plat/arm/board/juno/include/platform_def.h
plat/arm/common/arm_nor_psci_mem_protect.c

index 787ccb022abbcb40c0beb2564b40bcde91e2b6ba..dbf102b888dbaaaba0cd740b868acb561985106a 100644 (file)
                                                ARM_NS_DRAM1_SIZE,      \
                                                MT_MEMORY | MT_RW | MT_NS)
 
+#define ARM_MAP_DRAM2                  MAP_REGION_FLAT(                \
+                                               ARM_DRAM2_BASE,         \
+                                               ARM_DRAM2_SIZE,         \
+                                               MT_MEMORY | MT_RW | MT_NS)
 #ifdef SPD_tspd
+
 #define ARM_MAP_TSP_SEC_MEM            MAP_REGION_FLAT(                \
                                                TSP_SEC_MEM_BASE,       \
                                                TSP_SEC_MEM_SIZE,       \
  * Required platform porting definitions common to all ARM standard platforms
  *****************************************************************************/
 
+/*
+ * We need to access DRAM2 from BL2 for PSCI_MEM_PROTECT for
+ * AArch64 builds
+ */
+#ifdef AARCH64
+#define PLAT_PHY_ADDR_SPACE_SIZE                       (1ull << 36)
+#define PLAT_VIRT_ADDR_SPACE_SIZE                      (1ull << 36)
+#else
 #define PLAT_PHY_ADDR_SPACE_SIZE                       (1ull << 32)
 #define PLAT_VIRT_ADDR_SPACE_SIZE                      (1ull << 32)
+#endif
+
 
 /*
  * This macro defines the deepest retention state possible. A higher state
index 4638af1836877713ebdfeb492e9341d528e7b984..032ebdf7ec04381b8baa9c4bcf9b1d5a86f76c39 100644 (file)
@@ -36,6 +36,9 @@ const mmap_region_t plat_arm_mmap[] = {
        CSS_MAP_DEVICE,
        SOC_CSS_MAP_DEVICE,
        ARM_MAP_NS_DRAM1,
+#ifdef AARCH64
+       ARM_MAP_DRAM2,
+#endif
 #ifdef SPD_tspd
        ARM_MAP_TSP_SEC_MEM,
 #endif
index bc033130c3fbd0f513da915e51815d658c224acb..7015ac042eaf3e19db4d15aaf6ef1f2d35362393 100644 (file)
@@ -79,6 +79,9 @@ const mmap_region_t plat_arm_mmap[] = {
        MAP_DEVICE0,
        MAP_DEVICE1,
        ARM_MAP_NS_DRAM1,
+#ifdef AARCH64
+       ARM_MAP_DRAM2,
+#endif
 #ifdef SPD_tspd
        ARM_MAP_TSP_SEC_MEM,
 #endif
index e8a4a40a807538087b1b82639d60f5f2f62788b2..c739587ddf778179902575a4eb99f7d3bfcf038f 100644 (file)
 
 #ifdef IMAGE_BL2
 #ifdef SPD_opteed
-# define PLAT_ARM_MMAP_ENTRIES         10
+# define PLAT_ARM_MMAP_ENTRIES         11
 # define MAX_XLAT_TABLES               5
 #else
-# define PLAT_ARM_MMAP_ENTRIES         9
+# define PLAT_ARM_MMAP_ENTRIES         10
 # define MAX_XLAT_TABLES               4
 #endif
 #endif
@@ -82,7 +82,7 @@
 #endif
 
 #ifdef IMAGE_BL31
-#  define PLAT_ARM_MMAP_ENTRIES                6
+#  define PLAT_ARM_MMAP_ENTRIES                7
 #  define MAX_XLAT_TABLES              3
 #endif
 
index 0f16e3529c0d684c913b20e390e7bebaf14b1fbd..c5263fd8516c449fa0e3e7ccd520e03f9bf02e86 100644 (file)
@@ -14,6 +14,9 @@
 
 mem_region_t arm_ram_ranges[] = {
        {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_SIZE},
+#ifdef AARCH64
+       {ARM_DRAM2_BASE, ARM_DRAM2_SIZE},
+#endif
 };
 
 /*******************************************************************************