arm: socfpga: Fix emac1 doesn't work on socdk board

Updated pinmux group MIXED1IO[0-13] for RGMII1.
Updated EMAC1 clock.

Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>

diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h
index 33cf1fdb64e116f3b4035d0397b3ddacda2de6eb..442b1e08627b3568d97bf0b40afdb97f6003e477 100644 (file)
--- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
+++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
@@ -72,20 +72,20 @@ const u8 sys_mgr_init_table[] = {
        0, /* GENERALIO29 */
        0, /* GENERALIO30 */
        0, /* GENERALIO31 */
-       0, /* MIXED1IO0 */
-       1, /* MIXED1IO1 */
-       1, /* MIXED1IO2 */
-       1, /* MIXED1IO3 */
-       1, /* MIXED1IO4 */
-       0, /* MIXED1IO5 */
-       0, /* MIXED1IO6 */
-       0, /* MIXED1IO7 */
-       1, /* MIXED1IO8 */
-       1, /* MIXED1IO9 */
-       1, /* MIXED1IO10 */
-       1, /* MIXED1IO11 */
-       0, /* MIXED1IO12 */
-       0, /* MIXED1IO13 */
+       2, /* MIXED1IO0 */
+       2, /* MIXED1IO1 */
+       2, /* MIXED1IO2 */
+       2, /* MIXED1IO3 */
+       2, /* MIXED1IO4 */
+       2, /* MIXED1IO5 */
+       2, /* MIXED1IO6 */
+       2, /* MIXED1IO7 */
+       2, /* MIXED1IO8 */
+       2, /* MIXED1IO9 */
+       2, /* MIXED1IO10 */
+       2, /* MIXED1IO11 */
+       2, /* MIXED1IO12 */
+       2, /* MIXED1IO13 */
        0, /* MIXED1IO14 */
        1, /* MIXED1IO15 */
        1, /* MIXED1IO16 */

diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h
index 3d621ed9c15f42ff351c8c724c40a66792ead7f8..9e336e3e81c73dcfa963cf0e107f419bb65cc8f0 100644 (file)
--- a/board/altera/cyclone5-socdk/qts/pll_config.h
+++ b/board/altera/cyclone5-socdk/qts/pll_config.h
@@ -31,7 +31,7 @@
 #define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
 #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
 #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
 #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
 #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
 #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4