#reset-cells = <1>;
};
- pcie0: pcie-controller@17010000 {
+ pcie0: pcie@17010000 {
compatible = "qca,ar7100-pci";
#address-cells = <3>;
#size-cells = <2>;
#reset-cells = <1>;
};
- pcie: pcie-controller@180c0000 {
+ pcie: pcie@180c0000 {
compatible = "qcom,ar7240-pci";
#address-cells = <3>;
#size-cells = <2>;
};
&ahb {
- pcie: pcie-controller@180c0000 {
+ pcie: pcie@180c0000 {
compatible = "qcom,ar9340-pci", "qcom,ar7240-pci";
#address-cells = <3>;
#size-cells = <2>;
reg = <0x18070000 0x4>;
};
- pcie0: pcie-controller@180c0000 {
+ pcie0: pcie@180c0000 {
compatible = "qcom,ar7240-pci";
#address-cells = <3>;
#size-cells = <2>;
reg = <0x18070000 0x58>;
};
- pcie0: pcie-controller@180c0000 {
+ pcie0: pcie@180c0000 {
compatible = "qcom,qca9550-pci", "qcom,ar7240-pci";
#address-cells = <3>;
#size-cells = <2>;
status = "disabled";
};
- pcie1: pcie-controller@18250000 {
+ pcie1: pcie@18250000 {
compatible = "qcom,qca9550-pci", "qcom,ar7240-pci";
#address-cells = <3>;
#size-cells = <2>;
status = "disabled";
};
- pcie: pcie-controller@18250000 {
+ pcie: pcie@18250000 {
compatible = "qcom,ar7240-pci";
#address-cells = <3>;
#size-cells = <2>;
+- interrupt-parent: phandle to the MIPS IRQ controller
+
+* Example for ar7100
-+ pcie-controller@180c0000 {
++ pcie@180c0000 {
+ compatible = "qca,ar7100-pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+- interrupt-controller: define to enable the builtin IRQ cascade.
+
+* Example for qca9557
-+ pcie-controller@180c0000 {
++ pcie@180c0000 {
+ compatible = "qcom,ar7240-pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+- interrupt-parent: phandle to the MIPS IRQ controller
+
+* Example for ar7100
-+ pcie-controller@180c0000 {
++ pcie@180c0000 {
+ compatible = "qca,ar7100-pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+- interrupt-controller: define to enable the builtin IRQ cascade.
+
+* Example for qca9557
-+ pcie-controller@180c0000 {
++ pcie@180c0000 {
+ compatible = "qcom,ar7240-pci";
+ #address-cells = <3>;
+ #size-cells = <2>;