* the timer is in operating mode COUNTER it stops. In mode TIMER it will
* continue to count up.
*/
-
#define RTTM_CTRL_COUNTER 0
#define RTTM_CTRL_TIMER BIT(24)
* MHz and 153.125 MHz. The greatest common divisor of all explained possible
* speeds is 3125000. Pin the timers to this 3.125 MHz reference frequency.
*/
-
#define RTTM_TICKS_PER_SEC 3125000
struct rttm_cs {
struct clocksource cs;
};
-/*
- * Simple internal register functions
- */
-
+/* Simple internal register functions */
static inline void rttm_set_counter(void __iomem *base, unsigned int counter)
{
iowrite32(counter, base + RTTM_CNT);
iowrite32(0, base + RTTM_INT);
}
-/*
- * Aggregated control functions for kernel clock framework
- */
-
+/* Aggregated control functions for kernel clock framework */
#define RTTM_DEBUG(base) \
pr_debug("------------- %s %d %08x\n", __func__, \
smp_processor_id(), (u32)base)
return (u64)rttm_get_counter(rcs->to.of_base.base);
}
-/*
- * Module initialization part.
- */
-
+/* Module initialization part. */
static DEFINE_PER_CPU(struct timer_of, rttm_to) = {
.flags = TIMER_OF_BASE | TIMER_OF_CLOCK | TIMER_OF_IRQ,
.of_irq = {
int cpu, cpu_rollback;
struct timer_of *to;
int clkidx = num_possible_cpus();
-/*
- * Use the first n timers as per CPU clock event generators
- */
+
+ /* Use the first n timers as per CPU clock event generators */
for_each_possible_cpu(cpu) {
to = per_cpu_ptr(&rttm_to, cpu);
to->of_irq.index = to->of_base.index = cpu;
}
rttm_setup_timer(to->of_base.base);
}
-/*
- * Activate the n'th+1 timer as a stable CPU clocksource.
- */
+
+ /* Activate the n'th + 1 timer as a stable CPU clocksource. */
to = &rttm_cs.to;
to->of_base.index = clkidx;
timer_of_init(np, to);