drm/i915: Don't use the second dbuf slice on icl

The code managing the dbuf slices is borked and needs some
real work to fix. In the meantime let's just stop using the
second slice.

v2: Drop the change to intel_enabled_dbuf_slices_num() (Mahesh)

Cc: Mahesh Kumar <mahesh1.sh.kumar@gmail.com>
Reviewed-by: Imre Deak <imre.deak@intel.com> #v1
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190130155110.12918-1-ville.syrjala@linux.intel.com
Reviewed-by: Mahesh Kumar <mahesh1.sh.kumar@gmail.com>

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 53b706154c94a0628cd48ea8a93bde7376315eaa..ed9786241307746c4041e971eb4355cf7b9087e1 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3822,8 +3822,13 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
 
        /*
         * 12GB/s is maximum BW supported by single DBuf slice.
+        *
+        * FIXME dbuf slice code is broken:
+        * - must wait for planes to stop using the slice before powering it off
+        * - plane straddling both slices is illegal in multi-pipe scenarios
+        * - should validate we stay within the hw bandwidth limits
         */
-       if (num_active > 1 || total_data_bw >= GBps(12)) {
+       if (0 && (num_active > 1 || total_data_bw >= GBps(12))) {
                ddb->enabled_slices = 2;
        } else {
                ddb->enabled_slices = 1;